Embedded microcontrollers and processor design:
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ [u.a.]
Prentice Hall
2010
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XX, 431 S. Ill., graph. Darst. |
| ISBN: | 9780131130418 0131130412 |
Internformat
MARC
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| 100 | 1 | |a Osborn, Greg |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Embedded microcontrollers and processor design |c Greg Osborn |
| 264 | 1 | |a Upper Saddle River, NJ [u.a.] |b Prentice Hall |c 2010 | |
| 300 | |a XX, 431 S. |b Ill., graph. Darst. | ||
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Datensatz im Suchindex
| _version_ | 1804140647151566848 |
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| adam_text | EMBEDDED MICROCONTROLLERS AND PROCESSOR DESIGN GREG OSBORN PRENTICE HALL
UPPER SADDLE RIVER, NEW JERSEY COLUMBUS, OHIO CONTENTS CHAPTER 1
EMBEDDED PROCESSORS 1.0 MICROCONTROLLERS 1 1.1 MICROCONTROLLER MARKETS 1
1.2 DATAPATH 2 1.3 COMMERCIAL MICROCONTROLLERS 2 1.4 SOC CORE PROCESSORS
2 1.5 RELATIVE SOC UNIT VOLUMES 3 1.6 VERY-LARGE-SCALE INTEGRATION
(VLSI) CHIP DESIGN TOOLS 4 1.7 INTELLECTUAL PROPERTY 4 1.8 INSTRUCTION
SET ARCHITECTURE 6 1.9 RETURN ON INVESTMENT 6 1.10 SEMICONDUCTOR
TECHNOLOGY DEVELOPMENTS 7 CHAPTER 2 MICROCONTROLLER ARCHITECTURE 2.0
COMPUTER ON A CHIP 11 2.1 JOHN VON NEUMANN 12 2.1.1 VON NEUMANN
ARCHITECTURE 12 2.2 COMPUTER ARCHITECTURES 13 2.2.1 CISC AND RISC 13 2.3
SEMICONDUCTOR TECHNOLOGY 14 2.3.1 SMALL-SCALE INTEGRATION 14 2.3.2
HARDWARE BUS 14 2.3.3 INTELLIGENT PERIPHERALS 15 2.3.4 STANDARDIZED I/O
INTERFACES 15 2.4 MSI AND LSI 16 2.5 ELECTRONIC CALCULATOR 17 2.5.1
PROGRAMMABLE CALCULATOR 17 2.6 MICROPROCESSORS 18 2.6.1
APPLICATION-ORIENTED PROCESSING 2.6.2 INTEL I4004 19 2.6.3 INTEL I8080
19 2.7 MICROPROCESSOR PERIPHERALS 20 2.7.1 MICROCOMPUTER 20 2.8 I8051
MICROCONTROLLER 21 11 18 IX X CONTENTS 2.9 RISC INTRODUCTION 22 2.9.1
RISC PROCESSORS 22 2.9.2 RISC SYNERGY 23 2.9.3 RISC MARKETING 24 2.10
FABLESS SEMICONDUCTOR COMPANY 24 2.10.1 RISC AS INTELLECTUAL PROPERTY 25
2.10.2 RISC TECHNOLOGY CURVE 25 2.11 EMBEDDED CONTROLLER IP 26 2.11.1
CISC IP 27 2.11.2 RISC IP 27 2.11.3 THIRD-PARTY IP 27 2.12 APPLICATION
SPECIFIC PROCESSORS 27 2.13 SUMMARY 28 CHAPTER 3 EMBEDDED
MICROCONTROLLER TECHNOLOGY 3.0 INTEGRATED CIRCUITS 30 3.1 MOORE S LAW 30
3.1.1 MICROPROCESSOR PERFORMANCE 31 3.1.2 ENABLING TECHNOLOGIES 32 3.1.3
AMDAHL S LAW 33 3.1.4 TECHNOLOGY CONVERGENCE 33 3.2 DESIGN ABSTRACTION
34 3.2.1 INSTRUCTION SET ARCHITECTURES 34 3.2.2 PROCESSOR FAMILY TREE 35
3.3 RISC AND CISC 35 3.3.1 PROCESSOR TECHNOLOGY 36 3.3.2 PERFORMANCE
MEASUREMENT 36 3.3.3 PROGRAM INSTRUCTIONS 36 3.3.4 COST PER INSTRUCTION
37 3.3.5 MICROCODED INSTRUCTIONS 37 3.4 MEMORY TECHNOLOGY 38 3.4.1
LOCALITY 39 3.4.2 MEMORY HIERARCHY 39 3.4.3 CACHE MEMORY 40 3.4.4 LI AND
L2 CACHE 40 3.4.5 DATA REGISTERS 41 3.4.6 INSTRUCTION QUEUES 41 3.4.7
BRANCH INSTRUCTIONS 41 3.4.8 MEMORY LATENCY 42 3.4.9 CACHE BLOCKS 42 3.5
INSTRUCTION PROCESSING 44 3.5.1 SYMBOLIC ASSEMBLY 44 3.5.2 PROGRAM
COMPILERS 45 3.5.3 HARD-CODED INSTRUCTIONS 45 3.6 PROGRAM DESIGN 45
3.6.1 PROGRAM CODE SIZE CREEP 46 3.6.2 CISC INSTRUCTION SET 46 3.7
UNIFIED INSTRUCTION SET 47 3.7.1 INDUSTRY STANDARD SOFTWARE 47 3.7.2
INSTRUCTION SET EXTENSIONS 47 3.8 RISC INSTRUCTION SET ARCHITECTURE 48
3.8.1 MICROCODE 48 3.8.2 MICRO INSTRUCTION CYCLES 48 3.8.3 APPLICATION
SPECIFIC INSTRUCTIONS 48 3.8.4 SINGLE-CYCLE INSTRUCTIONS 49 CONTENTS XI
3.9 PROCESSOR LOGIC 49 3.9.1 SYNCHRONOUS LOGIC 50 3.9.2 REGISTER SETS 50
3.9.3 ORTHOGONAL REGISTERS 50 3.9.4 REGISTER OPTIMIZATION 50 3.9.5
LOAD/STORE DATA OPERATIONS 51 3.10 PROCESSOR FUNCTIONAL PARTITIONING 51
3.10.1 INSTRUCTION PIPELINING 51 3.10.2 EXECUTION UNITS 52 3.10.3
PIPELINE STAGES 52 3.10.4 PIPELINE THROUGHPUT 53 3.10.5 SEQUENTIAL
EXECUTION 54 3.10.6 BRANCH EXECUTION 54 3.11 FIVE-STAGE PIPELINE 54
3.11.1 INSTRUCTION PIPELINE STALLS 56 3.11.2 BRANCH PREDICTION TABLE 56
3.11.3 DATA PIPELINE STALL 56 3.12 SUMMARY 56 CHAPTER 4 MICROCONTROLLER
FUNCTIONS 58 4.0 DEVICE FUNCTIONS 58 4.1 TRANSISTOR TECHNOLOGY 59 4.1.1
CMOS TRANSISTOR 59 4.1.2 CMOS POWER CONSUMPTION 60 4.1.3 PACKAGING 60
4.1.4 OPERATING TEMPERATURE RANGE 61 4.2 MEMORY TECHNOLOGIES 61 4.2.1
DRAM 62 4.2.2 SRAM 62 4.2.3 NVRWM 63 4.2.4 EEPROM 63 4.2.5 FLASH
TECHNOLOGY 64 4.2.6 ROM 64 4.3 HARDWARE FEATURES 64 4.3.1 CONFIGURATION
WORD 64 4.3.2 OSCILLATOR TYPES 65 4.3.3 RESET 66 4.3.4 STANDBY MODES 66
4.3.5 LOW-POWER CONSUMPTION 67 4.3.6 WATCHDOG TIMER 67 4.3.7 IN-CIRCUIT
PROGRAMMING 67 4.4 DATA INPUT/OUTPUT 68 4.4.1 PARALLEL I/O 68 4.4.2
TRI-STATE BIT I/O 69 4.4.3 MEMORY MAPPED I/O 69 4.5 SYNCHRONOUS SERIAL
COMMUNICATION 70 CHAPTER 5 PROGRAM DESIGN 72 5.0 PROGRAM DESIGN 72 5.1
POLLING PROGRAM 73 5.1.1 PROGRAM FLOW 73 5.1.2 PROGRAM TIMING 74 5.1.3
SEQUENTIAL TASKS 74 XII CONTENTS 5.1.4 TASK TIMING 75 5.1.5 MULTIPLE
SEQUENTIAL TASKS 76 5.2 INTERRUPTS 76 5.2.1 ASYNCHRONOUS TIMING 77 5.2.2
INTERRUPT ENABLE 77 5.2.3 MACHINE STATE 78 5.2.4 LATENCY 78 5.2.5
CONTEXT SWITCH 79 5.2.6 INTERRUPT VECTOR 79 5.2.7 NESTED INTERRUPTS 80
5.2.8 CRITICAL CODE 80 5.2.9 INTERRUPT SERVICE ROUTINE 82 5.3 REAL-TIME
OPERATING SYSTEM 82 5.4 EVENT-DRIVEN SYSTEM 83 5.5 NUCLEUS 83 5.6 SYSTEM
LAYERING 84 5.7 RISK 84 CHAPTER 6 HARDWARE/SOFTWARE DEBUG 6.0
HARDWARE/SOFTWARE DEBUG 86 6.1 COTS CONTROLLER TOOLS 87 6.2 EMBEDDED
CONTROLLER TOOLS 88 6.3 FIRST SILICON 88 6.4 BOARD-LEVEL PROBES 89 6.5
DEBUG PROCESS STEPS 90 6.5.1 SOFTWARE EDITOR 90 6.5.2 COMPILATION 91
6.5.3 PROGRAM BUILD 92 6.5.4 SIMULATOR 92 6.5.5 IN-CIRCUIT EMULATION 93
6.6 SOC DEBUG STRATEGIES 94 6.6.1 SOC SOFTWARE DEBUG 95 6.6.2 CORE-LEVEL
DEBUG 95 6.6.3 JTAG/EJTAG SPECIFICATION 6.7 ARM SOC DEBUG 96 6.8 MIPS
SOC DEBUG 98 6.8.1 EJTAG FUNCTIONS 99 CHAPTER 7 SERIAL DATA
COMMUNICATIONS 101 7.0 SERIAL DATA COMMUNICATION 101 7.1 UART 101 7.1.1
ASYNCHRONOUS MODE 102 7.1.2 TRANSMIT/RECEIVE BUFFERS 104 7.2 SPI -
SERIAL PERIPHERAL INTERFACE 105 7.3 I 2 C - INTER-IC BUS 108 7.3.1 HOW
THE I 2 C BUS WORKS 109 7.3.2 I 2 C BUS TERMINOLOGY 110 7.3.3
TERMINOLOGY FOR BUS TRANSFER 11 1 7.4 CAN*CONTROLLER AREA NETWORK 112
7.5 LIN*LOCAL INTERCONNECT NETWORK 115 7.6 I 2 S*INTER-IC SOUND 116
7.6.1 I 2 S SERIAL DATA 117 7.6.2 I 2 S WORD SELECT 117 7.6.3 I 2 S BUS
TIMING 117 86 96 CONTENTS XIII 7.7 IRDA - INFRARED DATA ASSOCIATION 118
7.7.1 IRDA STACK 119 7.8 USB - UNIVERSAL PERIPHERAL BUS 119 7.8.1 USB
TOPOLOGY 120 7.8.2 USB ARCHITECTURE 121 7.8.3 USB PHYSICAL CONNECTION
122 7.8.4 USB INTERFACE 122 7.8.5 USB 2.0 SPECIFICATION 122 7.9
BLUETOOTH 122 7.9.1 BLUETOOTH ARCHITECTURE 124 7.9.2 BLUETOOTH FREQUENCY
124 7.9.3 BLUETOOTH NETWORK 125 CHAPTER 8 ANALOG TO DIGITAL CONVERSION
127 8.0 ANALOG-TO-DIGITAL CONVERSION 127 8.1 ANALOG-TO-DIGITAL
CONVERSION OVERVIEW 127 8.2 TRANSDUCERS 129 8.3 LOW-PASS FILTER 130
8.3.1 ACTIVE FILTER 131 8.4 SAMPLING 131 8.5 SHANNON S SAMPLING THEOREM
132 8.6 WHAT IS AN ADC? 133 8.6.1 ADC CONVERTER RESOLUTION 134 8.6.2 LSB
AND MSB DEFINED 134 8.6.3 QUANTIZATION 135 8.6.4 QUANTIZATION ERROR 137
8.6.5 OFFSET ERROR 138 8.6.6 DIFFERENTIAL NONLINEARITY 139 8.6.7 MISSING
CODES 139 8.6.8 SNR*SIGNAL-TO-NOISE RATIO 140 8.7 ANALOG-TO-DIGITAL
CONVERSION ALGORITHMS 141 8.7.1 SUCCESSIVE APPROXIMATION 142 8.7.2 SAR
ADC ARCHITECTURE 142 8.7.3 FLASH ADC 145 8.7.4 INTEGRATING ADCS 146
8.7.4.1 SINGLE-SLOPE ARCHITECTURE 146 8.7.4.2 DUAL-SLOPE ARCHITECTURE
147 8.7.5 PIPELINE ADC 148 8.7.6 SIGMA-DELTA 149 8.8 OVERSAMPLING 150
CHAPTER 9 DIGITAL SIGNAL PROCESSING 153 9.0 DIGITAL SIGNAL PROCESSING
153 9.1 WHAT IS A DSP? 154 9.1.1 FILTERING AND SYNTHESIS 155 9.1.2 DSP
PERFORMANCE 155 9.1.3 ANALOG SIGNAL CONVERSION 156 9.2 DSP CONTROLLER
ARCHITECTURES 156 9.3 ANALOG FILTERS 159 9.3.1 FILTER PERFORMANCE
MEASUREMENTS 159 9.3.2 TIME DOMAIN RESPONSE 161 9.3.3 ANALOG LOW-PASS
FILTER 161 9.3.4 ACTIVE ANALOG FILTERS 162 9.3.5 ACTIVE FILTER
COMPARISON 163 XIV CONTENTS 9.4 DIGITAL FILTERS 164 9.4.1 FINITE INPUT
RESPONSE FILTER 164 9.4.2 FIR FILTER IMPLEMENTATION 166 9.4.3
CONVOLUTION 167 9.4.4 INFINITE IMPULSE RESPONSE FILTER 169 9.5 SIGNAL
TRANSFORMATION 170 9.5.1 PHASOR MODEL 170 9.5.2 FOURIER SERIES 171 9.5.3
DISCRETE FOURIER SERIES 171 9.5.4 FOURIER TRANSFORM 171 9.5.5 DISCRETE
FOURIER TRANSFORM 172 9.6 FAST FOURIER TRANSFORM 174 9.6.1 FFT
IMPLEMENTATION 174 9.6.2 DFT BUTTERFLY 175 9.7 TABLE ADDRESSING 176
CHAPTER 10 FUZZY LOGIC 10.0 FUZZY LOGIC 178 10.1 FUZZY LOGIC METHOD 180
10.2 FUZZY PERCEPTION 180 10.3 FUZZY LOGIC TERMINOLOGY 181 10.4 FUZZY
EXPERT SYSTEM 182 10.4.1 THE INFERENCE PROCESS 183 10.4.2 FUZZIFICATION
183 10.4.3 INFERENCE 184 10.4.4 COMPOSITION 184 10.4.5 DEFUZZIFICATION
185 10.5 LINGUISTIC VARIABLES 185 10.5.1 USING LINGUISTIC VARIABLES 187
10.5.2 ANATOMY OF A FUZZY RULE 188 10.5.3 LOGICALLY COMBINING LINGUISTIC
VARIABLES 10.6 PID CONTROLLER 189 10.6.1 LINGUISTIC TIME OF DAY 189
10.6.2 LINGUISTIC COMPARISONS 190 10.7 FUZZY LOGIC APPLICATION 191
10.7.1 HOW FUZZY LOGIC IS USED 191 10.8 THE RULE MATRIX 192 10.8.1 FUZZY
LOGIC IMPLEMENTATION 193 10.8.2 MEMBERSHIP FUNCTIONS 194 10.8.3 INPUT
DEGREE OF MEMBERSHIP 197 10.8.4 INFERENCING 197 10.9 DEFUZZIFICATION 198
10.9.1 FUZZY CENTROID ALGORITHM 198 10.10 TUNING AND SYSTEM ENHANCEMENT
199 CHAPTER 11 8-BIT MICROCONTROLLERS 201 11.0 GENERAL-PURPOSE
MICROCONTROLLERS 201 11.1 MICROCHIP PIC 18F4520 202 11.1.1 PIC18F4520
HARVARD ARCHITECTURE 202 11.1.2 INSTRUCTION PIPELINE 204 11.1.3 SPECIAL
FEATURES 205 11.1.4 POWER MANAGEMENT MODES 205 11.1.5 OSCILLATOR
CONFIGURATION 206 178 188 CONTENTS 11.1.6 RESET 207 11.1.7 MEMORY
ORGANIZATION 208 11.1.8 INTERRUPT STRUCTURE 210 11.1.9 INPUT/OUTPUT
PORTS 211 11.1.10 TIMER-RELATED FUNCTIONS 211 11.1.11 TIMERMODULES 212
11.1.12 CAPTURE/COMPARE/PWM FUNCTIONS 215 11.1.13 SERIAL COMMUNICATION
INTERFACE 218 11.1.13.1 MSSP 218 11.1.13.2 SPI 218 11.1.13.3 I 2 C 219
11.1.13.4 EUSART 220 11.1.14 ANALOG-TO-DIGITAL CONVERTER 222 1 1.1.15
ANALOG COMPARATOR 223 11.1.16 SPECIAL FEATURES OF THE CPU 224 11.1.17
INSTRUCTION SET 225 11.1.18 ELECTRICAL CHARACTERISTICS 225 11.2 Z1LOGZ8
ENCORE! XPF0830 SERIES 226 11.2.1 EZ8 CPU DESCRIPTION 227 11.2.2 THE Z8
ENCORE! CPU ARCHITECTURE 228 11.2.2.1 FETCH UNIT 228 11.2.2.2 EXECUTION
UNIT 228 11.2.3 ADDRESS SPACE 229 11.2.3.1 REGISTER FILE 229 11.2.3.2
PROGRAM MEMORY 230 11.2.3.3 DATA MEMORY 230 11.2.4 PERIPHERALS OVERVIEW
231 11.2.5 RESET CONTROLLER AND STOP MODE RECOVERY 233 11.2.6 LOW-POWER
MODES 233 11.2.7 GENERAL-PURPOSE INPUT/OUTPUT 234 11.2.7.1 GPIO
ARCHITECTURE 234 11.2.7.2 GPIO ALTERNATE FUNCTIONS 235 11.2.7.3 GPIO
INTERRUPTS 235 11.2.8 INTERRUPT CONTROLLER 235 11.2.8.1 MASTER INTERRUPT
ENABLE 236 11.2.8.2 INTERRUPT VECTORS AND PRIORITY 236 11.2.9 TIMERS 237
11.2.9.1 ONE-SHOT MODE 237 11.2.9.2 CONTINUOUS MODE 238 11.2.9.3
COMPARATOR COUNTER MODE 238 11.2.9.4 PWM SINGLE OUTPUT MODE 238 11.2.9.5
PWM DUAL OUTPUT MODE 238 11.2.9.6 CAPTURE MODE 239 11.2.9.7 CAPTURE
RESTART MODE 239 11.2.9.8 COMPARE MODE 239 11.2.9.9 GATED MODE 240
11.2.9.10 CAPTURE/COMPARE MODE 240 11.2.10 WATCHDOG TIMER 240 11.2.11
ANALOG-TO-DIGITAL CONVERTER 241 11.2.11.1 ADC OPERATION 242 11.2.11.2
ADC TIMING 242 11.2.12 COMPARATOR 243 I 1.2.13 FLASH MEMORY 243 11.2.14
NONVOLATILE DATA STORAGE 243 11.2.15 ON-CHIP DEBUGGER 244 XVI CONTENTS
11.2.16 OSCILLATOR CONTROL 245 11.2.16.1 CRYSTAL OSCILLATOR 245
11.2.16.2 INTERNAL PRECISION OSCILLATOR 246 11.2.17 EZ8 CPU INSTRUCTIONS
AND PROGRAMMING 247 11.2.17.1 PROGRAM STACK 247 CHAPTER 12 16-BIT
MICROCONTROLLER 250 12.0 16-BIT PROCESSOR OVERVIEW 250 12.1 FREESCALE
SI2XD PROCESSOR OVERVIEW 250 12.1.1 XGATE OVERVIEW 253 12.1.1.1 XGATE
MODULE 254 12.1.1.2 XGATE RISC CORE 255 12.1.1.3 XGATE PROGRAMMER S
MODEL 255 12.1.1.4 XGATE MEMORY MAP 256 12.1.1.5 XGATE SEMAPHORES 257
12.1.1.6 XGATE MODES OF OPERATION 257 12.1.2 CLOCKING 257 12.1.2.1 CLOCK
AND RESET GENERATOR (CRG) 258 12.1.2.2 PIERCE OSCILLATOR (XOSC) 258
12.1.3 ANALOG-TO-DIGITAL CONVENOR (ATD) 259 12.1.4 ENHANCED CAPTURE
TIMER (***) 261 12.1.4.1 FEATURES 261 12.1.5 PULSE-WIDTH MODULATOR (PWM)
262 12.1.5.1 FEATURES 263 12.1.6 INTERINTEGRATED CIRCUIT (IIC) 263
12.1.6.1 FEATURES 263 12.1.7 SCALABLE CONTROLLER AREA NETWORK (CAN) 264
12.1.7.1 FEATURES 264 12.1.7.2 CAN SYSTEM 265 12.1.8 SERIAL
COMMUNICATION INTERFACE (SCI) 265 12.1.8.1 FEATURES 265 12.1.8.2
FUNCTIONAL DESCRIPTION 266 12.1.8.3 DATA FORMATS 268 12.1.8.4 RECEIVER
268 12.1.8.5 TRANSMITTER 268 12.1.8.6 BAUD RATE GENERATOR 268 12.1.9
SERIAL PERIPHERAL INTERFACE (SPI) 269 12.1.9.1 FEATURES 269 12.1.9.2
FUNCTIONAL DESCRIPTION 271 12.1.10 PERIODIC INTERRUPT TIMER (PIT) 272
12.1.10.1 FEATURES 273 12.1.11 VOLTAGE REGULATOR (VREG) 273 12.1.11.1
FEATURES 274 12.1.12 BACKGROUND DEBUG MODULE (BDM) 274 12.1.12.1
FEATURES 274 12.1.13 INTERRUPT MODULE (XINT) 275 12.1.13.1 FEATURES 275
12.1.13.2 INTERRUPT NESTING 276 12.1.14 MAPPING MEMORY CONTROL (MMC) 277
12.1.14.1 FEATURES 277 12.1.15 DEBUG (DBG) 278 12.1.15.1 FEATURES 278
12.1.16 EXTERNAL BUS INTERFACE (XEBI) 280 12.1.16.1 FEATURES 280
CONTENTS XVII 12.1.17 PORT INTEGRATION MODULE (PIM) 280 12.1.17.1
FEATURES 282 12.1.17.2 PORT PIN 282 12.1.17.3 FUNCTIONAL DESCRIPTION 282
12.1.17.4 DATA REGISTER 282 12.1.17.5 INPUT REGISTER 283 12.1.17.6 DATA
DIRECTION REGISTER 283 12.1.18 2 KBYTE EEPROM (EETX2K) 284 12.1.18.1
FEATURES 284 12.1.18.2 FUNCTIONAL DESCRIPTION 285 12.1.18.3 EEPROM
MODULE SECURITY 286 12.1.19 512 KBYTE FLASH MODULE (FTX512K4) 286
12.1.19.1 FEATURES 286 12.1.20 SECURITY (SEC) 286 12.1.20.1 FEATURES 286
12.1.20.2 MODES OF OPERATION 288 12.1.20.3 SECURED MICROCONTROLLER 288
12.2 TEXAS INSTRUMENTS MSP430* FAMILY 288 12.2.1 LOW POWER DESIGN 291
12.2.2 FLEXIBLE CLOCK SYSTEM 291 12.2.3 MSP430CPU 292 12.2.4 OPERATING
MODES 293 12.2.5 FLL + CLOCK MODULE 293 12.2.6 FLASH MEMORY CONTROLLER
295 12.2.7 HARDWARE MULTIPLIER 295 12.2.8 DMA CONTROLLER 296 12.2.9
DIGITAL I/O 297 12.2.10 WATCHDOG TIMER 297 12.2.11 TIMERS A AND * 298
12.2.12 US ART 299 12.2.13 USCI 301 12.2.13.1 UARTMODE 301 12.2.13.2
SPIMODE 301 12.2.13.3 I 2 C MODE 303 12.2.14 ADC 12 FUNCTION 304 12.2.15
DAC12 306 12.2.16 EMBEDDED EMULATION MODULE 306 12.2.16.1 TRIGGERS 307
CHAPTER 13 INTELLECTUAL PROPERTY SOC CORES 309 13.0 SOC OVERVIEW 309
13.1 SOC DESIGN CHALLENGES 310 13.1.1 CONFIGURABLE PROCESSORS 312 13.1.2
SOC INTEGRATION 314 13.1.3 EXTENSIBLE PROCESSORS 316 13.1.4 EXTENSIBLE
PROCESSORS AS RTL ALTERNATIVES 316 13.1.5 EXPLICIT CONTROL SCHEME 317
13.2 THE MIPS32 4K PROCESSOR CORE FAMILY 318 13.2.1 KEY FEATURES OF THE
4KE FAMILY 319 13.2.2 EXECUTION UNIT 322 13.2.3 MULTIPLY/DIVIDE UNIT
(MDU) 323 13.2.4 MEMORY MANAGE UNIT (MMU) 324 13.2.5 CACHE CONTROLLER
325 13.2.6 BUS INTERFACE UNIT (BIU) 325 13.2.7 POWER MANAGEMENT 326
XVIII CONTENTS 13.2.8 INSTRUCTION CACHE 326 13.2.9 DATA CACHE 327
13.2.10 EJTAG CONTROLLER 327 13.2.11 SYSTEM COPROCESSOR 328 13.2.12
USER-DEFINED INSTRUCTIONS (UDI) 329 13.2.13 INSTRUCTION PIPELINE 329
13.2.13.1 INSTRUCTION FETCH 329 13.2.13.2 EXECUTION 329 13.2.13.3 MEMORY
FETCH 330 13.2.13.4 ALIGN 330 13.2.13.5 WRITEBACK 330 13.2.14
INSTRUCTION CACHE MISS 330 13.2.15 DATA CACHE MISS 331 13.2.16
MULTIPLY/DIVIDE OPERATIONS 331 13.2.17 BRANCH DELAY 332 13.2.18 MEMORY
MANAGEMENT 332 13.2.18.1 MMU OVERVIEW 332 13.2.19 MODES OF OPERATION 333
13.2.19.1 VIRTUAL MEMORY SEGMENTS 333 13.2.19.2 USER MODE 334 13.2.19.3
KERNEL MODE 335 13.2.19.4 DEBUG MODE 335 13.3 OVERVIEW OF THE ARM1022E
PROCESSOR 336 13.3.1 COMPONENTS OF THE PROCESSOR 337 13.3.1.1 INTEGER
UNIT 338 13.3.2 REGISTERS 338 13.3.3 INTEGER CORE 338 13.3.4 INTEGER
CORE PIPELINE 339 13.3.4.1 PREFETCH UNIT 339 13.3.4.2 LOAD/STORE UNIT
342 13.3.5 MEMORY MANAGEMENT UNIT 343 13.3.6 CACHES AND WRITE BUFFER 343
13.3.7 BUS INTERFACE 344 13.3.8 TOPOLOGY 345 13.3.9 COPROCESSOR
INTERFACE 345 13.3.10 COPROCESSOR PIPELINE 346 13.3.11 DEBUG UNIT 346
13.3.12 HALT MODE 346 13.3.13 MONITOR DEBUG-MODE 346 13.3.14 CLOCKING
AND PLL 347 13.3.15 ETM INTERFACE LOGIC 348 13.3.16 OPERATING STATES 348
13.3.17 SWITCHING STATE 350 13.3.18 SWITCHING STATE DURING EXCEPTION
HANDLING 350 13.3.19 OPERATING MODES 350 CHAPTER 14 TENSILICA
CONFIGURABLE IP CORE 352 14.0 INTRODUCTION: MOORE S LAW REVISITED 352
14.1 CHIP DESIGN PROCESS 354 14.1.1 BUILDING THE WRONG CHIP 354 14.1.2
FUNDAMENTAL TRENDS OF SOC DESIGN 355 14.1.3 A NEW SOC FOR EVERY SYSTEM
IS A BAD IDEA 356 14.1.4 NANOMETER TECHNOLOGY 357 14.1.5 SOC DESIGN
REFORM 358 CONTENTS XIX 14.1.6 SOC PROGRAMMABILITY 359 14.1.7
PROGRAMMABILITY VERSUS EFFICIENCY 360 14.1.8 THE KEY TO SOC DESIGN
SUCCESS 363 14.1.9 AN IMPROVED DESIGN METHODOLOGY FOR SOC DESIGN 364
14.1.10 THE CONFIGURABLE PROCESSOR AS A BUILDING BLOCK 365 14.1.11 RAPID
SOC DEVELOPMENT USING AUTOMATICALLY GENERATED PROCESSORS 366 14.1.12 THE
STARTING POINT: ESSENTIAL INTERFACES AND COMPUTATION 367 14.1.13
PARALLELIZING A TASK 367 14.1.14 IMPLICATIONS OF AUTOMATIC
INSTRUCTION-SET GENERATION 371 14.2 TENSILICA XTENSA ARCHITECTURE
OVERVIEW 372 14.3 PRINCIPLES OF INSTRUCTION SET DESIGN 374 14.4
TENSILICA XTENSA PROCESSOR UNIQUENESS 374 14.5 REGISTERS 375 14.6
INSTRUCTION WIDTH 376 14.7 COMPOUND INSTRUCTIONS 377 14.8 BRANCHES 378
14.9 INSTRUCTION PIPELINE 380 14.10 LIMITED INSTRUCTION CONSTANT WIDTH
381 14.11 SHORT INSTRUCTION FORMAT 381 14.12 REGISTER WINDOWS 382 14.13
XTENSA LX2 SUMMARY 383 CHAPTER 15 DIGITAL SIGNAL PROCESSORS 385 15.0 DSP
OVERVIEW 385 15.1 TMS320C55X 385 15.1.1 CHARACTERISTICS OF THE
TMS320C55X 386 15.1.1.1 MARKET SEGMENTS 387 15.1.1.2 DSP APPLICATIONS
387 15.1.2 KEY FEATURES OF THE C55X 387 15.1.3 INSTRUCTION SET
ARCHITECTURE 388 15.1.3.1 INSTRUCTION PIPELINING 389 15.1.3.2 CPU
FEATURES 389 15.1.3.3 INSTRUCTION SET 390 15.1.4 PRIMARY FUNCTIONAL
UNITS 390 15.1.4.1 INSTRUCTION BUFFER UNIT 391 15.1.4.2 PROGRAM FLOW
UNIT 393 15.1.4.3 ADDRESS DATA FLOW UNIT 395 15.1.4.4 DATA COMPUTATION
UNIT 396 15.1.5 DEVICE SPECIAL FEATURES 398 15.1.5.1 LOW-POWER
DISSIPATION 398 15.1.6 LOW-POWER DESIGN 398 15.1.6.1 MEMORY ACCESSES 398
15.1.6.2 AUTOMATIC POWER MECHANISMS 398 15.1.6.3 LOW-POWER ENHANCEMENTS
399 15.1.6.4 POWER CONSERVATION 399 15.1.6.5 IDLE DOMAINS 399 15.1.6.6
ADVANCED TECHNOLOGY 399 15.1.7 PROCESSOR ON-CHIP PERIPHERALS 400
15.1.7.1 ON-CHIP MEMORY 400 15.1.7.2 ANALOG-TO-DIGITAL CONVERTER 400
15.1.7.3 DSP CLOCK GENERATOR 401 15.1.7.4 DMA CONTROLLER 401 15.1.7.5
EXTERNAL MEMORY INTERFACE 403 15.1.7.6 I 2 C MODULE 403 CONTENTS
15.1.7.7 MULTIMEDIA/SD CARD CONTROLLER 405 15.1.7.8 PROGRAMMABLE TIMERS
405 15.1.7.9 UART 405 15.1.7.10 USB MODULE 407 15.1.8 EMULATION AND TEST
408 15.2 ANALOG DEVICES ADSP-BF535 BLACKFIN PROCESSOR 408 15.2.1
PORTABLE LOW-POWER ARCHITECTURE 409 15.2.2 SYSTEM INTEGRATION 409 15.2.3
PROCESSOR CORE 411 15.2.3.1 INSTRUCTION PIPELINE 412 15.2.3.2
INSTRUCTION PIPELINE FLOW 412 15.2.4 MEMORY ARCHITECTURE 413 15.2.4.1
INTERNAL (ON-CHIP) MEMORY 414 15.2.4.2 PCI 415 15.2.4.3 I/O MEMORY SPACE
415 15.2.5 EVENT HANDLING 415 15.2.5.1 CORE EVENT CONTROLLER (CEC) 416
15.2.5.2 SYSTEM INTERRUPT CONTROLLER (SIC) 417 15.2.5.3 INTERRUPT EVENT
CONTROL 417 15.2.6 DMA CONTROLLER 418 15.2.7 EXTERNAL MEMORY CONTROL 419
15.2.7.1 SDRAM CONTROLLER 420 15.2.8 ASYNCHRONOUS CONTROLLER 420 15.2.9
PCI INTERFACE 420 15.2.9.1 PCI HOST FUNCTIONS 420 15.2.9.2 PCI TARGET
FUNCTION 421 15.2.10 USB DEVICE 421 15.2.11 REAL-TIME CLOCK 421 15.2.12
WATCHDOG TIMER 422 15.2.13 TIMERS 422 15.2.14 SERIAL PORTS 423 15.2.15
SERIAL PERIPHERAL INTERFACE (SPI) PORTS 424 15.2.16 UART PORTS 425
15.2.17 DYNAMIC POWER MANAGEMENT 426 15.2.17.1 FULL ON OPERATING MODE
426 15.2.17.2 ACTIVE OPERATING MODE 426 15.2.17.3 SLEEP OPERATING MODE
427 15.2.17.4 DEEP SLEEP OPERATING MODE 427 15.2.18 OPERATING MODES AND
STATES 427 INDEX 429
|
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| author | Osborn, Greg |
| author_facet | Osborn, Greg |
| author_role | aut |
| author_sort | Osborn, Greg |
| author_variant | g o go |
| building | Verbundindex |
| bvnumber | BV024625124 |
| classification_rvk | ST 153 ST 170 ZN 4980 |
| ctrlnum | (OCoLC)699125198 (DE-599)GBV58318992X |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV024625124 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:03:18Z |
| institution | BVB |
| isbn | 9780131130418 0131130412 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018596881 |
| oclc_num | 699125198 |
| open_access_boolean | |
| owner | DE-83 DE-634 DE-1050 |
| owner_facet | DE-83 DE-634 DE-1050 |
| physical | XX, 431 S. Ill., graph. Darst. |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Prentice Hall |
| record_format | marc |
| spelling | Osborn, Greg Verfasser aut Embedded microcontrollers and processor design Greg Osborn Upper Saddle River, NJ [u.a.] Prentice Hall 2010 XX, 431 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 s DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018596881&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Osborn, Greg Embedded microcontrollers and processor design Eingebettetes System (DE-588)4396978-1 gnd |
| subject_GND | (DE-588)4396978-1 |
| title | Embedded microcontrollers and processor design |
| title_auth | Embedded microcontrollers and processor design |
| title_exact_search | Embedded microcontrollers and processor design |
| title_full | Embedded microcontrollers and processor design Greg Osborn |
| title_fullStr | Embedded microcontrollers and processor design Greg Osborn |
| title_full_unstemmed | Embedded microcontrollers and processor design Greg Osborn |
| title_short | Embedded microcontrollers and processor design |
| title_sort | embedded microcontrollers and processor design |
| topic | Eingebettetes System (DE-588)4396978-1 gnd |
| topic_facet | Eingebettetes System |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018596881&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT osborngreg embeddedmicrocontrollersandprocessordesign |