2001 proceedings: [May 29 - June 1, 2001], Orlando, Florida
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Piscataway, NJ
IEEE Service Center
2001
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXXIII, 1518 S. Ill., graph. Darst. |
| ISBN: | 0780370384 |
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Datensatz im Suchindex
| _version_ | 1804140480882016256 |
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| adam_text | SEPTEMBER 25-26, 2001 VMC CATALOG NO. R 01 BVHC - 300 SANTA CLARA
MARRIOTT HOTEL SANTA CLARA, CA 2001 EEDINGS EIGHTEENTH INTERNATIONAL
VLSI MULTILEVEL INTERCONNECTION CONFERENCE (VMIC) A SPECIALTY CONFERENCE
OF ICROELECTFIONICS INTBR- ONNECTION TOC LIBRARY OF CONGRESS NO.
89-644090 UB/TIB HANNOVER 89 123 842 921 EIGHTEENTH INTERNATIONAL VLSI
MULTILEVEL INTERCONNECTION CONFERENCE SEPTEMBER 25 -26, 2001 ADVANCE
PROGRAM TUESDAY, SEPTEMBER 25, 2001 OPENING SESSION * 9 A.M. WELCOMING
REMARKS BY THE GENERAL CHAIRMAN DR. THOMAS E. WADE UNIVERSITY OF SOUTH
FLORIDA SESSION I *9:15 A.M. ON - CHIP OPTICAL INTERCONNECTS DR. JURGEN
MICHEL MICROPHOTONICS CENTER MASSACHUSETTS INST. OF TECHNOLOGY
CAMBRIDGE, MASSACHUSETTS COFFEE BREAK 9:45 - 10:00 A.M. SESSION H -10:00
A.M. -12:00 P.M. VLSI MULTILEVEL INTERCONNECTION CONDUCTOR CHAIRMAN:
PARTI DR. DONALD S. GARDNER INTEL CORP. SANTA CLARA, CA. 2.A FILL OF
0.35 MICRON CONTACT STRUCTURES USING SILVER FORCEFILT BY M.G.M. HARRIS,
P. RICH AND N. RIMMER; TRIKON TECH.; NEWPORT, UNITED KINGDOM. 17 2.B
IN-SITU MONITORING OF COPPER - DAMASCENE ELECTRO- CHEMICAL PLATING
SOLUTIONS BY P. M. ROBERTSON, ATMI; SAN JOSE, CA. 22 (INVITED PAPER)
2.C THE OPTIMUM CONTENT OF MG IN ELECTROLESS SILVER PLATING FOR
MICROELECTRONIC INTERCONNECTION BY H.H. PARK, S. H. CHA; SEOUL NAT L
UNIV.; SEOUL, KOREA; CD. LEE, JJ. KIM; LG PHILLIPS LCD; KYONG, KOREA. 30
2.D VOID-FREE CU FILLING OF 0.05 TO 0.10 MICRON INTER- CONNECTIONS BY
JETS-ECD BY U. COHEN; JETS TECHNOLOGY; SANTA CLARA, CA. 36 2.E
COMPARISON OF OPTIONS FOR SUB 0.10 MICRON GENERATION DAMASCENE COPPER
FEATURE FILL BY E. WEBB, J. SUKAMTO, J. REID; NOVELLUS SYSTEMS;
WILSONVILLE, OR; T ANDRYUSHCHENKO; INTEL; HILLSBORO, OR; M. DANEK, E.
KLAWUHN, R. ROZBICKI, G. ALERS, T. SUWWAN DE FELIPE; NOVELLUS; SAN JOSE,
CA; K. PHEIFER; SEMATECH; AUSTIN, TX.;V. BHASKARAN; KLA-TENCOR; SAN
JOSE, CA.; A. FRANK; TEXA S INSTRUMENTS; DALLAS, TX. 42 (INVITED PAPER)
2.F THE ENHANCEMENT OF ADHESION STRENGTH, REDUCTION OF STRESS AND
SUPPRESSION OF AGGLOMERATION IN ULSI COPPER INTERCONNECTION BY T. HARA;
HOSEI UNIVERSITY; TOKYO, JAPAN. 53 (INVITED PAPER) 2.G STRESS FREE
COPPER ELECTROPOLISHING BY P.H. YIH, D. H. WANG, S. H. CHIAO; ACM
RESEARCH; FREMONT, CA. 59 * POSTER PAPERS* 74 2.H DEUTERIUM POST -
METALLIZATION ANNEAL OF COPPER FILM BY Y.L. WU, Y. C. HUANG; NAT L
CHI-NAN UNIV.; TAIWAN, R.O.C:; J.K. LAN AND Y.L. WANG; T.S.M.C; TAIWAN,
R.O.C. 65 2.1 THE IMPACT ON TUNGSTEN DEPOSITION UNIFORMITY DUE TO
COLLAPSE OF THE PURGE RING ON WXZ TUNGSTEN HEATERS BY M. GONSALVES, A.
SIDHWA, K. DENNIS, T. GANDY, C. SPINNER; ST MICROELECTRONICS; PHEONIX,
AZ. 68 2.J SIH 4 POST FLOW EFFECT BETWEEN TUNGSTEN CHEMICAL VAPOR
DEPOSITED NUCLEATION PROCESS AND BULK DEPOSITION PROCESS BY W. P. CHIU,
C. S. HUANG AND B.R. NI; PROMOS TECH.; TAIWAN, R.O.C. 71 2.K DEPOSITION
OF LOW STRESS AND LOW RESISTIVITY COPPER CONDUCTIVE LAYERS BY
ELECTROPLATING EMPLOYING COPPER- HEXAFLUORO-SILICATE ELECTROLYTIC
SOLUTION B Y T. HARA, K. MIYAZAWA; HOSEI UNIV.; TOKYO, JAPAN; AND M.
MIYAMOTO, T. YONEZAWA, S. ISHIDA; MORITA CHEMICAL; OSAKA, JAPAN. SESSION
HI - 12:45 - 2:00 P.M. VLSI MULTILEVEL INTERCONNECTION POSTER PAPER /
EXHIBITION DEDICATED VIEWING TIME SESSION IV - 2:00 - 3:45 P.M. VLSI
MULTILEVEL INTERCONNECTION VMI CMP PROCESSES CHAIRMAN: DR. MANSOUR
MOINPOUR INTEL CORP. SANTA CLARA, CALIFORNIA CMP CHARACTERIZATION 4.A
REDUCING CMP PROCESS CYCLE TIME WHILE MAINTAINING YIELD WITH AUTOMATED
PROCESS CONTROL BY J. MOYNE, A. CHENG; UNIV. OF MICHIGAN; ANN ARBOR,
MI; J. COLT, J. CHAPPLE-SOKOL, R. NADEAU, P. SMITH; IBM MICRO-
ELECTRONICS; ESSEX JET., VT.; AND B. VAN ECK; INT L SEMATECH; AUSTIN,
TX. 81 (INVITED PAPER) 4.B NANO-TOPOGRAPHY AFFECTS ON CMP PLANARIZATION
PERFORMANCE BY M. TSUJIMURA; EBARA; TOKYO, JAPAN. 91 (INVITED PAPER)
4.C QUANTITATIVE FUNCTIONAL TESTING ON CMP MATERIALS USING A BENCH-TOP
CMP TESTER WITH MULTIPLE SENSORS BY N. GITIS, M. VINOGRADOV; CENTER FOR
TRIBOLOGY; CAMPBELL, CA. 98 --POSTER PAPER * 4.D PRELIMINARY STUDY OF
ENDPOINT DETECTION FOR CHEMICAL MECHANICAL PLANARIZATION PROCESSES USING
ACOUSTIC EMISSION BY H. HOCHENG, Y. L. HUANG; NAT L TSING HUA UNIV;
TAIWAN, R.O.C. 107 CMP MODELINC & SIMULATION 4.E MODELING OF PATTERN
DEPENDENCIES IN ABRASIVE-FREE COPPER CHEMICAL MECHANICAL POLISHING
PROCESSES BY T. TUGBAWA, T. PARK, B. LEE, D. BONING; M. I. T.;
CAMBRIDGE, MA.; P. LEFEVRE; INT L SEMATECH; AUSTIN, TX.; AND J. NGUYEN;
SPEEDFAM-IPEC, PHOENIX. AZ. 113 (INVITED PAPER) 4.F NUMERICAL ANALYSIS
TO STUDY THE EFFECT OF TURBULENCE ON THE PARTICLES IN CHEMICAL
MECHANICAL PLANARIZATION PROCESSES BY W. JENG; ASIA IC; TAIWAN, R.O.C;
AND J. J. YEUAN, S.H. LIN; FENG CHIA UNIV.; TAIWAN, R.O.C. 123 4.G A
MULTISCALE CONTACT MECHANICS AND HYDRODYNAMICS MODEL OF CHEMICAL
MECHANICAL POLISHING BY A.T. KIM, J.SEOK, J.A. TICHY, T. S. CALE;
RENSSELAER; TROY, N.Y. 129 * POSTER PAPERS * 4.H ANTI-LUBRICATING
BEHAVIOR OF COPPER CMP BY H. LIANG, G.H. XU; UNIV OF ALASKA; FAIRBANKS,
AK. SESSION V - 4:00 - 5:00 P.M. VLSI MULTILEVEL INTERCONNECTION
BARRIERS/CONTACT/ADHESION LAYERS & DIELECTRICS 137 CHAIRMAN: DR. NEIL H.
HENDRICKS ATMI MATERIALS SAN JOSE, CALIFORNIA BARRIER/CONTACT/ADHESION
5.A AN EFFECTIVE TECHNOLOGY USING SICN / FSG STRUCTURES FOR DUAL
DAMASCENE COPPER PROCESS BY N. MIURA, J. NOGUCHI, K. OOMORI, T. JIMBO,
H. AOKI AND T. TAMARU; HITACHI; TOKYO, JAPAN. 143 147 5.B DEPOSITION
AND CHARACTERIZATION OF IONIZED PVD TA AND TAN BARRIER FILMS FOR COPPER
INTERCONNECTS BY S.R. BURGESS, K. BUCHANAN, J. CRESSWELL, I. MONCRIEFF;
TRKON TECH.; NEWPORT, SOUTH WALES 5.C CRITICAL CHALLENGES AND NEWLY
EMERGING DIRECTIONS IN DIFFUSION BARRIER TECHNOLOGY FOR THE 100 NM NODE
AND BEYOND BY G. RAMANATH, M. STUKOWSKI, H. KIM, M.J, FREDERICK, X.
GUO; RENSSELAER POLYTECH; TROY, N 153 (INVITED PAPER) * POSTER
PAPERS * 5.D CVD / PVD COPPER SEED LAYER FOR SUB 0.10 MICRON
INTECONNECTS BY U. COHEN; U.C. CONSULTING; PALO ALTO, CA. 5.E
INFLUENCE OF SPUTTERING TOOL ON TI THIN FILM FORMATION BY C.F. LO, C.
TSAI, P. GILMAN; PRAXAIR SURFACE TECH; NEW YORK, N.Y.; AND B. WANG;
U.M.C.; TAIWAN, R.O.C. 165 168 DIELECTRIC SYSTEMS 5.F A NOVEL METHOD TO
FORM POROUS CVD OXIDE FILM B Y C.T. NI, E. SU, A. LIU AND K. TSAI; T.
S. M .C. ; TAIWAN, R.O.C. I 73 * POSTER PAPERS * 5.G METROLOGY FOR
CONTROL OF NEAR-PLANAR SHALLOW TRENCH ISOLATION STRUCTURES VIA ATOMIC
FORCE MICROSCOPY BY M.E. LAGUS; IBM MICROELECTRONICS; HOPEWELL JET.;
N.Y. AND S.M. HAND; DIGITAL INST; SANTA BARBARA, CA. 181 5.H
DEVELOPMENT OF A HIGH DEPOSITION RATE PROCESS FOR BOROSILICATE GLASS
FILMS BY M. PATEL AND S. GOVINDARAJAN; INFINEON TECH; RICHMOND, VA. 184
5.1 METHOD TO REDUCE HDP OXIDE THICKNESS VARIATIONS AT NARROW AND WIDE
TRENCHES BY T.P. LEE AND C. JANG; MOSEL VITELIC; SAN JOSE, CA. 187 5.J
ELECTRICAL CHARACTERISTICS OF METHYL-DOPED CVD LOW-K DIELECTRICS BY
L.J. LI, C.C. KO, T.I. BAO, Y.C. LU, S.M. JANG, C.H. YU AND M.S. LIANG;
T. S. M. C; TAIWAN, R.O.C. 5.K OPTIMIZATION OF REMOTE PLASMA CLEAN FOR
SACVD BPSG AND BSG PROCESS BY A. JAIN; UNIV. OF VIRGINIA;
CHARLOTTESVILLE, VA; AND S. GOVINDARAJAN; INFINEON TECH.; SANDSTON, VA.
SESSION VI - 5:00 - 5:45 P.M. VLSI MULTILEVEL INTERCONNECTION CMP STI &
DL L 190 193 CHAIRMAN: DR. PETER BURKE LSI LOGIC GRESHAM, OREGON 6. A
DESIGN OF EXPERIMENTS METHODS USED FOR CHEMICAL MECHANICAL
PLANARIZATION OF SHALLOW TRENCH ISOLATION FOR A MULTI-RESPONSE SYSTEM
BY L. TINOCO; INTEL; PORTLAND, OR; AND M. MELLOCH; PURDUE UNIV.; W.
LAFAYETTE, IN. 199 6.B HIGH SELECTIVITY SLURRY FOR STI CMP BY E. S.
OSWALD, R. HER; FERRO ELECTRONIC MAT L; PENN YAN, N.Y. 205 6.C CHEMICAL
MECHANICAL POLISHING OF COPPER-POROUS LOW-K FILMS: SINGLE DAMASCENE
SCHEMES AND RELATED ISSUES BY K. WIJEKOON, Y. MOON, F. REDEKER, A.
DEMOS, N. BEKIARIS AND T. WEIDMAN; APPLIED MATERIAL; SANTA CLARA, CA.
211 * POSTER PAPERS * 6.D TUNABLE SLURRIES FOR INTEGRATION OF COPPER
WITH SILK AND POROUS SILK DIELECTRIC FILMS BY J. HAWKINS, S. WANG, G.
GROVER, M. PETERSON, J. CHAMBERLAIN; CABOT MICRO-ELECTRONICS; AURORA,
IL.; AND M. SIMMONDS, G. MYERS; DOW CHEMICAL; MIDLAND, MI. 217 6.E
GLOBAL PLANARIZATION OF DIRECT STI-CMP PROCESS USING HIGH SELECTIVITY
SLURRY BY C.B. KIM, , S.Y. JEONG, Y. J. SEO; DAEBUL UNIV.; CHONNAM,
KOREA; AND S.Y. KIM; ANAM SEMI; KOREA. 222 6.F CHEMICAL MECHANICAL
POLISHING OF COPPER - CVD LOW-K FILMS: A COMPARISON OF SELECTIVE AND
NON-SELECTIVE PROCESSES BY K. WIJEKOON, Y. MOON, F. REDEKER, T. PAN, M.
NAIK AND L.Q. XAI; APPLIED MATERIALS; SANTA CLARA, CA. 22S 6.G
OPTIMIZATION OF POLISHING PAD SET FOR DIRECT STI-CMP APPLICATIONS BY
S.W. PARK, Y.J. SEO; DAEBUL UNIV.; KOREA.; S.Y. KIM; ANAM SEMI; KOREA.
6.H DIRECT POLISH STI WITH REFLEXION FIXED ABRASIVE WEB BY A.
NICKLES, G. LEUNG, V. MOHAN, H. TARN, P. MCREYNOLDS, G. PRABHU AND T.
OSTERHELD; APPLIED MATERIALS; SANTA CLARA, CA. WEDNESDAY, SEPTEMBER 26,
2001 SESSION VH - 8:00 - 9:15 A.M. VLSI MULTILEVEL INTERCONNECTION IC
PACKAGING) TRENDS &CHALL 230 233 CHAIRMAN: DR. JOEL J. CAMARDA KULICKE &
SOFFA INDUSTRIES MILPITAS, CALIFORNIA 7.A PACKAGING CHALLENGES OF MEMS
COMPONENTS BY T.C. CHAI, C.S. PREMACHANDRAN, S.C. CHONG, M.K. IYER;
INST. OF MICROELECTRONICS; SINGAPORE. 239 7.B TEST AND WIREBOND
CHALLENGES FOR FINE PITCH, LOW-K DIELECTRIC AND COPPER WAFERS BY J.
KISTER, F. KELLER AND M.G. OSBORNE; KULICKE & SOFFA; MILPITAS, CA. 245
7.C WAFER PROCESS OF THROUGH ELECTRODE IN SI WAFER USING COPPER
DAMASCENE FOR THREE DIMENSIONAL SYSTEM IN A PACKAGE BY M. HOSHINO, H.
YONEMURA, M. TOMISAKA, T. FUJII, M. SUNOHARA, K. TAKAHASHI; ASET.;
IBARAKI, JAPAN 250 7.D PACKAGING COPPER BASED SEMICONDUCTORS
(ELECTROLESS- NICKEL/GOLD FOR SOLDER BUMPING AND WIREBONDING) BY A.J.G.
STRANDJORD, S. POPELAR, CA. ERICKSON; I.C. INTER- CONNECT: COLORADO
SPRINGS, CO. 255 * POSTER PAPERS * 7.E RAPID RELIABILITY ASSESSMENT OF
ULSI ELECTRONICS BY P. MCCLUSKEY; UNIV. OF MARYLAND; COLLEGE PARK, MD.
263 7.F A NEW CONCEPT ON LOW COST PLASTIC PACKAGING FOR GHZ DEVICES BY
K. SEYAMA, S. KIKUCHI, M. NISHIHARA, H. YAMAMOTO; FUJITSU LTD; KANAGAWA,
JAPAN. 266 7.G STRUCTURE, CHARACTERIZATION AND RELIABILITY OF THICK
FIHN CAPACITORS EMBEDDED HI THE LOW TEMPERATURE COFIRED CERAMICS (LTCC)
BY S.C. LIN, Y.T. CHEN AND S.Y. CHANG; I.T.R.S.; TAIWAN, R.O.C. 269
SESSION VFFL - 9:30 A.M.-12:00 P.M. VLSI MULTILEVEL INTERCONNECTION CMP
CONSUMABLES & CONDUCTOR PROCESSES CHAIRMAN: DR. DALE HETHERINGTON SANDIA
NAT L LABS ALBUQUERQUE, NEW MEXICO CMP CONSUMABLES 8.A EFFECT OF
TEMPERATURE ON THERMOANALYTICAL PROPERTIES OF POLISHING PADS BY A.
TREGUB, M. MOINPOUR AND J. SOROOSHIAN; INTEL CORP; SANTA CLARA, CA. 275
8.B OPTIMIZATION OF CHEMICAL MECHANICAL PLANARIZATION FROM THE
VIEWPOINT OF CONSUMABLE EFFECTS BY J. LUO AND D. DORNFELD; UNIV. OF
CALIFORNIA; BERKELEY, CA. 281 (INVITED PAPER) 8.C SURFACTANT BEHAVIOR
AND STUDY IN SLURRY BY B.T. LIN, C.S. CHEN, W.K. YEH, S.N. PENG; TSMC;
TAIWAN, R.O.C. 290 8.D EVALUATION OF ALUMINA/SILICA MIXED ABRASIVE
SLURRY FOR CMP OF COPPER AND TANTALUM BY A. JINDAL, S. HEGDE AND S.V.
BABU; CLARKSON UNIV.; POTSDAM, N.Y. 297 (INVITED PAPER) 8.E TRIBOLOGY,
FLUID DYNAMICS AND REMOVAL RATE CHARACTERIZATION OF NOVEL SLURRIES FOR
ILD POLISH APPLICATIONS BY A. PHILIPOSSIAN; UNIV. OF ARIZONA/ INTEL
CORP; TUCSON, AZ.; C. ROGERS, J. LU; TUFTS UNIV.; MEDFORD, MA. 307
(INVITED PAPER) * POSTER PAPERS * 8.F SURFACTANT INTERACTION WITH
COPPER CMP SLURRIES BY S. SUNDARAM, X. GAO, U.R. MURRAY, C.S. MAGEE,
R.K. PINSCHMIDT; AIR PRODUCTS & CHEMICALS; ALLENTOWN, PA; J.A. SIDDIQUI;
DUPONT AIR PRODUCTS; TEMPE, AZ 321 8.G CONCENTRATION LIMITS WHEN
MEASURING CMP SLURRIES USING A NON-INVASIVE BACK SCATTERING WITH CELL
POSITION CONTROL BY J. WESTBROOK, X. SHI, P. DAVIS AND Y. LI; CLARKSON
UNIV.; POTSDAM, N.Y. 324 8.H CHEMICAL MECHANICAL POLISHING USING A
LUBRICATING BOUNDARY LAYER BY C.J. MOLNAR; BEAVER CREEK CONCEPTS;
WILMINGTON, DE. 328 CMP CONDUCTOR PROCESSES 8.1 PLATINUM CHEMICAL
MECHANICAL POLISHING FOR FRAM FABRICATION BY H. WANG, R. SCHMIDT, C. YE
AND S. LANE; RODEL; NEWARK, DE. 8. J COPPER CMP FOR ULTRA LOW-K
INTENNETAL DIELECTRIC BY T. SHIH, C.W. CHUNG, S.N. LEE, S.M. JANG, C.H.
YU AND M.S. LIANG; TSMC; TAIWAN, R.O.C. (INVITED PAPER) 8.K DIRECT
OBSERVATION OF INTERACTIONS BETWEEN COPPER AND POLYURETHANE SURFACES DUE
TO FRICTION BY H.LIANG; UNIV. OF ALASKA; FAIRBANKS, ALASKA; AND T.
LEMOGNE, J.M. MARTIN; ECOLE CENTRALS DE LYON; LYON, FRANCE. 7 333 338
342 8.L COPPER/LOW-K DIELECTRIC CMP WITH LINEAR PLANAR- IZATION
TECHNOLOGY BY A. J. JIN, S. SRIVATSAN, S. JEW, K. Y. RAMANUJAM, P.
CHENG, R. KISTLER; LAM RESEARCH; FREMONT, CA. 345 * POSTER PAPERS *
SESSION X - 2:00 - 4:35 P.M. VLSI MULTILEVEL INTERCONNECTION MODELLING &
SIMULATIONS CHAIRMAN: 8.M CHEMICAL MECHANICAL POLISHING OF COPPER/LOW-K
DUAL DAMASCENE BY C.W. CHUNG, T. SHIH, S.M. JANG, C.H. YU AND M.S.
LIANG; TSMC; TAIWAN, R.O.C. 8.N EVALUATION OF POLISHHIG PADS AND
SLURRIES FOR TUNGSTEN DAMASCENE CMP BY K.C. WU, D. LUI AND C.H. CHEN;
MOSEL-VRRELIC; SAN JOSE, CA.; AND B. KOUTNY, G. LOU, I. GILBOA AND S.
GEHA; CYPRESS SEMI.; SAN JOSE, CA. 2001 VMIC A WARDS LUNCHEON WEDNESDAY,
SEPTEMBER 26; 12:00 -1:00 P.M. (ONLY 250 TICKETS SOLD, FIRST COME-FIRST
SERVED BASIS) AWARDS LUNCHEON PRESENTATION TTRS PACKAGING ROADMAP IN THE
ERA OF COPPER/LOW-K ON-CHIP INTERCONNECT 365 DR. CHI SHIH CHANG KULICKE
& SOFFA MILPITAS, CALIFORNIA OUTSTANDING PAPER & POSTER PRESENTATIONS
THE OUTSTANDING PAPER AWARD FOR VMIC 2000 IS PRESENTED TO THE PAPER
ENTITLED 3D MKROSTRUCTURAL SIMULATION OF THIN FILM DEPOSITION FOR VLSI
INTERCONNECTS BY T. SMY; CARLETON UNIV; ALBERTA, CANADA; S.K. DEW AND
M.J. BRETT; UNIV. ALBERTA; EDMONTON, CANADA. THE OUTSTANDING POSTER
PAPER AWARD FOR VMIC 2000 IS PRESENTED TO THE POSTER PAPER ENTITLED
ELIMINATION OF JUNCTION SPIKING PROBLEMS BY USING PRE- CLEAN ETCH AND
TWO STEP TIN DURING CONTACT BARRIER DEPOSITION PROCESS BY A. SIDHWA, C.
SPINNER, T. GRADY, S. GUISINGER; ST MICROELECTRONICS; PHOENIX, AZ.
CONGRATULATIONS TO 2000 VMIC RECIPIENTS. THEY WILL BE BOTH RECOGNIZED
AND PRESENTED WITH A CERTIFICATE/CHECK AT THIS YEARS VMIC AWARDS
LUNCHEON. DR. VALERIY SUKHAREV LSI LOGIC CORP. SANTA CLARA, CALIFORNIA
353 357 10.A NEW METHODOLOGIES FOR THE INTERCONNECT RELIABILITY
ASSESSMENTS OF INTEGRATED CIRCUITS BY S. P. HAU-RIEGE, C.S. HAU-RIEGE;
INTEL CORP; HILLSBORO, OR.; AND C.V. THOMPSON, V.K. ANDLEIGH, Y. CHERY,
D. TROXEL; M. I. T.; CAMBRIDGE, MA. (INVITED PAPER) 10.B SUPERCONFORMAL
ELECTRODEPOSITION HI SUBMICRON FEATURES BY D. JOSELL, D. WHEELER AND
T.P. MOFFAT; NIST.; GAITHERSBURG, MD. 10.C ELECTROMIGRATION RESISTANT
MULTILEVEL INTERCONNECTION WITH INTERMETAL DIELECTRIC AH- GAPS BY V.
SUKHAREV, B.P. SHIEH, R. CHOUDHURY, C W. PARK; LSI LOGIC; SANTA CLARA,
CA. 10.D INTEGRATED MULTISCALE SIMULATION OF COPPER ELECTRO- CHEMICAL
DEPOSITION B Y M. O. BLOOMFIELD, S. SEN, K. E. JANSEN AND T.S. CALE;
RENSSELAER POLYTECH.; TROY, N.Y. (INVITED PAPER) 10.E OPTIMUM
INTERCONNECT DESIGN FOR ASIC CHIPS BY P. ZARKESH-HA, B. LOH, P. BENDIX;
LSI LOGIC; MILPITAS, CA; AND J. C. MEINDL; GEORGIA TECH; ATLANTA, GA.
10.F A FEATURE SCALE MODEL FOR ATOMIC LAYER DEPOSITION BY M.K.
GOBBERT; UNIV. OF MARYLAND; BALTIMORE, MD.; AND V. PRASAD, M.O.
BLOOMFIELD AND T.S. CALE; RENSSELAER POLYTECH; TROY, N.Y. * POSTER
PAPERS * 10.G MODELING AND SIMULATION OPPORTUNITIES FOR 3D INTEGRATED
CIRCUITS BY V. PRASAD, M.O. BLOOMFIELD, J. LU, O. KLAAS, A. MANIATTY,
Y. LECOZ, R.B. IVERSON AND T.S. CALE; RENSSELAER POLYTECH; TROY, N.Y.
10.H PROCESS CAPABILITY OPTIMIZATION BY J. J. FLAIG; APPLIED TECH; SAN
JOSE, CA. 375 385 391 397 407 413 421 426 10.1 A NEW DIRICHLET-NEUMANN
RANDOM-WALK ALGORITHM FOR ELECTROMAGNETIC ANALYSIS OF IC INTERCONNECTS:
ID VERIFICATION, MATERIALLY HOMOGENEOUS DOMAINS BY K. CHATTERJEE, R.B.
IVERSON AND Y.L. LECOZ; RENSSELAER POLYTECH; TROY, N.Y. 429 SESSION IX -
1:00 - 2:00 P.M. VLSI MULTILEVEL INTERCONNECTION POSTER PAPER /
EXHIBITION DEDICATED VIEWING TIME CONDUCTOR SYSTEMS - PART II 10.J
FAST, IN-LINE COPPER METROLOGY USING OPTOACOUSTICS BY M. GOSTEIN, J.
TOWER; PHILIPS ANALYICAL; NATICK, MA. (INVITED PAPER) 435 8 10.K DESIGN
AND FABRICATION OF DAMASCENE PATTERNED INTERCONNECTIONS FOR
FACE-TO-FACE WAFER BONDED 3D- STACKED IC TEST STRUCTURES BY J.Q. LU,
O. ERDOGAN, Y. KWON, P. BELEMJIAN, G. RAJAGOPALAN, D.L. BAE, C.K. HONG,
M. GUPTA, J.M. MCMAHON, J. MAYEGA, R.P. KRAFT, T.S. CALE, J.F. MCDONALD
AND R.G. GUTMANN; RENSSELAER POLYTECH; TROY, N.Y. 442 (INVITED PAPER)
10.L EXTENDING COPPER ELECTROPLATING TO 0.035 MICRON MANUFACTURE NODE
BY P.H. YIH, D.H. WANG AND S.H. CHIAO; ACM RESEARCH; FREMONT, CA. 451 *
POSTER PAPERS * 10.M CO-SUPPRESSION BEHAVIOR OF POLYETHYLENE GLYCOL AND
CHLORIDE ION AT COPPER ELECTRODEPOSITION BY Y. S. KIM, S.K. KIM AND
J.J. KIM; SEOUL NAT L UNIV; SEOUL, KOREA. 459 10.N ETCHING AND CLEANING
AT THE BEVEL AND SIDE-WALL BY CHEMICAL SPIN ETCHING IN COPPER
INTERCONNECTION SI WAFER BY T. HARA, T. TANIGUCHI; HOSEI UNIV.; TOKYO,
JAPAN; K. KINOSHITA; SEZ JAPAN; TOKYO, JAPAN; H.Q. LI, J. TAKAMURA;
RAYTEX; TOKYO, JAPAN; AND T.C. BRISTOW; CHAPMAN INSTRUMENTS; ROCHESTER,
MA. 462 SESSION XI - 4:35 - 5:55 P.M. VLSI MULTILEVEL INTERCONNECTION
RELIABILITY & CMP PROCESSES CHAIRMAN: DR. LOREN W. LINHOLM NAT L INST.
OF STD & TECH. (NIST) GAITHERSBURG, MARYLAND RELIABILITY ISSUES 11. A
TEMPERATURE ACCELERATED THICKNESS DEPENDENCE SOFT BREAKDOWN OF ULTRA
LOW-K THIN FILMS BY S.W. LEE, H. KIM, F.G. SHI; UNIV. OF CALIFORNIA;
IRVINE, CA; AND B. ZHAO; CONEXANT SYSTEMS; NEWPORT BEACH, CA. 467
(INVITED PAPER) LL.B EFFECTS OF COPPER DIFFUSION ON MOSFET ELECTRICAL
PROPERTIES BY C ZHU, W.J. YOO, D.P.P. TAN, S.Y. LIM, B.J. CHO; NAT L
UNIV. OF SINGAPORE; SINGAPORE. 487 LL.C IMPACT OF MODULE INTEGATION ON
COPPER DUAL DAMASCENE DEFECTIVITY MECHANISMS BY A.R. SETHURAMAN, S.A.
KEKARE AND R. YANG; KLA-TENCOR; SAN JOSE, CA. 491 (INVITED PAPER) *
POSTER PAPERS * LL.D THE IMPACT OF THE ABNORMAL ALCU GRAM GROWTH ON
THICK METAL INTERCONNECT LINES USED FOR WIRELESS CHIPSET BY A. SIDHWA,
C. SPINNER, M. KALAGA AND T. GANDY; ST MICROELECTRONICS; PHOENIX, AZ.
501 LL.E SPIDER LIKE DEFECT CORRELATED WITH TUNGSTEN POLYCIDE BY J.
HSIEH, C.S. HUANG, W.P. CHIU; PROMOS TECH; TAIWAN, R.O.C. 504 LL.F
CHARACTERIZATION OF PARTICLE CONTAMINATION SOURCE IN REACTIVE SPUTTER
TIN DEPOSITION PROCESS BY B. VOSS, J. SHEN AND D. JENDRESKY; SAMSUNG
SEMI; AUSTIN, TX. 507 LL.G FAILURE ANALYSIS FOR LOW YIELD CAUSED BY
CHARGING EFFECT BY CVD SYSTEM FOR IMD LAYER BY G.S. CHO. GO. PARK, Y.M.
KWON, K.H. SUH AND J. LEE; ANAM SEMI; KYUNGGI, KOREA. 510 LL.H THE
IMPACT OF A RF PLASMA PRIOR TO TI/TIN DEPOSITION ON THE FORMATION OF
VOLCANOES IN TUNGSTEN DUAL- DAMASCENE STRUCTURES FOR HIGH-DENSITY FLASH
MEMORY APPLICATIONS BY V. FORTIN, D. AVALOS, T. QURESHI, T.P. LEE, K.C.
WU, G. KOVALL, C. JANG, D. LUI AND C.H. CHEN; MOSEL VITELIC; SAN JOSE,
CA. 513 CMP - RELIABILITY ISSUES 11.1 CORRELATING POLISHING AND
ELECTRICAL PERFORMANCE OF 1ST STEP AND 2ND STEP COPPER CMP WITH
DEFECTIVITY AND THE IMPACT OF FILTRATION BY G. VASILOPOULOS, A.
ZAMARRO, Z. LIN; MYKROLIS; BEDFORD, MA; AND K. DEVRIENDT, M. MEURIS;
IMEC; LEUVEN, BELGIUM. 519 * POSTER PAPERS * 1 1.J NEXT GENERATION CU
CMP: FORMULATION AND EVALUATION OF AN AF CU CMP SYSTEM BY J. KELEHER,
X. SHI, S. KENNEY, M. JIANG, Y. LI; CLARKSON UNIV; POTSDAM, N.Y. 527 ILK
AN INVESTIGATION OF SURFACE OXIDE DAMAGE RESULTING FROM TUNGSTEN CMP
USING H 2 O 2 AS THE OXIDENT BY D.A. HANSEN, D. WATTS; EBARA TECH; SAN
JOSE, CA; AND G. MOLONEY; CYBEQ NANO TECH; SAN JOSE, CA. 532 11 .L TI
SIH CIDE RESIDUE CAUSED S14 256M DRAM BIT LINE SHORT THROUGH THE
WATERMARK FORMATION BY B.R. NI, C.S. HUANG, W.P. CHIU; PROMOS TECH;
TAIWAN, R.O.C. 535 CMP - CLEANING PR 1 I.M INVESTIGATING THE TWO PART
CLEANING PROCESS WITH SEMI-AQUEOUS FLUORIDE CHEMISTRIES BY R. SMALL, M.
CARTER, S. J. KIRK, M. CERNAT; EKC TECH; HAYWARD, CA. 541 (INVITED
PAPER) SESSION XO VLSI MULTILEVEL INTERCONNECTION CMP - INSTRUMENTATION
& HARDWARE * POSTER PAPERS * 12.A CHARACTERIZATION OF A SILICA BASED
STI CMP SLURRY IN A VACUUM-PRESSURE DISPENSE SLURRY DELIVERY SYSTEM AND
PUMP LOOP BY R.K. SINGH, E.C. KONG AND J.P. BARE; BOC EDWARDS; SANTA
CLARA, CA.; AND B. JOHL; RODEL; PHOENIX, AZ. 557 12.B EFFECT OF CMP
SLURRY FILTRATION ON WAFER DEFECTIVITY REDUCTION BY H. LINKOWICH;
FJLTERITE; TIMONIUM, MD. 560 12.C COPPER CMP PROCESS MONITORING USING
AN IN-LINE COMPACT METROLOGY SYSTEM BY D. LIKHACHEV, D. GAN, E. MAIKEN,
F. STANKE; SENSYS INSTRUMENTS; SANTA CLARA, CA; AND K.Y. RAMANUJAM, G.
LEE; LAM RESEARCH; FREMONT, CA. 563
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