2000 proceedings: May 21 - 24, 2000, LasVegas, Nevada, USA
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| Beschreibung: | XXXV, 1756 S. Ill., graph. Darst. |
| ISBN: | 0780359089 0780359097 |
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| adam_text | JUNE 27-29, 2000 VMIC CATALOG NO. 00 EVIIC - 200 SANTA CLARA MARRIOTT
HOTEL SANTA CLARA, CA 2000 INGS SEVENTEENTH INTERNATIONAL VLSI
MULTILEVEL INTERCONNECTION CONFERENCE (VMIC) A SPECIALTY CONFERENCE OF X
I- 1 ^ I ICROELECTRONICS NST1TDTE J^INTER- ONNECTION TOC LIBRARY OF
CONGRESS NO. 89-644090 SEVENTEENTH INTERNATIONAL VLSI MULTILEVEL
INTERCONNECTION CONFERENCE JUNE 27 -29, 2000 ADVANCE PROGRAM TUESDAY,
JUNE 27, 2000 OPENING SESSION * 9 A.M. WELCOMING REMARKS BY THE GENERAL
CHAIRMAN DR. THOMAS E. WADE UNIVERSITY OF SOUTH FLORIDA SESSION I *9:15
A.M. KEYNOTE ADDRI 300 MM/COPPER/LOW-K CONVERGENCE: TIMING, TRENDS &
ISSUES DR. ROBERT N. CASTELLANO PRESIDENT & CEO THE INFORMATION NETWORK
NEW TRIPOLI, PENNSYLVANIA JAPAN S INDUSTRIAL PROGRESS IN 300 MM
FABRICATION TECHNOLOGY DR. SHIGERU KOBAYASHI DEPUTY GENERAL MANAGER
SEMICONDUCTOR LEADING EDGE TECHNOLOGIES (SELETE) YOKOHAMA, JAPAN SESSION
H -10:30 A.M. -12:10 P.M. VLSI MULTILEVEL INTERCONNECTION CONDUCTOR
SYSTEMS - PARTI CHAIRMAN: DR. DONALD S. GARDNER INTEL CORP. SANTA CLARA,
CA. 2.A SEED LAYERS AND CU JET PLATING FOR INTERCONNECTS BELOW 0.10
MICRONS BY U. COHEN AND G. TZANAVARAS; JETS TECH; SANTA CLARA, CA 2.B
COMPARATIVE ANALYSIS AND STUDY OF IONIZED METAL PLASMA - CU (IMP-CU)
AND CHEMICAL VAPOR DEPOSITION - CU (CVD-CU) ON DIFFUSION BARRIER
PROPERTIES OF IMP * TAN ON SIO, BY K. LEE, L. CHAOYONG, B. NARAYANAN,
W. J. JIE, F. P. DOW; INST. OF MICROELECTRONICS; SINGAPORE; Y.K . LEE,
K. M. LATT, K.J. HYUNG; NANYANG TECH UNIV; SINGAPORE. 2.C
ELECTROCHEMICAL DEPOSITION OF COPPER ON CVD COPPER SUBSTRATES: EFFECT
ON THE SUBSTRATE BY I. IBANOV, Y.F. LEE, D. PAPAPANAYIOUTU, C.H. TING;
STEAG-CUTEK; SAN JOSE, CA. (INVITED PAPER) 21 27 31 2.D A NOVEL
ROOM-TEMPERATURE PLASMA-BASED COPPER ETCHING PROCESS FOR VLSI BY Y. KUO
AND S. LEE; TEXAS A & M UNIV; COLLEGE STATION, TX. 2.E RECENT PROGRESS
OF CU - LOW K INTERCONNECTS BY Y. HAYASHI; NEC CORP; TOKYO, JAPAN.
(INVITED PAPER) SESSION FFL -1:30 - 3:10 P.M. VLSI MULTILEVEL
INTERCONNECTION VMI NOVEL PROCI 39 45 62 CHAIRMAN: DR. ANDREW R.
NEUREUTHER UNIVERSITY OF CALIFORNIA BERKELEY, CA. 3.A A RADIO-FREQUENCY
QUASI-SOI POWER MOSFET USING CMP TECHNOLOGY BY S. MATSUMOTO, Y.
HIRAOKA, T. SAKAI, T. YACHI; NTT TELECOMM. LAB; KANAGAWA, JAPAN. 55
(INVITED PAPER) 3.B MULTIPLEXED LOCAL AREA NETWORK INTERCONNECT
TOPOLOGIES: DESIGN CONCEPTS FOR THE POST COPPER/LOW-K DECADE BY R.J.
GUTMANN, J.Q. LU; RENSSAELAER POLYTECH; TROY, NY (INVITED PAPER) 3.C
TECHNOLOGY AND DESIGN CHALLENGES FOR LOW POWER AND HIGH PERFORMANCE
MICROPROCESSORS BY V. K. DE AND S. BORKAR; INTEL CORP; HILLSBORO, OR.
70 (INVITED PAPER) 3.D INTERCONNECT PASSIVE COMPONENTS FOR MIXED
SIGNAL/RF APPLICATIONS BY A. KAR-ROY, P. N. SHERMAN, B. SHEN, S.
BHATTACHARYA AND P. KEMPF; CONEXANT SYS; NEWPORT BEACH, CA. (INVITED
PAPER) 3.E FACE TO FACE WAFER BONDING FOR 3D CHIP STACK FABRICATION TO
SHORTEN WIRE LENGTHS BY J.F. MCDONALD, R. KRAFT, J. LU, T.M. LU, A.
KUMAR, T. CALE, P. BELEMJIAN, O. ERGODAN AND Y.KWON; RENSSELAER
POLYTECH; TROY, NY; AND A. KALYEROS, J. CASTRACANE; STATE UNIV OF NEW
YORK; ALBANY, NY * POSTER PAPER* 3.F METAL-INSULATOR-METAL (MIM)
CAPACITORS USING TAJO, FOR RF-BICMOS TECHNOLOGY BY M. C. OLEWINE, G.J.
COLOVOS, H. SUN, J.F. DIGREGORIO, K.F. SAIZ AND R. DONDERO; PHILIPS
SEMI; ALBUQUERQUE, NM.; C. WIGGINS; TRKON TECH.; NEWPORT GWENT, U. K.
SESSION IV - 3:25 - 5:05 P.M. VLSI MULTILEVEL INTERCONNECTION
CMP-GENERAL & DIELECTRICS 80 99 CHAIRMAN: CHRIS SMITH APPLIED MATERIALS
SANTA CLARA, CA CHEMICAL MECHANICAL POLISHING 4.A MECHANICAL ASPECTS OF
CHEMICAL MECHANICAL POLISHING* BY D. A. DOMFELD; UNJV CALIFORNIA;
BERKELEY, CA. 105 (INVITED PAPER) 113 123 4.B A GENERALIZED MATERIAL
REMOVAL MODEL FOR THE CMP PROCESS BY G. FU AND A. CHANDRA ; IOWA STATE
UNIV; AMES, LA.; S. GUHA; SPEEDFAM-IPEC; CHANDLER, AZ. (INVITED PAPER)
4.C CHEMICAL-MECHANICAL POLISHING OF COPPER AND SILK IN MODEL ALUMINA
SLURRIES: EXPERIMENTAL AND MODELING RESULTS BY R.J. GUTMANN, C.L.
BORST, B. C. LEE, D.G. THAKURTA, D.J. DUQUETTE, AND W.N. GILL;
RENSSELAER POLYTECH; TROY, NY (INVITED PAPER) DIELECTRIC SYSTEMS 4.D
LOCAL DEPOSITION OF DIELECTRICS FOR THE DEEP SUB-MICRON RANGE BY H. D.
WANZENBOECK, S. HARASEK, H. LANGFISCHER, A. LUGSTEIN, E. BERTAGNOLLI, M.
GRITSCH, H. HUTTER, C. TOMASTIK, J. BRENNER AND H. STOERI; VIENNA UNIV
OF TECH; VIENNA, AUSTRIA. 137 4.E LOW-K POROUS SILICA FINNS DEPOSITED
BY PECVD USING POLYSILOXANE BY Y. SHIOYA, K. OHHIRA AND K. MAEDA; SPL;
TOKYO, JAPAN; AND H. DCAKURA, T. ISHIMARU AND S. OHGAWARA; CANON; TOKYO,
JAPAN --POSTER PAPER* 4.F CVD-BASED PREPARATION OF POROUS SILICA FILMS
BY Y. UCBIDA; TEKYO UNJV OF SCI & TECH; YAMANASHI, JAPAN; AND S.
SUGAHARA, M. MATSUMURA; TOKYO INST TECH; TOKYO, JAPAN. 153 4.G POST
ETCH STRIPPER DEVELOPMENT FOR HOSP LOW-K DIELECTRIC BY J. DUNNE, K.
NGUYEN, O. LEONTE,; HONEYWELL; SUNNYVALE, CA; AND D. PETERS, L. MOLNAR,
M. EGBE AND J. RIEKER; ASHLAND SPL CHEMICALS; EASTON, PA. 143 156
WEDNESDAY, JUNE 28, 2000 SESSION V - 8:00 - 9:40 A.M. VLSI MULTILEVEL
INTERCONNECTION C.M.P. CONDUCTORS CHAIRMAN: DR. KATHLEEN PERRY APPLIED
MATERIALS SANTA CLARA, CA 5.A A VIABLE 300 MM COPPER CMP PROCESS BY J.
MENDONCA , F. HAMPTON, D. KEENAN; MOTOROLA; AUSTIN, TX; AND A. ZUTSHI,
D. VIJAY, B. WITHERS, S. HUEY, R. BAJAJ, R. TOLLES, F. REDEKAR; APPLIED
MAT L; SANTA CLARA, CA. (INVITED PAPER) 161 5.B THE IMPROVEMENT ON DUAL
DAMASCENE TUNGSTEN PLANARIZATION VIA END-POINT SIGNAL TRIGGERED TWO-STEP
POLISHING BY S.Y. TAI, M.C. YANG, J.F. WANG AND C. YI; PROMOS TECH;
TAIWAN, R.O.C. 171 5.C UNLOCKING THE COPPER DAMASCENE PUZZLE BY R.
BAJAJ, F. REDEKER, K. WIJEKOON; APPLIED MAT L; SANTA CLARA, CA. 177 5.D
A NOVEL TUNGSTEN CMP PROCESS WITH SOFT PAD AND OPTICAL ENDPOINT SYSTEM
CONTROL BY A. SHIEH, Y. LIU, J. CHEN AND Y.L. HWANG; MACRONIX; TAIWAN,
R.O.C; AND J. CHANG, T. LIU AND P. TSAI; APPLIED MAT L; TAIWAN, - R.O.C.
183 5.E PROCESS METHODOLOGIES TO REDUCE REWORK AND PLUG CORING IN
SUB-QUARTER MICRON TUNGSTEN CHEMICAL MECHANICAL PLANARIZATION USING H 2
O 2 CONTAINING SLURRIES BY B. KASSAB, L. WITTERS, D. DORNISCH, L.
CAMILLETTI, D. TEETS, AND R. VISWANATHAN; CONEXANT SYS; NEWPORT BEACH,
CA. 189 * POSTER PAPERS * 5.F COPPER CMP AND EFFECT OF DUMMY
STRUCTURES BY J.T. PAN AND P. LI; APPLIED MAT L; SANTA CLARA, CA. 197
5.G FUNDAMENTALS OF CU CMP FOR DUAL DAMASCENE TECHNOLOGY BY Y. GOTKIS
AND R. KISTLER; LAM RES; FREMONT, CA. 20 5.H DETECTIVITY REDUCTION IN
COPPER CMP PROCESSES BY A. ZUTSHI, R. SURANA, J. TANG, G. LAM, C.
GARRETSON, R. BAJAJ AND F. REDEKAR; APPLIED MAT L; SANTA CLARA, CA. 203
5.1 DEVELOPMENT OF LOW COST AND HIGH THROUGHPUT W CMP PROCESS BY R.
LUM, S. MISHRA, L. WU, S. KUMARASWAMY, C. CHAN AND D. GROECHEL; APPLIED
MAT L; SANTA CLARA, CA. 206 SESSION VI - 9:55 A.M.-12:00 P.M. VLSI
MULTILEVEL INTERCONNECTION & MODELLING - PART I DR. VALERIY SUKHAREV LSI
LOGIC CORP. SANTA CLARA, CA 6. A PLASMA EQUIPMENT MODELING FOR PROCESS
DESIGN BY M. J. KUSHNER AND J. LU; UNIV OF ILLINOIS; URBANA, IL. 211
{INVITED PAPER) 6.B SIMULATION AND ANALYSIS OF PHYSICAL VAPOR
DEPOSITION OVER SUB-MICRON FEATURES BY D. G. CORONELL AND E.W. EGAN;
REACTION DESIGN; SAN DIEGO, CA. 217 (INVITED PAPER) 6.C SIMULATIONS OF
C 2 F S , Q E, /Q Q E, /CO AND F T IFL PLASMAS FOR OXIDE ETCH BY X.P.
XU AND P. SCHOENBORN; LSI LOGIC; SANTA CLARA, CA. 227 6.D INTEGRATED
MULTISCALE PROCESS SIMULATION FOR LPCVD BY T. CALE; RENSSELAER
POLYTECH; TROY, NY.; T.P. MERCHANT AND L.J. BORUCKI; MOTOROLA; MESA, AZ;
M.K. GOBBERT; UNIV. MARYLAND; BALTIMORE, MD; AND A.H. LABUN; COMPAQ;
SHREWSBURY, MA. 233 (INVITED PAPER) 6.E MODELING PLASMA TOOLS: REACTOR
AND FEATURE SCALES BY P. STOUT, V. KOLOBOV AND N. ZHOU; CFD RES;
HUNTSVILLE, AL; S. A. ALIBEIK, J.P. MCVITTIE AND K.C. SARASWAT; STANFORD
UNIV; STANFORD, CA. 243 6.F CHIP-SCALE SIMULATION OF PATTERN
PROCESSING: METHODS, MODELS, ACCURACY AND APPLICATIONS BY Y. GRANIK, O.
TOUBLAN, N. COBB, E. SAHOURIA, T. DONNELLY AND T. DO; MENTOR GRAPHICS;
SAN JOSE, CA. 249 CHAIRMAN: * POSTER PAPERS* 6.G ALL-OPTICAL METROLOGY
FOR RAPID CHARACTERIZATION OF COPPER DAMASCENE STRUCTURES BY M. BANET,
M. JOFFE, M. GOSTEIN, A. MAZNEV AND R. SACCO; PHILIPS ANALYTICAL;
NATICK, MA. 6.H FEATURE SUPERFILLING USING LEVELING AGENTS IN COPPER
PLATING BY S. SOUKANE AND T. S. CALE; RENSSELAER POLYTECH; TROY, NY.
SESSION VH - 1:00 - 3:00 P.M. VLSI MULTILEVEL INTERCONNECTION POSTER
PAPER / EXHIBITION DEDICATED VIEWING TIME SESSION VM - 3:00 - 5:00 P.M.
VLSI MULTILEVEL INTERCONNECTION RELIABILITY ISSUES CHAIRMAN: DR. LOREN
W. LINHOLM NAT L INST. OF STD. & TECH. (NIST) GAITHERSBURG, MD. 8.A
ELECTROMIGRATION FAILURE MECHANISMS IN DAMASCENE COPPER MULTILEVEL
INTERCONNECTS BY D. NGUYEN AND H. RATHORE; IBM; HOPEWELL JET.; NY. 8.B
THE INFLUENCE OF POST ETCH CLEANING ON THE STOP LAYER DAMAGE FOR DUAL
DAMASCENE ETCH BY B.R. YOUNG, Y.H. CHIU, M.H. HUANG, H.J. TAO, C.S.
TSAI AND M.S. LIANG; TSMC; TAIWAN, R.O.C. 8.C A CORRELATION OF PECVD
OXIDE FILM CHARGE TO TRANSISTOR LEAKAGE BY L. ZHANG, D. WEI, W.
CATABAY, Y. WANG, J. DONG, S. YOSHIKAWA Y.L. HO; LSI LOGIC; SANTA CLARA,
CA. (INVITED PAPER) 8.D EFFECT OF TI SALICIDE PROCESS WITH METAL
CONTAMINATION IN BF, IMPLANTATION FOR GATE OXIDES BY Y. SUEYOSHI, M.
KONDO, S. SAITO AND A. ISHIHAMA; SHARP; HIROSHIMA, JAPAN. 8.E
IMPROVEMENT IN GATE OXIDE DAMAGE USING LOW TEMPERATURE AR-PRECLEAN AND
TI DEPOSITION IN 0.18 MICRON METALLIZATION BY H. ABDUL-RIDHA, D. YOUNG,
W. MCAUTHUR, J. YOTA, J. WOOD, V. RAMANATHAN AND M. BRONGO; CONEXANT
SYS; NEWPORT BEACH, CA. 8.F LOW TEMPERATURE CVD TIN DEPOSITION COMBINED
WITH N 2 /HJ PLASMA TREATMENT TO PREVENT AL EXTRUSION BY Y.C. CHANG, B.
WANG, T. HSIEH AND M. LIN; UMC; TAIWAN, R.O.C. * POSTER PAPERS * 8.G
IMPACT OF DEGAS CONDITIONS ON VIA CHAIN RESISTANCE FOR INTEGRATED FSG
IMD/AL-CU METALLIZATION PROCESS BY J.N. TU AND C. T. HUANG; MACRONK;
TAIWAN, R.O.C. 8.H THE EFFECT OF TUNGSTEN SILIDDE DEPOSITION PRECURSOR
ON THIN FLOATING GATE OXIDE RELIABILITY AND EEPROM PROGRAMMING
EFFICIENCY BY K. CHERUKURI AND L. NGUYEN; ST MICRO; CARROLLTON, TX. 8.1
METAL DEFECTS LOCALIZATION WITH A NOVEL LARGE AREA TEST STRUCTURE BY
G. MAGRI AND B. ZANDERIGHI; ST MICRO; AGRATE BRIANZA, ITALY. 257 260 267
272 275 285 291 297 305 308 311 8.J ADHESION PROMOTION STUDY ON 0.13
MICRON SIO:C:H LOW-K/COPPER DAMASCENE PROCESS BY C.C. LIN, T.I. BAO,
S.M. JANG, C.H. YU AND M.S. LIANG; TSMC; TAIWAN, R.O.C. 314 8.K
ELIMINATION OF JUNCTION SPIKING PROBLEMS BY USING PRE- CLEAN ETCH AND
TWO STEP TIN DURING CONTACT BARRIER DEPOSITION PROCESS BY A. SIDHWA, C.
SPINNER, T. GANDY, S. GUISINGER; ST MICRO; PHOENIX, AZ. 317 8.L
INVESTIGATION OF ALUMINUM WHISKER GROWTH ON MULTILEVEL METALLIZATION
BY R.J. CHEIN, W.C. LIEN AND Y.Y. CHEN; MACRONK; TAIWAN, R.O.C. 3 20 8.M
THE IMPACT OF BELL-JAR AND QUARTZ PEDESTAL IN METAL DEPOSITION TOOLS
BY A. SIDHWA, X. BREUREC, C. SPINNER, T.CHHATPAR, S.ZHENG, K. DENNIS; ST
MICRO; PHOENIX. AZ. 323 8.N THE EFFECT OF METAL LAYER PHOTO REWORK TO
ETCH RESIDUE FORMATION AND SOLUTION BY Y.F. HUANG, A.J. CHIOU, N.T.
LIAN, S. S. HWU AND P. LIU; MACRONK; TAIWAN, R.O.C. 326 THURSDAY, JUNE
29, 2000 SESSION IX - 8:15 -10:00 A.M. VLSI MULTILEVEL INTERCONNECTION
CMP-DIELECTRICS/TEST & MODELING CHAIRMAN: DR. PETER BURKE RODEL INC.
NEWARK, DELAWARE CMP - DIELECTRICS 9.A PATTERN DENSITY EFFECTS OF FA
VS. SLURRY BY B. KOUTNY; CYPRESS SEMI; SAN JOSE, CA. 331 (INVITED
PAPER) * POSTER PAPERS * 9.B TRACE METAL REDUCTION IN POST OXIDE CMP
CLEANING BY USING DOUBLE-SIDED BRUSH SCRUBBING BY A. SHIEH, W.H. HUANG,
J. CHEN , Y.L. HWANG; MACRONK; TAIWAN, R.O.C. 341 9.C CHEMICAL
MECHANICAL PLANARIZATION OF ILD DEVICE WAFERS USING CERIA OXIDE SLURRY
BY H.A. HANSEN, G. MOLONEY AND A. REYES; CYBEQ NANO TECH; SAN JOSE, CA.
344 9.D THE OPTIMIZATION OF SINGLE STEP STI CMP BY S.Y. TING, K.J.
LIU, J. LIANG, C.C. JUAN AND T.J. YIN; WINBOND; TAIWAN, R.O.C. 347 9.E
A MATHEMATICAL SIMULATION MODEL TO PREDICT STT-CMP POLISH RATE FOR
VARIOUS NEW PRODUCTS BY C.F. LU, J.P. CHUANG, C.H. LO AND W.W. LEE;
TSMC; TAIWAN, R.O.C. 350 MODELLING. & SIMULATIONS - II 9.F 3D
MICROSTRUCTURAL SIMULATION OF THIN FILM DEPOSITION FOR VLSI
INTERCONNECTS BY T. SMY; CARLETON- UNIV.; ALBERTA, CANADA; S.K. DEW AND
MJ. BRETT; UNW. ALBERTA; EDMONTON, CANADA. 355 (INVITED PAPER) 7 9.G
APPLICATION OF MULTI-LAYER METAL PROCESS MODELS TO INTERCONNECT DESIGN
BY T. OHTA AND K. NISHI; SELETE; YOKOHAMA, JAPAN. 365 (INVITED PAPER)
9.H EFFECTS OF CROSSING UNDER-LAYER INTERCONNECT GEOMETRY ON THE SIGNAL
INTEGRITY OF UPPER-LAYER INTERCONNECTS BY J.K. WEE, K.W. KWAK, Y.J.
JEON, P.S. LEE, H.J. LEE, C.S. PARK, S.J. LN, S.B. YE, D.J. LEE, J.Y.
CHUNG; HYUNDAI; KYOUNGKI, KOREA 9.1 DEVELOPMENT OF A RANDOM-WALK
ALGORITHM FOR IC INTERCONNECT ANALYSIS: 2D TE BENCHMARKS, MATERIALLY
HETEROGENEOUS DOMAINS BY Y.L. LECOZ, K. CHATTERJEE AND R.B. IVERSON;
RENSSELAER POLYTECH; TROY, NY. 369 374 SESSION X -10:10 A.M. -12:00 P.M.
VLSI MULTILEVEL INTERCONNECTION DIELECTRICS & CONDUCTORS CHAIRMAN: DR.
WILLI VOLKSEN IBM ALMADEN RES. CTR. SAN JOSE, CA. 10A THERMAL STABILITY
STUDY OF HDP FSG FOR CU DUAL DAMASCENE APPLICATION BY P. Y. CHANG, P.R.
JENG AND M. LIOU; MACRONK; TAIWAN, R.O.C. 10B ELIMINATION OF PR POISON
BY SURFACE MODIFICATION ON LOW-K CVD MATERIALS BY S.M. JENG, L.J. LI,
B.R. YOUNG, S.M. JANG, C.H. YU AND M.S LIANG; TSMC; TAIWAN, R.O.C. IOC
OPTIMIZATION OF BAKING FOR FLARE ORGANIC LOW-K DIELECTRIC MATERIAL BY
Y. XU, S.Y.M. CHOOI, M.S. ZHOU AND S. GUPTA; CHARTER SEMI; SINGAPORE. *
POSTER PAPERS * 10D THERMAL STABILITY STUDY OF PEC VD CARBON-DOPED SIO 2
LOW DIELECTRIC CONSTANT THIN FILMS BY L.M. HAN, N. BALASUBRAMANIAN, S.
CHEN, X. BU, P.D. FOO AND J. XIE; INST OF MICRO; SINGAPORE 10E PROCESS
OPTIMIZATION AND FILM CHARACTERIZATION OF SI- RICH OXIDE DEPOSITED BY
PECVD BY S.L. WU AND P.R. JENG; MACRONK; TAIWAN, R.O.C. 10F THE
INFLUENCE OF INTER-METAL DIELECTRIC AND HDP PASSIVATION LAYER ON DEVICE
PERFORMANCE BY C.T. NI; D. YANG, E. SU AND K. TSAI; TASMC; TAIWAN,
R.O.C. 383 389 393 401 404 407 10G HYDROGEN CONCENTRATION ANALYSIS IN
SEQUENTIALLY DEPOSITED THIN FILMS AND APPLICATION OF SURFACE CHARGE
ANALYSIS TECHNIQUES FOR FAST AND NON-DESTRUCTIVE CHARACTERIZATION OF
PECVD SILICON NITRIDE BY C.Y. WANG, E.H. LIM, V.Y. VASSILIEV, J.L.
SUDIJONO, J.Z. ZHENG AND A. CUTHBERTSON; CHARTER SEMI; SINGAPORE. 411
10H A STUDY OF PMD FILMS BY USING SACVD AND APC VD IN ALSICU AND AICU
METALLIZATION PROCESS BY Y. Y. CHEN, W. C. LIEN.W.C. FU; MACRONK;
TAIWAN, R.O.C. 414 101 A NOVEL ADHESION MEASUREMENT OF LOW-K MATERIALS
FOR ULSI BY L.S. JUANG, W.W. LEE, C.I. CHANG AND C.H. HO; TSMC: TAIWAN,
R.O.C. 417 8 CONDUCTOR SYSTEMS - PART II 10J PLANARIZATION OF CU DURING
ELECTRODISSOLUTION BY Y. TIAN AND I.I. SUNI; CLARKSON UNIV; POTSDAM,
NY. 423 10K GAP FILLING CAPABILITY STUDY OF LTS/HOT AL PROCESS ON METAL
DAMASCEME BY H. CHEN, S.H. HUANG, S.K. HUANG, Y. T. HUANG AND E.
CHIANG; WINBOND; TAIWAN, R.O.C. 431 * POSTER PAPERS * 10L IMPROVEMENT
OF FIB-BASED TUNGSTEN METALLIZATION BY H. LANGFISCHER, E. BERTAGNOLLI,
A. LUGSTEIN, H.D. WANZENBOCK, H. HUTTER, M. GRITSCH AND C. TOMASTIK;
VIENNA UNIV; WIEN, AUSTRIA. 439 10M EVOLUTION OF ALUMINUM TARGET
ORIENTATION AND ITS INFLUENCE ON DEPOSITION FILM UNIFORMITY AT THE EARLY
LIFE SPUTTERING BY C.F. LO, A. SNOWMAN, R. MATHEW, P. GILMAN, D. DRAPER
AND C. FISHER; PRAXAIR-MRC; ORANGEBURG, NY. ION METAL ETCH WITH PR-FREE
PROCESS FOR 0.15 MICRON TECHNOLOGY BY Y.H. CHIU, M.H. HUANG, H.J. TAO
AND C.S. TSAI; TSMC; TAIWAN, R.O.C. 10O X-RAY DIFFRACTION STUDY OF
COBALT SILICIDE PHASES FORMED BY HOT SPUTTERING AND IN-SITU ANNEAL BY
D. SAIGAL, G. KOHARA, G. LAI AND P. WANG; APPLIED MAT L; SANTA CLARA,
CA. 448 10P MECHANISM OF ALUMINUM LIGHT SPOTS FORMATION BY Y.J. WU AND
M. LIN; UNITED MICRO CORP; TAIWAN, R.O.C. 451 2000 VMIC AWARDS LUNCHEON
THURSDAY, JUNE 29; 12:30 - 2:00 P.M. AWARDS LUNCHEON PRESENTATION
SUPER-COOLED UNITY-K DIELECTRIC SYSTEM FOR ULSI INTERCONNECTS DR.
THOMAS E. WADE PROFESSOR UNIVERSITY OF SOUTH FLORIDA OUTSTANDING
PAPER/POSTER PRESENTATIONS THE VMIC OUTSTANDING PAPER AWARD FOR 1999 IS
PRESENTED TO THE PAPER ENTITLED INTEGRATION OF HSQ IN A SUB-0.20
MICRON CMOS TECHNOLOGY WITH UNLANDED VIA ARCHITECTURE BY C. LAIR, G.
PARE, F. ANDRE, C. MADDALON, M. HAOND; ST MICRO; CROLLES, FRANCE; V.
DEJONGHE, S. LOUWERS; PHILIPS SEMI; AND R. PANTEL, G. AUVERT; CNET
TELECOM; MEYLAN, FRANCE. THE VMIC OUTSTANDING POSTER PAPER AWARD FOR
1999 IS PRESENTED TO THE POSTER PAPER ENTITLED TES T METHODS FOR
ASSESSING ADHESION OF INTEGRATED CIRCUIT THIN FILM DURING CMP BY S.
TOWLE AND M. MOINPOUR; INTEL CORP; SANTA CLARA, CA. 442 445 SESSION XI
- 2:00 - 4:30 P.M. VLSI MULTILEVEL INTERCONNECTION
BARRIER-CONTACT-ADHESION & CMP-CONSUMABLES CHAIRMAN: DR. ARJUN N. SAXENA
INT L SCIENCE CO. PALO ALTO, CA. BARRIER/CONTACT/ADHESION 11A BARRIER
LAYERS FOR CU INTERCONNECTION - BARRIER PROPERTIES AND CMP BY T. HARA;
HOSEI UNIV; TOKYO, JAPAN. 459 (INVITED PAPER) 1 IB VERY DEEP ML CONTACT
PROCESS INTEGRATION ON W BIT LINE DEPENDING ON THE DIFFERENT PREMETAL
CLEANING AND BARRIER METALS TI/TIN BY H. KWON, C.Y. KIM, J.S. KIM, J.H.
YUN, B.S. EUN, K.Y. KIM, B.W. YANG, Y.S. KIM AND H.L. PARK; HYUNDAI;
KYOUNGKI, KOREA. 469 11C LOW TEMPERATURE RTP MONITORING BY USING COBALT
SUICIDE CHARACTERISITICS BY T. TSENG, R. CHANG AND M. LIN; UNITED MICRO
CORP; TAIWAN, R.O.C. 475 11D ELECTRICAL CHARACTERISTICS FOR METAL
CONTACT IN ULSI INTERCONNECT APPLICATIONS BY D.W. KIM, K.W . KIM, J.S.
KIM, S.H. SOHN, S.T. HONG, W.S. WOO, C.Y. LEE, M. K. GONG, K.S. SON;
HYUNDAI; KYOUNGKI, KOREA 480 * POSTER PAPERS * HE SPUTTER DEPOSITION OF
TA/TAN, DIFFUSION BARRIERS FOR CU INTERCONNECTS BY H. ZHANG; TOSOH SMD;
GROVE CITY, OH. 487 11F IMPROVED TIN BASED DIFFUSION BARRIER USING
MULTI- LAYERED TI/TIN STRUCTURE BY W.F. WU, K. C. TSAI; NNDL; TAIWAN,
R.O.C; C.G. CHAO, Y.L. CHIN, B. S. CHIOU; CHIAO TUNG UNIV; TAIWAN,
R.O.C; C.F. HUANG, S.T. WU; TSING HUA UNIV; TAIWAN, R.O.C. 490 11G
SOLUTIONS OF INTEGRATION ISSUES FOR THROUGH-ARC VIA PROCESS USING MOCVD
TIN AS GLUE LAYER BY CR. LIN, J.J. HUANG, H.B. LU, C.K.L. WU; UNITED
MICRO CORP; TAIWAN, R.O.C. 493 11H THE EFFECT OF SB, SOAK FOR WC VD
PROCESS ON THE C VD TIN BARRIER FILM BY Y.K. KIM, J.W. HAN, S.C SHIM,
J.W. PARK, Y.S. JANG, S. Y. LEE AND K.H. SUH; ANAM SEMI; KYUNGGI, KOREA.
496 1II THE EFFECTS OF LINERS ON W CMP AND PLUG PERFORMANCE BY C.T.
NI, M. CHEN AND K. TSAI; TASMC; TAIWAN, R.O.C. 499 11J EFFECTS OF ARGON
PLASMA PREDEAN ON NON-SALIDDE SILICON CONTACT RESISTANCE FOR
NON-VOLATILE MEMORY BY C T. HUANG, C.Y. LEE, Y.L. HWANG; MACRONK;
TAIWAN, R.O.C. 503 CMP - CONSUMABLES 1 IK INVESTIGATIONS OF VARIABILITY
IN CMP SLURRY QUALITY AND ITS IMPACT ON PLANARIZATION PROCESS BY P.
HECKER, C. AUSTIN AND J. NORBERT; TEXAS INSTRUMENTS; DALLAS, TX; AND A.
MISRA AND B. SCHMIDT; AIR LIQUIDE; DALLAS, TX. 509 528 11L THE EFFECT
OF SLURRY VISCOSITY ON CMP BY B. MULLANY AND G. BYRNE; UNIV COLLEGE;
DUBLIN, IRELAND. 515 (INVITED PAPER) 11M A STUDY OF EFFECTS OF
POLISHING PARTIDE DISTRIBUTION ON SURFACE CHARACTERISTICS BY S.C. LIN
AND M.L. WU; TSING-HUA UNIV; TAIWAN, R.O.C. 522 UN RECENT ADVANCES IN
CMP SLURRY MANAGEMENT SYSTEMS BY J. BARE; BOC EDWARDS; HOCKESSIN, DE.
(INVITED PAPERS) * POSTER PAPERS * HO THICKNESS MEASUREMENTS ON
PATTERNED SITES FOR CMP BY D. SCHEINER, A. RAVID; NOVA MEASURING;
REHOVOTH, ISRAEL; AND N. BEN-MOSHE, E. BRANSKY; NOVA MEASURING; PHOENIX.
AZ. 539 IIP THE EFFECTS OF THE SLURRY TYPES ON STT POLISHING PROCESS
BY L. PENG, J.F. WANG AND C. YI; PROMOS TECH; TAIWAN, R.O.C. 11Q
BEHAVIOR OF CMP SLURRY PROPERTIES IN CONTINUOUS BLENDING AND
DISTRIBUTION SYSTEMS BY R.K. SINGH, B.R. ROBERTS; BOC EDWARDS; SANTA
CLARA, CA. 11R STI CMP DEFECT REDUCTION WITH SLURRY FILTRATION BY A.H.
LIU, R. SOUS, J. LI, P. PERSON, G. GRIFFITH, G. SPRAYBERRY, K. MURRAY,
J. GUZMAN AND N. WHITE; PHILIPS SEMI; ALBUQUERQUE, NM; AND G.
VASILOPOULOS, Z. LIN AND R. BLUM; MILLIPORE; BEDFORD, MA. 548 US CMP
WASTEWATER TREATMENT BY J.H. GOLDEN; MICRO- BAR; SUNNYVALE, CA. 551 542
545
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| title | 2000 proceedings May 21 - 24, 2000, LasVegas, Nevada, USA |
| title_auth | 2000 proceedings May 21 - 24, 2000, LasVegas, Nevada, USA |
| title_exact_search | 2000 proceedings May 21 - 24, 2000, LasVegas, Nevada, USA |
| title_full | 2000 proceedings May 21 - 24, 2000, LasVegas, Nevada, USA 50th Electronic Components & Technology Conference ; [IEEE] |
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| title_sub | May 21 - 24, 2000, LasVegas, Nevada, USA |
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