Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs: May 31 - June 2, 1994, Davos, Switzerland
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Konstanz
Hartung-Gorre
1994
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| Ausgabe: | 1. ed. |
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| Beschreibung: | XV, 436 S. Ill., graph. Darst. |
| ISBN: | 3891917848 0780314956 0780314948 |
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| 245 | 1 | 0 | |a Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs |b May 31 - June 2, 1994, Davos, Switzerland |c [IEEE]. Ed. by: Wolfgang Fichtner ... |
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| adam_text | PROCEEDINGS OF THE 6TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR
DEVICES & ICS 4- I5P5D94 MAY 31 - JUNE 2, 1994 DAVOS, SWITZERLAND EDITED
BY: WOLFGANG FICHTNER SWISS FEDERAL INSTITUTE OF TECHNOLOGY (ETH)
ZUERICH, SWITZERLAND ANDRE A. JAECKLIN ABB CORPORATE RESEARCH
BADEN-DAETTWIL, SWITZERLAND DOELF AEMMER SWISS FEDERAL INSTITUTE OF
TECHNOLOGY (ETH) ZUERICH, SWITZERLAND CO-SPONSORS: , SWISS FEDERAL
INSTITUTE OF TECHNOLOGY (ETH) ZUERICH, SWITZERLAND IEEE ELECTRON DEVICE
SOCIETY IEE JAPAN IEEE SWITZERLAND, ELECTRON DEVICE CHAPTER EUROPEAN
CONF. ON POWER ELECTRONICS (EPE), CHAPTER OF COMPONENTS AND DEVICES VII
TABLE OF CONTENTS TUESDAY, MAY 31, 1994 SESSION 1: THYRISTORS 1
CO-CHAIRMEN: J. BALIGA, NORTH CAROLINA STATE UNIVERSITY, RALEIGH, USA P.
PALMER, CAMBRIDGE UNIVERSITY, CAMBRIDGE, GB 1.1 NEXT GENERATION OF POWER
MODULES - AN EVOLUTIONARY CHANGE 3 FROM DISCRETE SEMICONDUCTOR TO
SYSTEM SEMICONDUCTOR T. YAMADA, G. MAJUMDAR, S, MORI, H. HAGINO, H.
KONDOH, MITSUBISHI ELECTRIC, FUKUOKA, JAPAN T. HIRAO, MITSUBISHI
ELECTRIC CORP., ITAMI, JAPAN (INVITE D PAPER) 1.2 COSMIC RADIATION AS A
CAUSE FOR POWER DEVICE FAILURE AND POSSIBLE 9 COUNTERMEASURES H.KABZA,
H.-J. SCHULZE, Y. GERSTENMAIER, F. PFIRSCH, K. PLATZOEDER, SIEMENS,
MUNICH, GERMANY P. VOSS, J. WILHELMI, W. SCHMID, EUPEC, MUNICH, GERMANY
1.3 4.5 KV MCT WITH BUFFER LAYER AND ANODE SHORT STRUCTURE 13 H.
DETTMER, W. FICHTNER, ETH, ZUERICH, F. BAUER, T. STOCKMEIER, ABB
SEMICONDUCTORS, LENZBURG, SWITZERLAND SESSION 2: IGBT 1 CO-CHAIMEN: D.
PAXMAN, PHILIPS, REDHILL, SURREY, GB Y. UCHIDA, FUJI ELECTRIC, TOKYO,
JAPAN 2.1 ADVANCED POWER MODULE USING GAAS SEMICONDUCTORS, METAL MATRIX
21 COMPOSITE PACKAGING MATERIAL, AND LOW INDUCTANCE DESIGN S. ANDERSON,
K. BERRINGER, G. ROMERO, MOTOROLA, PHOENIX, AI, USA 2.2 2.5KV 100 A
^I-STACK IGBT 25 Y. TAKAHASHI, T. KOGA, H. KIRIHATA, Y. SEKI, FUJI
ELECTRIC CORP. R&D, MATSUMOTO, JAPAN 2.3 A NEW IGBT WITH A MONOLITHIC
OVER-CURRENT PROTECTION CIRCUIT 31 Y. SEKI, Y. HARADA, N. IWAMURO, N.
KUMAGAI, FUJI ELECTRIC CORP. R&D, MATSUMOTO, JAPAN 2.4 A HIGH
PERFORMANCE INTELLIGENT IGBT WITH OVER CURRENT PROTECTION 37 Y. SHIMIZU,
Y. NAKANO, Y. KONO, N. SAKURAI. Y. SUGAWARA, S. OTAKA, HITACHI,
HITACHI-SHI, JAPAN SESSION 3: POSTER SESSION 1 CO-CHAIRMEN: P. HOWER,
UNITRODE INTEGRATED CIRCUITS, MERRIMACK, NH, USA H. OHASHI, TOSHIBA,
KAWASAKI, JAPAN IGBT 3.1 A STUDY ON THE IGBTS TURN-OFF FAILURE AND
INHOMOGENEOUS OPERATION 45 J. YAMASHITA, H. HARAGUCHI, H. HAGINO,
MITSUBISHI ELECTRIC, FUKUOKA-CITY, JAPAN 3.2 CRITICAL SWITCHING
CONDITION OF A NON-PUNCH-THROUGH IGBT INVESTIGATED BY 51 ELECTROTHERMAL
CIRCUIT SIMULATION P. TUERKES, W. KIFFE, R. KUHNERT, SIEMENS, MUNICH,
GERMANY 3.3 A REVERSE-CHANNEL, HIGH-VOLTAGE LATERAL IGBT 57 T, P. CHOW,
RENSSELAER POLYTECHNIC INSTITUTE, TROY, NY, USA D.N. PATTANAYAK, M.S.
ADLER, GENERAL ELECTRIC, SCHENECTADY, NY, USA B.J. BALIGA, NORTH
CAROLINA STATE UNIV., RALEIGH, NC, USA 3.4 THE FAST TURN OFF ADVANCED
IGBT, A NEW DEVICE CONCEPT 63 H.P. LEE, P.O. LAURITZEN, R.B. DARLING,
UNIV. WASHINGTON, SEATTLE, WA, USA M, WAKATABE, A. SUGAI, K. HORIGUCHI,
SHINDENGEN ELECTRIC, HANNA-CITY, SAITAMA, JAPAN 3.5 CELL OPTIMIZATION
FOR 500V, N-CHANNEL IGBTS 69 V. PARTHASARATHY, K.C. SO, Z. SHEN, T.P.
CHOW, RENSSELAER POLYTECHNIC INSTITUTE, TROY, NY, USA 3.6 COMPARATIVE
STUDY OF INTEGRATED CURRENT SENSORS IN N-CHANNEL IGBTS 75 Z. SHEN, K.C.
SO, T.P. CHOW, RENSSELAER POLYTECHNIC INSTITUTE, TROY, NY, USA 3.7
CURRENT SENSING IN IGBTS FOR SHORT-CIRCUIT PROTECTION 81 S.P. ROBB, A.A.
TAOMOTO, S. L. TU, MOTOROLA, PHOENIX, AI, USA 3.8 COMPARATIVE
INVESTIGATION ON POWER LOSSES IN SOFT-SWITCHING INSULATED 87 GATE
DEVICES A. CONSOLI, C. LICITRA, S. MUSUMECI, A. TESTA, UNIV. CATANIA F.
FRISINA, R. LETOR, SGS-THOMSON, CATANIA, ITALY 3.9 INTELLIGENT POWER
MODULES FOR DRIVING SYSTEMS 93 K. REINMUTH, H. STUT, L. LORENZ, SIEMENS,
MUNICH, S. KONRAD, TECH. UNIV. ILMENAU, ILMENAU, GERMANY 3.10 TURN-OFF
ANALYSIS OF THE IGBT USED IN ZCS MODE 99 S. LEFEBVRE, F. FOREST, LESIR,
CACHAN, FRANCE F. CALMON, J.P. CHANTE, CEGELY-ECPA, VILLEURBANNE, FRANCE
3.11 COMPUTER SIMULATION AND DESIGN OPTIMIZATION OF IGBT S IN
SOFT-SWITCHING 105 CONVERTERS I. WIDJAJA, A. KURNIA, D. DIVAN, K.
SHENAI, UNIV. WISCONSIN, MADISON, WI, USA SOI 3.12 COMPACT VERY HIGH
VOLTAGE CMOS COMPATIBLE BIPOLAR SILICON-ON- 113 INSULATOR TRANSISTOR A.
LITWIN, T. ARNBORG, ERICSSON COMPONENTS, KISTA-STOCKHOLM, SWEDEN 3.13
FORWARD BLOCKING CHARACTERISTICS OF SOI POWER DEVICES AT HIGH 117
TEMPERATURES R, CONSTAPEL, J. KOREC, DAIMLER-BENZ, FRANKFURT, GERMANY
3.14 THERMAL BEHAVIOUR OF LATERAL POWER DEVICES ON SOI SUBSTRATES 123 H.
NEUBRAND, R. CONSTAPEL, M. FUELLMANN, DAIMLER-BENZ, FRANKFURT, GERMANY R.
BOOT, A. BOOSE, UNIV. BREMEN, BREMEN, GERMANY FET 3.15 A COMPARISON OF
HIGH FREQUENCY CELL DESIGNS FOR HIGH VOLTAGE DMOSFETS 131 N. THAPAR,
B.J. BALIGA, NORTH CAROLINA STATE UNIV., RALEIGH, NC, USA 3.16 MODELLING
OF LDMOS AND LIGBT STRUCTURES AT HIGH TEMPERATURES 137 B. FATEMIZADEH,
D. SILBER, UNIV. BREMEN, BREMEN, GERMANY M. FUELLMANN, J. SERAFIN,
DAIMLER-BENZ, FRANKFURT, GERMANY 3.17 THE INFLUENCE OF THE N+ SOURCE
REGION ON PARASITIC PNP CONDUCTION IN 143 INTEGRATED N-CHANNEL DMOS R.K.
WILLIAMS, M.S. SHEKAR, SILICONIX, SANTA CLARA, CA, USA 3.18 NOVEL
ULTRALOW RON MBE GAAS MESFETS FOR HIGH-FREQUENCY HIGH- 149 TEMPERATURE
SWITCHED-MODE POWER CONVERTER APPLICATIONS K. SHENAI, D. HODGE, UNIV.
WISCONSIN, MADISON, WI, USA M.D. FEUER, J. CUNNINGHAM, AT&T BELL
LABORATORIES, HOLMDEL, NJ, USA 3.19 IMPROVEMENT OF BREAKDOWN VOLTAGE OF
GAAS-FETS USING LOW- 155 TEMPERATURE-GROWN GAAS INSULATOR H. THOMAS,
J.K. LUO, D.V. MORGAN, D, WESTWOOD, UNIV. WALES, CARDIFF, UK, K. LIPKA,
E, SPLINGART, E. KOHN, UNIV. ULM, ULM, GERMANY WEDNESDAY, JUNE 1, 1994
SESSION 4: IGBT 2 CO-CHAIRMEN: M. OKAMURA, HITACHI LTD., HITOCHI-SHI,
JAPAN R. SITTIG, UNIV. BRAUNSCHWEIG, BRAUNSCHWEIG, GERMANY 4.1 ULTIMATE
LIMITS OF AN IGBT (MCT) FOR HIGH VOLTAGE APPLICATIONS IN 163 CONJUNCTION
WITH A DIODE A. PORST, SIEMENS AG, MUNICH, GERMANY (INVITED PAPER) 4.2 A
LOW LOSS/HIGHLY RUGGED IGBT-GENERATION - BASED ON A SEIF ALIGNED 171
PROCESS WITH DOUBLE IMPLANTED N/N+-EMITTER T. LASKA, A. PORST, H.
BRUNNER, W. KIFFE, SIEMENS AG, MUNICH, GERMANY 4.3 A NEW IGBT STRUCTURE
WITH A WIDER SAFE OPERATING AREA (SOA) 177 N. THAPAR, B.J. BALIGA, NORTH
CAROLINA STATE UNIV.,RALEIGH, NC, USA AA HIGH VOLTAGE TRENCH DRAIN
LDMOS-FET USING SOI WAFER 183 Y. BABA, S. YANAGIYA, Y. KOSHINO, Y. UDO,
TOSHIBA, KAWASAKI, JAPAN SESSION 5: THYRISTORS 2 CO-CHAIRMEN: T.
SHIBATA, TOHOKU UNIVERSITY, SENDAI, JAPAN P. SPIRITO, UNIVERSITY OF
NAPLES, NAPLES, ITALY 5.1 TRENCH GATE EMITTER SWITCHED THYRISTORS 189
M.S. SHEKAR, SILICONIX, SANTA CLARA, CA, USA, J. KOREC, DAIMLER-BENZ,
FRANKFURT, GERMANY, B.J. BALIGA, NORTH CAROLINA STATE UNIV., RALEIGH,
NC, USA 5.2 COMPARISON OF RBSOA OF ESTS WITH IBGTS AND MCTS 195 N.
IWAMURO, B.J. BALIGA, R. KURLAGUNDA, G. MANN, A.W. KELLEY, NORTH
CAROLINA STATE UNIV., RALEIGH, NC, USA 5.3 ON THE SUITABILITY OF BIMOS
HIGH POWER DEVICES IN INTELLIGENT, SNUBBERLESS 201 POWER CONDITIONING
CIRCUITS F. BAUER, T. STOCKMEIER, ABB SEMICONDUCTORS, LENZBURG,
SWITZERLAND H. DETTMER, H, LENDENMANN, W. FICHTNER, ETH, ZUERICH,
SWITZERLAND 5.4 TURN-OFF FAILURE MECHANISMS IN LARGE (2.2KV, 20A) MCT
DEVICES 207 H. LENDENMANN, W. FICHTNER, ETH, ZUERICH, SWITZERLAND 5.5
IMPROVING THE GATE OXIDE INTEGRITY OF VERY HIGH VOLTAGE MCT AND IGBT 213
DEVICES BY EXTERNA! GETTERING OF METAL IMPURITIES E. HERR, H. BALTES,
ETH, ZUERICH, SWITZERLAND U. THIEMANN, T. STOCKMEIER, ABB SEMICONDUCTORS,
LENZBURG, SWITZERLAND SESSION 6: POSTER SESSION 2 CO-CHAIRMEN: L.
LORENZ, SIEMENS AG, MUNICH, GERMONY M. A. SHIBIB, AT&T BELL LABS,
READING, PA, USA BIPOLAR POWER DEVICES 6.1 ANALYSIS OF GTO FAILURE MODE
DURING DC VOLTAGE BLOCKING 221 H. MATSUDA, T. FUJIWARA, M. HIYOSHI, K.
NISHITANI, A. KUWAKO, T. IKEHARA, TOSHIBA, KAWASAKI, JAPAN 6.2 TURING S
INSTABILITY AS A FAILURE MECHANISM OF GTO 227 A. V. GORBATYUK, P. B.
RODIN, A.P. LOFFE INSTITUTE, ST. PETERSBURG, RUSSIA 6.3 GATE TURN-OFF
THYRISTOR ON THE BASE OF THE SDB-TECHNIQUE 233 I.V. GREKHOV, L.S.
KOSTINA, E.L. BELAKOVA, I.A. ROLNIK, A.P. LOFFE INSTITUTE, ST.
PETERSBURG, RUSSIA 6.4 MODELING AND CHARACTERIZING POWER SEMICONDUCTORS
AT LOW TEMPERATURES 237 T, VOGLER, A. SCHLOEGL, D. SCHROEDER, TU MUNICH,
MUNICH, GERMANY 6.5 CRYOGENIC OPERATION OF POWER BIPOLAR TRANSISTORS 243
R. SINGH, B.J. BALIGA, NORTH CAROLINA STATE UNIVERSITY, RAIEIGH, NC, USA
6.6 KIRK EFFECT LIMITATIONS IN HIGH VOLTAGE IC S 249 A.W. LUDIKHUIZE,
PHILIPS, EINDHOVEN, NETHERLANDS 6.7 SILICON CARBIDE P-N STRUCTURES AS
POWER RECTIFIERS 253 V.F. CHELNOKOV, A. STREL CHUCK, P. A. IVANOV, A.F.
LOFFE INSTITUTE, ST. PETERSBURG, RUSSIA G. LENTZ, C. PARNIERE, MERLIN
GERIN, GRENOBLE, FRANCE TECHNOLOGY 6.8 REDUCTION OF THERMOMECHANICAL
STRESS BY APPLYING A LOW TEMPERATURE 259 JOINING TECHNIQUE S. KLAKA, R.
SITTIG, TU BRAUNSCHWEIG, BRAUNSCHWEIG, GERMANY 6.9 ACCURATE SIMULATION
OF COMBINED ELECTRON AND LON-LRRADIATED SILICON 265 DEVICES FOR LOCAL
LIFETIME TAILORING J. VOBECKY, P. HAZDRA J. VOVES, F. SPURNY, CZECH
TECH. UNIV. PRAGUE, PRAGUE, CZECH REPUBLIC J. HOMOLA CKD SEMICOND.,
PRAGUE, CZECH REPUBLIC 6.10 A STUDY ON THE VARIATION OF CARRIER LIFETIME
WITH TEMPERATURE IN BIPOLAR 271 SILICON DEVICES AND ITS INFLUENCE ON
DEVICE OPERATION Y.C. GERSTENMAIER, SIEMENS AG, MUNICH, GERMANY 6.11
EXPERIMENTAL VALIDATION OF ELECTROTHERMAL SIMULATION USING SETIPIC FOR
275 ANALOGUE INTEGRATED CIRCUITS J, ECRABEY, L. HEBRARD, CH.
KLINGELHOFER, F. GAFFIOT, G. JACQUEMOD, J. BERGER-TOUSSAN, M. LE HELLEY,
ECOLE CENTRALE DE LYON, ECULLY, FRANCE 6.12 EXPERIMENTALLY VERIFIED,
TEMPERATURE DEPENDENT PHYSICAL MODELS/ 281 PARAMETERS FOR POWER DEVICE
SIMULATION M. ISBERG, FALUL-BORLAENGE UNIVERSITY COLLEGE, FALUN, SWEDEN
P. JONSSON, F. MASSZI, H. BLEICHNER, M. ROSLING, INSTITUTE OF
TECHNOLOGY, UPPSALA UNIVERSITY, UPPSALA, SWEDEN F. VOJDANI, LAKE MAELAR
VALLEY UNIVERSITY COLLEGE, VAESTERAS, SWEDEN E. NORDLANDER,
GAEVLE-SANDVIKEN UNIVERSITY COLLEGE, SANDVIKEN, SWEDEN 6.13 BIPOLAR POWER
DEVICE PERFORMANCE: DEPENDENCE ON MATERIALS, LIFETIME 287 AND DEVICE
RATINGS A. BHALLA, T.P. CHOW, RENSSELAER POLYTECHNIC INSTITUTE, TROY,
NY, USA 6.14 INFLUENCE OF THE MECHANICAL CONDITIONS ON THE ELECTRICAL
AND STRUCTURAL 293 PROPERTIES OF THE INTERFACE BETWEEN DIRECTLY BONDED
SILICON WAFERS A. LAPORTE, G. SARRABAYROUSE, LAAS-CNRS, TOULOUSE, FRANCE
A. LAPORTE, L. LESCOUZERES, A. PEYRE LAVIGNE, MOTOROLA SEMICONDUCTORS
SA, TOULOUSE, FRANCE M. BENAMARA, A. ROCHER, A. CLAVERIE,
CEMES/LOE-CNRS, TOULOUSE, FRANCE 6.15 A NOVEL HIGH VOLTAGE BIPOLAR
TECHNOLOGY FEATURING TRENCH-ISOLATED BASE 297 H.S. KIM, J,H. JIN, CK.
JEOUN, Y.C. CHOL B.J. KWON, S.K. LIM, K.H. CHOL SAMSUNG ELECTRONICS,
BUCHUN, KOREA MOS-GATED THYRISTORS 6.16 TWO-DIMENSIONAL DOPANT PROFILE
CHARACTERIZATION FOR MCT AND IGBT 305 STRUCTURES G. DALIMANN, H, SYHRE,
INSTITUT FRESENIUS, DRESDEN, GERMANY T. FEUDEL, H. LENDENMANN, W.
FICHTNER, ETH, ZUERICH, SWITZERLAND 6.17 THE INVERSION LAYER EMITTER
THYRISTOR - A NOVEL POWER DEVICE CONCEPT 309 F, UDREA G. AMARATUNGA
CAMBRIDGE UNIVERSIFY, CAMBRIDGE, GB 6.18 A COMPARATIVE STUDY OF PHYSICAI
AND SUBCIRCUIT MODELS FOR MOS-GATED 315 POWER DEVICES M. ANDERSSON, M.
GROENLUND, P. KUIVALAINEN, H. POHJONEN, FINLAND ELECTRONICS, ESPOO,
FINLAND PIC 6.19 DESIGN OF CURRENT LIMITER FOR A SMART POWER IC 323 G.
CALI , G. PALMISANO, G. PALUMBO, UNIVERSITA DI CATANIA, CATANIA, ITAIY
N. AIELLO, ST-MICROELECTRONICS, CATANIA, ITAIY 6.20 HIGH VOLTAGE
AUTOMOTIVE INTERFACE DESIGN, IN A VLSI COMPATIBLE 329 BICMOS TECHNOLOGY
M. CORSI, F. FATTORI, TEXAS INSTRUMENTS, DALLAS, TEXAS, USA SESSION 6A:
LATE NEWS PAPERS CO-CHAIRMEN: L. LORENZ, SIEMENS AG, MUNICH, GERMANY M.
A. SHIBIB, AT&T BELL LABS, READING, PA, USA 6.21 AN ALGAAS/GAAS HETERO
SOURCE BIPOLAR MODE STATIC INDUCTION 337 TRANSISTOR (HBSIT) WITH LOW
FORWARD VOLTAGE DROP AND HIGH CURRENT GAIN K. NONAKA, Y. ISHIKAWA, S.
YOKOYAMA, M. ABE, T. KAMIYAMA, HONDA R&D, SAITAMA, JAPAN 6.22 COSMIC RAY
INDUCED BREAKDOWN IN HIGH VOLTAGE SEMICONDUCTOR DEVICES 339 MICROSCOPIC
MODEL AND PHENOMENOLOGICAL LIFETIME PREDICTION H.R. ZELLER, ABB
SEMICONDUCTORS, LENZBURG, SWITZERLAND THURSDAY, JUNE 2, 1994 SESSION 7:
MOSFET 1 CO-CHAIRMEN: A. NAKAGAWA, TOSHIBA, KAWASAKI, JAPAN R. WILLIAMS,
SIIICONIX, SANTA CLARA, CA, USA 7.1 RECENT ADVANCES IN POWER INTEGRATED
CIRCUITS WITH HIGH LEVEL INTEGRATION 343 S. P. ROBB, J. L. SUTOR,
MOTOROLA, PHOENIX, AI, USA (INVITED PAPER) 7.2 HIGH-PERFORMANCE LATERAL
DMOSFET WITH OXIDE SIDEWALL-SPACERS 349 N. FUJISHIMA, A. KITAMURA, Y.
NAGAYASU, FUJI ELECTRIC CORPORATE R&D, MATSUMOTO CITY, JAPAN 7.3
SUBMICRON BICMOS COMPATIBLE HIGH VOLTAGE MOS TRANSISTORS 355 Y. Q.LI,
C.A.T. SALAMA, UNIV. OF TORONTO, TORONTO, CANADA M. SEUFERT, M. KING,
NORTHERN TELECOM LTD., NEPEAN, CANADA 7.4 HIGH TEMPERATURE PERFORMANCE
OF DIELECTRICALLY ISOLATED LDMOSFET: 359 CHARACTERIZATION, SIMULATION
AND ANALYSIS R. SUNKAVALLI, B.J. BALIGA, Y.S. HUANG, NORTH CAROLINA
STATE UNIVERSITY, RALEIGH, NC, USA 7.5 A 70-V, 90-MQTTIM 2 , HIGH-SPEED
DOUBLE-LAYER GATE UMOSFET REALIZED 365 BY SELECTIVE CVD TUNGSTEN S.
MATSUMOTO, NTT, MUSASHINO-SHI, TOKYO, JAPAN H. YOSHINO, H. ISHI, T.
OHNO, NTT, ATSUGI-SHI, KANAGAWA, JAPAN SESSION 8: POWER IC CO-CHAIRMEN:
C. CONTIERO, SGS-THOMSON, CORNAREDO/MILAN, ITALY Y. SUGAWARA, HITACHI
LTD., HITACHI-SHI, JAPAN 8.1 A NEW EDGE STRUCTURE FOR 2 KVOLT POWER IC
OPERATION 373 R. ZAMBRANO, G. CACCIOLA, S. LEONARDI, SGS-THOMSON
MICROELECTRONICS, CATANIA, ITALY 8.2 A 500V 1A 1 -CHIP INVERTER IC WITH
NEW ELECTRIC FIELD REDUCTION STRUCTURE 379 K. ENDO, Y. BABA, Y. UDO, M,
YASUI, Y. SANO, TOSHIBA CORP., KAWASAKI, JAPAN 8.3 A SINGLE-CHIP
PRE-REGULATOR CIRCUIT USING LIGBT AND CURRENT MODE SENSING 385 S. L.
WONG, N, MAJID, PHILIPS, BRIARCLIFF MANOR, NY, USA XV 8.4 A FULLY
INTEGRATED HDD POWER IC WITH NOVEL HEAD RETRACT FEATURE 391 R.K.
WILLIAMS, A. CHANG, B. CONCKLIN, G. PHAM, SILICONIX, SANTA CLARA, CA,
USA SESSION 9: IGBT 3 CO-CHAIRMEN: G. CHARITAT, LAAS, TOULOUSE, FRANCE
T.P. CHOW, RENSSELAER POLYTECHNIC INSTITUTE, TROY, NY, USA 9.1 THIN SOI
IGBT LEAKAGE CURRENT AND A NEW DEVICE STRUCTURE FOR HIGH 399 TEMPERATURE
OPERATION T. MATSUDAI, Y. YAMAGUCHI, N. YASUHARA, A. NAKAGAWA, H.
MOCHIZUKI, TOSHIBA CORP., KAWASAKI, JAPAN 9.2 A TRENCH-GATE LIGBT
STRUCTURE AND TWO LMCT STRUCTURES IN SOI SUBSTRATES 405 D.R. DISNEY,
DELCO ELECTRONICS CORP., KOKOMO, IN, USA H.B. PEIN, PHILIPS, BRIARCLIFF,
NY, USA J.D. PLUMMER, STANFORD UNIVERSITY, STANFORD, CA, USA 9.3 600V
TRENCH IGBT IN COMPARISON WITH PLANAR IGBT - AN EVALUATION OF THE 411
LIMIT OF IBGT PERFORMANCE M. HARADA, T. MINATO, I. TAKATA, MITSUBISHI
ELECTRIC, ITAMI CITY, JAPAN H. TAKAHASHI, K. INOUE, MITSUBISHI ELECTRIC,
FUKUOKA, JAPAN H. NISHIHARA, MITSUBISHI ELECTRIC, KITA-ITAMI CITY, JAPAN
SESSION 10: HF DEVICES CO-CHAIRMEN: H. IWAMOTO, POWEREX/MITSUBISHI,
YOUNGWOOD USA/ JAPAN D. SIGURD, IND. MICROELECTRONICS CENTER, KISTA,
SWEDEN 10.1 A 150V, 320MHZ, LOW NOISE SELF-ALIGNED DOUBLE DIFFUSED
LATERAL (SADDL) 419 PNP TRANSISTOR Y. SUGAWARA, M. INABA, H. ARAKAWA,
HITACHI, HITACHI-SHI, JAPAN 10.2 A 1.5GHZ, 35-W SI-MOSFET WITH AN
INTERNAL MATCHING CIRCUIT 425 E. YANOKURA, T. SEKI, I. TAKEI, Y.
MARUYAMA, Y. FUJITA, HITACHI, TAKASAKI, GUNMA, JAPAN M. KATSUEDA, I.
YOSHIDA, M. OHNISHI, K. SEKINE, HITACHI, TOKYO, JAPAN AUTHOR S INDEX 431
436
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| any_adam_object | 1 |
| author2 | Fichtner, Wolfgang |
| author2_role | edt |
| author2_variant | w f wf |
| author_corporate | ISPSD Davos |
| author_corporate_role | aut |
| author_facet | Fichtner, Wolfgang ISPSD Davos |
| author_sort | ISPSD Davos |
| building | Verbundindex |
| bvnumber | BV024399708 |
| ctrlnum | (OCoLC)916453020 (DE-599)BVBBV024399708 |
| edition | 1. ed. |
| format | Conference Proceeding Book |
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| id | DE-604.BV024399708 |
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| indexdate | 2024-07-09T21:58:49Z |
| institution | BVB |
| institution_GND | (DE-588)2136294-4 (DE-588)1692-5 |
| isbn | 3891917848 0780314956 0780314948 |
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| oclc_num | 916453020 |
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| owner | DE-83 |
| owner_facet | DE-83 |
| physical | XV, 436 S. Ill., graph. Darst. |
| publishDate | 1994 |
| publishDateSearch | 1994 |
| publishDateSort | 1994 |
| publisher | Hartung-Gorre |
| record_format | marc |
| spelling | ISPSD 6 1994 Davos Verfasser (DE-588)2136294-4 aut Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland [IEEE]. Ed. by: Wolfgang Fichtner ... 1. ed. Konstanz Hartung-Gorre 1994 XV, 436 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift gnd-content Fichtner, Wolfgang edt Institute of Electrical and Electronics Engineers Sonstige (DE-588)1692-5 oth GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018378472&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland |
| subject_GND | (DE-588)1071861417 |
| title | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland |
| title_auth | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland |
| title_exact_search | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland |
| title_full | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland [IEEE]. Ed. by: Wolfgang Fichtner ... |
| title_fullStr | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland [IEEE]. Ed. by: Wolfgang Fichtner ... |
| title_full_unstemmed | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs May 31 - June 2, 1994, Davos, Switzerland [IEEE]. Ed. by: Wolfgang Fichtner ... |
| title_short | Proceedings of the 6th International Symposium on Power Semiconductor Devices & ICs |
| title_sort | proceedings of the 6th international symposium on power semiconductor devices ics may 31 june 2 1994 davos switzerland |
| title_sub | May 31 - June 2, 1994, Davos, Switzerland |
| topic_facet | Konferenzschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018378472&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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