Proceedings of the IEEE 1994 Custom Integrated Circuits Conference: San Diego, California, May 1 - 4, 1994
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1994
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| ISBN: | 0780318870 0780318862 |
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| adam_text | Proceedings of the
IEEE 1994
CUSTOM INTEGRATED CIRCUITS
CONFERENCE
,----------------------
Technische Hochschule Darmstadt
FACHBEREICH INFORMATIK
BIBLIOTHEK
tnventar-Nr :
Sachgebiete:
Standort: j
Town amp; Country Hotel
San Diego, California
May 1 -4, 1994
Fachbereipjhs^bhotJ^ek Informatik
59516310
The CCIC ’94 is sponsored by the IEEE Electron Devices Society with cooperation from the IEEE Solid State
Circuits Council Its goal is to provide a forum for manufacturers, circuit designers, CAD developers, and
users of ASICs to present and discuss exciting new developments, future trends, and innovative ideas
CONTENTS
SESSION 1 - PRESIDIO ROOM
Monday Morning
8:00 WELCOME/OPENING REMARKS
Lauren Christopher, General Chairman
Resve Saleh, Conference Chairman
8:10 CICC ’94 - TECHNICAL PROGRAM
Allen Barlow, Technical Program Committee Chairman
8:20 KEYNOTE ADDRESS
Digital Wireless: Computer and Communication
Symbiosis or Culture Clash?
Dr Andrew J Viterbi, Vice-Chairman and Chief Technical
Officer, QUALCOMM Incorporated
SESSION 3 - FRIARS/PADRE/SIERRA ROOMS
Monday Morning
9:30 TOPICS IN SIMULATION AND MODELING
Chair: K Mayaram Co-Chair: Dilee p Divekar
3 1 25
9:35 Accurate Fourier Analysis for Circuit Simulators
K Kundert, Cadence Design Systems, San Jose, CA
3 2 29
10:00 Simulation of Return Ratio in Fully Differential
Feedback Circuits
P Hurst and S Lewis, University of California, Davis, CA
SESSION 2 - PRESIDIO ROOM
Monday Morning
9:30 LOW POWER CUSTOM TECHNOLOGIES
Chair: Jenny Ford Co-Chair: Michiel Beunder
2 1 3
9:35 INVITED
CMOS Technology for Low Voltage/Low Power
Applications
B Davari, R Dennard and G Shahidi, IBM,
Yorktown Heights, NY
2 2 11
10:25 High Performance 3 3 and 5 Volt 0 5-^m CMOS
Technologies for ASICs
I Kizilyalli M Thoma, S Lytle E Martin S
Vitkavage, R Singh, P Bechtold, J Kearney, M
Rambaud, A Oates, V Ryan, P Layman, M
Twiford, and W Cochran, AT amp;T Bell Laboratories,
Allentown, PA
2 3 15
10:50 BEST2 • A High Performance Super Self-Aligned 3V/5V
BiCMOS Technology With Extremely Low Parasitics
for Low-Power Mixed-Signal Applications
J Sung, T Chiu, K Lau, T Liu, V Archer, B
Razavi, R Swartz, AT amp;T Bell Laboratories,
Holmdel, NJ, F Erceg, J Glick, G Hower, S
Krafty, A LaDuca, M Ling K Moerschel W
Possanza, M Prozonic and T Long AT amp;T
Microelectronics, Allentown, PA
2 4 19
11:15 Trends in Devices for Low Power
R Reuss, S Mastroianni* B Ooms**, B-Y Hwang#, and
S-W Sun##, Motorola, Inc , Northbrook, IL, ‘Core
Technologies, Tempe, AZ, “Phoenix Corporate Res Lab ,
Tempe, AZ, #Advanced Custom Technologies, Mesa, AZ,
##Advanced Products Research, Austin, TX
3 3 33
10:25 A Quick Way to Find the Optimized Performance of a
Power Constrained Logic Circuit
K Lowe and P Gulak, University of Toronto, Toronto,
Ontario, Canada
3 4 37
10:50 Device-Level Analysis of a BIPMOS Pull-Down Device
Structure for Low-Voltage Dynamic BiCMOS VLSI
J Kuo, K Su, J Lou, S Ma, S Chen and C Chiang,
National Taiwan University, Taiwan, Republic of China
3 5 41
11:15 A New Deep Submicron Compact Physical Model for
Analog Circuits
D Cho and S Kang, University of Illinois, Urbana, IL
SESSION 4 - GOLDEN WEST ROOM
Monday Morning
9:30 SIGNAL PROCESSING FOR COMMUNICATIONS
ChainNicholas van Bavel Co-Chair: Jerry Molnar
4 1 47
9:35 A Channel Demodulator 1C for Digital Audio
Broadcasting
A Delaruelle, J Huisken, J van Loon and F Welten,
Philips Research Laboratories, Eindhoven, The Netherlands
4 2 51
10:00 A 50 MHz 70 mW 8-Tap Adaptive Equalizer/Viterbi
Sequence Detector in l ^um CMOS
G Uehara, C Wong, J Rudell and P Gray, University of
California, Berkeley, CA
4 3 55
10:25 A10 (am CMOS 60-MBaud Single-Chip QAM
Processor for Digital Radio Applications
E De Man, M Schulz and R Schmidmaier, Siemens, A G ,
Munich, Germany
4 4 59
10:50 A 200-MHz Quadrature Digital Synthesizer/Mixer in
0 8-^m CMOS
L Tan and H Samueli*, Broadband Telecom, Inc , Los
Angeles, CA, ‘University of California, Los Angeles, CA
CONTENTS
4 5 63
11:15 A Chip Set for 7 KHz Handfree Telephony
P LeScan, M Soler, F Perreal, G Martel E Closse, F
Balestro, P Senn, D Morche, J Jullien and G Le
Tourneur, France Telecom CNET, Grenoble, France
SESSION 5 - CALIFORNIA ROOM
Monday Morning
9:30 PROGRAMMABLE LOGIC ARCHITECTURES AND
APPLICATIONS
Chair: Kerry Pierce Co-Chair: John Turner
5 1 69
9:35 INVITED
An Overview of Technology, Architecture and CAD
Tools for Programmable Logic Devices
S Brown, University of Toronto, Toronto, Canada
5 2 77
10:25 RRANN: The Run-Time Reconfiguration Artificial
Neural Network
J Eldredge and B Hutchings, Brigham Young University,
Provo, UT
5 3 81
10:50 FPGA Implementation of FIR Filters Using Pipelined
Bit-Serial Canonical Signed Digit Multipliers
S He and M Torkelson, Lund University, Lund, Sweden
5 4 85
11:15 Using FPGAsto Prototype a Self-Timed Floating Point
Co-Processor
J Novak and E Brunvand, University of Utah, Salt Lake
City, UT
SESSION 6 - PRESIDIO ROOM
Monday Afternoon
2:00 VIDEO COMPRESSION AND CONSUMER
APPLICATIONS
Chair: Lauren ChristopherCo-Chair: Masao Nakaya
6 1 91
2:05 A Single Chip Multimedia Video Processor
K Balmer, N Ing-Simmons, P Moyse, I Robertson, J
Keay, M Hammes, E Oakland, R Simpson, G Barr and
D Roskell, Texas Instruments, Ltd , Bedford, United
Kingdom
6 2 95
2:30 A15 GIPS Video Signal Processor (VSP)
H Veendrick, O Popp, G Postunta and M Lecoutere,
Philips Research Laboratories, Eindhoven, The Netherlands
6 3 99
2:55 A12 GIP General Purpose Digital Image Processor
S Evans, S Walker, N Thacker, R Yates and P Ivey,
University of Sheffield, Sheffield, United Kingdom
6 4 103
3:20 Data Flow Processor for Multi-Standard Video Codec
B Lee, H Kwon, B Kim, D Still*, T Kopet*, and S
Magar*, Samsung Electronics Co Kyunggi-do, Korea,
*Array Microsystems, Colorado Springs, CO
6 5 107
3:45 A 162Mbit/s Variable Length Decoding Circuit Using
an Adaptive Tree Search Technique
Y Ooi, A Taniguchi and S Demura, NEC Corporation,
Kanagawa, Japan
6 6 HI
4:10 Multipurpose Scanning Rate Converter 1C for
Improved Quality Television
V D’Alto, C Heintz*, M Karlsson,**, A Cremonesi, A
Vindigni#, and S Dal Poz#, SGS-Thontson, Brianza, Italy,
*NOKIA Consumer Electronics, Bochum, Germany and
**Tampere, Finland, #SELECO, Pordenone, Italy
6 7 115
4:35 A Low Cost Application Specific Video Codec for
Consumer Video Phone
S Azirn, Crystal Semiconductor, Austin, TX, M Jahanghir,
Compression Labs Inc , San Jose, CA, R Aghevli, C
Holmqvist, J Mena, M Takla, M Yellayi, AT amp;T Bell
Labs , Allentown, PA, B Edwards, N Weste, TLW,
Burlington, MAand V Maheshwari, C-Cube, Milpitas CA
SESSION 7 - FRIARS/PADRE/SIERRA ROOMS
Monday Afternoon
2:00 SYNTHESIS FOR DIGITAL SYSTEMS amp; SILICON
Chair: James Lipntan Co-Chair: Herve Touati
7 1 121
2:05 INVITED
EDA and Electronic System Design
J Rowson, Redwood Design Automation Inc , San Jose,
CA
7 2 128
2:55 Improving Cell Libraries for Synthesis
K Scott and K Keutzer, Synopsys, Inc , Mountain View,
CA
7 3 132
3:20 Automatic Synthesis and the Cost of Testing
T Marchok and W Maly, Carnegie Mellon University,
Pittsburgh, PA
7 4 136
3:45 State Assignment for Low Power Dissipation
L Benini and G DeMicheli, Stanford University, Stanford,
CA
7 5 140
4:10 State Assignment for Low-Power FSM Synthesis Using
Genetic Local Search
E Olson and S Kang, University of Illinois, Urbana, IL
CONTENTS
a
7 6 144
4:35 Working Chips from High Level Synthesis: A Case
Study from Industry
R Hunter Delco Electronics Corp , Kokomo IN and T
Fuhrman, GM R amp;D Center Warren, MI and D Thomas,
Carnegie Mellon University Pittsburgh, PA
2:00 ANALOG CIRCUIT TECHNIQUES FOR
COMMUNICATIONS
Chair: Terri Fiez Co-Chair: Masao Hotta
8 1 151
2:05 INVITED
Radio Frequency Integrated Circuits for Portable
Communications
A Abidi, University of California, Los Angeles, CA
8 2 159
2:55 A Low Noise Integrated AMPS IF Filter
T Adachi, A Ishikawa, K Tomioka, S Hara, K Takasuka
and H Hisajima, Asahi Kasei Microsystems Tokyo, Japan
and A Barlow, Asahi Kasei Microsystems, San Diego, CA
8 3 163
3:20 10 7MHz Bandpass Delta-Sigma A/D Modulators
F Singor and M Snelgrove*, University of Toronto,
Toronto, Canada and *Carleton University, Ottawa,
Canada
8 4 167
3:45 A Versatile Monolithic 800kHz to 800MHz
Phase-Startable Oscillator
L Dobos and B Jensen, Tektronix, Beaverton, OR
8 5 171
4:10 A Low Noise CMOS Frequency Synthesizer with
Dynamic Bandwidth Control
M Bayer, T Chomicz, F James, P McEntarfer, D
Mijuskovic and J Porter, Motorola, Inc , Chandler, AZ
SESSION 9 - CALIFORNIA ROOM
Monday Afternoon
9 3 185
2:55 Programming Antifuses in Crosspoint’s FPGA
D Marple and L Cooke, Crosspoint Solutions, Inc , Santa
Clara, CA
9 4 189
3:20 SIPPOS (Single Poly Pure CMOS) EEPROM
Embedded FPGA by News Ring Interconnection and
Highway Path
K Ohsaki, N Asamoto, and Y Takaya, IBM, Shiga-ken,
Japan
9 5 193
3:45 A Novel Reprogrammable Interconnect Architecture
with Decoded RAM Storage
R Guo, H Nguyen, A Srinivasan, Q Nasir, H Cai, S Law
and A Mohsen, Aptix Corp , San Jose, CA
9 6 197
4:10 Architectures for a Real Time Classification Processor
M Robert, P Gorria*, J Miteran* S Turgis, University of
Montpellier, Montpellier, France, *University of
Bourgogne, Le Creusot, France
SESSION 10 - PRESIDIO ROOM
Tuesday Morning
8:30 APPLICATION-SPECIFIC DIGITAL SIGNAL
PROCESSING
Chair: Michael Thorn Co-Chair: Fang Lu
10 1 203
8:35 High Performance Multi-Channel Data Compression
Chip
E Nusinov and J Pasco-Anderson, Motorola, Mansfield,
MA
10 2 207
9:00 A Fast Single Chip Implementation of 8192 Complex
Points
E Bidet, C Joanblanq, P Senn, CNET, Grenoble, France
10 3 211
9:25 A Single Chip QCELP Vocoder for CDMA Digital
Cellular
J McDonough, C Chang, P Kantak, C Sakamaki, R
Singh and M Tsai, QUALCOMM, Inc , San Diego, CA
2:00 ADVANCES IN PROGRAMMABLE LOGIC
ARCHITECTURES
Chair: Teile Whitney Co-Chair: Jeffery Oppold
9 1 177
2:05 A Low Power Programmable Logic Device
Reconfigurable for 3 3V or 5 0V Operation During and
After Fabrication
C McClintock, W Leong, H Randhawa and J Watson,
Altera Corporation, San Jose CA
9 2 181
2:30 Minimizing Interconnection Delays in Array-based
FPGAs
M Khellah S Brown and Z Vranesic University of
Toronto, Ontario, Canada
10 4 215
9:50 A180 MHz 16 bit Multiplier Using Asynchronous Logic
Design Techniques
R Burford, X Fan and N Bergmann, Flinders University,
Adelaide, Australia
10 5 219
10:15 A Programmable Digital Signal Processor for Service
Adaptive Access
D Mitchler and S Aly, Bell Northern Research, Ontario,
Canada
10 6 223
10:40 A Flexible 8-channel Data Acquisition Device for Signal
Processing and Analysis
D McGrath, J Krisciunas and S Garverick*, General
Electric Corp , Schenectady, NY and *Case Western
Reserve University, Cleveland, OH
CONTENTS
10 7 227
11:05 A Real-Time Object Extraction Processor
R Nishimura, T Kinugasa, H Komatsu*, J Kamimura, T
Imaide, Hitachi Ltd , *Hitachi Video amp; Information
System, Inc , Yokohama, Japan
SESSION 11 - FRIARS/PADRE/SIERRA ROOMS
Tuesday Morning
8:30 SYNTHESIS AND OPTIMIZATION
Chair: Herve Touati Co-Chair: Paul Ainslie
11 1 233
8:35 Synthesizing Optimal Registerfile Architectures for
FPGA Technology
C Gebotys, University of Waterloo, Ontario, Canada
11 2 237
9:00 ILP Synthesis of Signal Processing Architectures with
Minimum Structural Complexity
B Haroun and B Sajjadi, Concordia University, Montreal,
Canada
11 3 241
9:25 Generating the Optimal Graph Representations from
the Instruction Set Tables of Circuits
C Chen and W-C Tseng, Syracuse University, Syracuse,
NY
11 4 245
9:50 Skew and Delay Minimization of High Speed CMOS
Circuits Using Stochastic Optimization
S Mehrotra, P Franzon and W Liu, North Carolina State
University, Raleigh, NC
11 5 249
10:15 Power Analysis for Semi-Custom Design
B George, G Yeap, M Wloka, S Tyler and D Gossain,
Motorola, Inc , Tentpe, AZ
11 6 253
10:40 POP: an efficient Performance Optimization algorithm
based on integrated approach
H Chang, Motorola, Austin, TX and J Abraham,
University of Texas, Austin, TX
SESSION 12 - GOLDEN WEST ROOM
Tuesday Morning
8:30 LOW-POWER, LOW-VOLTAGE DESIGNS AND
TECHNIQUES
Chair: Brian Fitzgerald Co-Chair: Larry Starr
12 1 259
8:35 TUTORIAL
Design of Portable Systems
A Chandrakasan, A Stratakos and R Brodersen,
University of California, Berkeley, CA and R Allmon,
Digital Equipment Corporation
12 2 267
9:25 Limitation of CMOS Supply-Voltage Scaling by
MOSFET Threshold-Voltage Variation
S Sun and P Tsui, Motorola, Austin, TX
12 3 271
9:50 Self-Adjusting Threshold-Voltage Scheme (SATS) For
Low-Voltage High-Speed Operation
T Kobayashi and T Sakurai, Toshiba, Mountain View, CA
12 4 275
10:15 High Sensitivity, Low Power, Silicon Magnetic Field
Detector
J Doyle and C Lyden, University College Cork, Cork,
Ireland
12 5 278
10:40 A High Speed, Low Power, Swing Restored
Pass-Transistor Logic Based Multiply and Accumulate
Circuit for Multimedia Applications
A Paranteswar, H Hara and T Sakurai, Toshiba Corp ,
Kawasaki, Japan
12 6 282
11:05 Adiabatic Dynamic Logic
A Dickinson and J Denker, AT amp;T Bell Laboratories,
Holmdel, NJ
SESSION 13 - CALIFORNIA ROOM
Tuesday Morning
8:30 STATISTICAL AND YIELD MODELING
Chair: Dileep Divekar Co-Chair: German Gutierrez
13 1 289
8:35 Yield Enhancement Prediction with Statistical Process
Simulations in an Advanced Poly-Emitter
Complementary Bipolar Technology
J Lopez-Serrano, S Koh*, T Crandell*, J Delgado*, H
Nicolay*, T Haycock* and A Strojwas, Carnegie Mellon
University, Pittsburgh, PA and ‘Harris Semiconductor,
Melbourne, FL
13 2 293
9:00 Parametric Yield Prediction of Complex, Mixed-Signal
ICs
M O’Leary and C Lyden, University College, Cork,
Ireland
13 3 297
9:25 Applying a Submicron Mismatch Model to Practical 1C
Design
C Guardiani, A Tomasini, J Benkoski, M Quarantelli*
and P Gubian*, SGS-Thomson Microelectronics, Agrate,
Italy and *Universita di Brescia, Brescia, Italy
13 4 301
9:50 Performance Modeling of Analog Circuits Using
Additive Regression Splines
C Chao and L Milor, University of Maryland, College
Park, MD
CONTENTS
t
13 5 305
10:15 A Moment Method for Statistical Analysis of High
Speed VLSI Interconnects
L Li, Q Zhang and M Nakhla, Carleton University,
Ottawa, Canada
13 6 309
10:40 Manufacturability Analysis Environment - MAPEX
H Heineken and W Maly, Carnegie Mellon University,
Pittsburgh, PA
13 7 313
11:05 Component Level Yield/Cost Model for Predicting VLSI
Manufacturability on Designs Using Mixed
Technologies, Circuitry, and Redundancy
S Domer, S Foertsch and G Raskin, Motorola Inc ,
Chandler, AZ
SESSION 14 - PRESIDIO ROOM
Tuesday Afternoon
2:00 AUTOMOTIVE AND SENSOR CIRCUIT TECHNIQUES
Chair: Larry Starr Co-Chair: Ken Au
14 1 319
2:05 TUTORIAL
1C Design Considerations for the Harsh Automotive
Electrical Environment
D Laude, Ford Microelectronics, Colorado Springs, CO
14 2 327
2:55 Dedicated Protective Functions of Automotive ICs and
Design Examples
A Lechner, D Draxelmayr, *H Inner, H Zitta, *J
Melbert, Siemens, Villach, Austria,*Munich, Germany
14 3 331
3:20 A Portable 3-Axis 11-Bit Shock Measurement Circuit
B DeGeeter, M Pierre, O Nys, V von Kaenel, M
Chevroulet and M Degrauwe CSEM, Neuchatel,
Switzerland
14 4 335
3:45 A Low Power Transponder 1C for High Performance
Identification Systems
U Kaiser and W Steinhagen, Texas Instruments
Deutschland GmbH, Freising, Germany
14 5 339
4:10 Silicon Range Finder - A Realtime Range Finding VLSI
Sensor
K Sato, A Yokoyama*, and S Inokuchi, Osaka University,
*Sony Corporation, Toyonaka, Japan
14 6 343
4:35 Maximum Entropy Co-Processor for Computed
Tomography
S Chang*, M Peckerar and C Marrian, *Department of
Defense, Ft Meade, MD and Naval Research Laboratory,
Washington, DC
SESSION 15 - FRIARS/PADRE/SIERRA ROOMS
Tuesday Afternoon
2:00 ANALOG HDL AND SYNTHESIS
Chair: Scott Cravens Co-Chair: Paul Ainslie
15 1 349
2:05 INVITED
Analog Hardware Description Languages
R Saleh, D Rhodes*, E Christen**, B Antao, University
of Illinois, Urbana, IL,*Army Research Lab, Ft
Monmouth, NJ, **Analogy, Inc , Beaverton, OR
15 2 357
2:55 Capture and Re-use of Analog Simulation Knowledge
R Henderson, M Hinners, P Nussbaum and L Astier,
Centre Suisse d’Electronique amp; Microtechnique, Neuchatel,
Switzerland
15 3 361
3:20 DORIC: Design of Optimal amp; Robust Integrated
Circuits
Z Daoud and C Spanos, University of California,
Berkeley, CA
15 4 365
3:45 Analog Circuit Synthesis for Large, Realistic Cells:
Designing a Pipelined A/D Converter with
ASTRX/OBLX
E Ochotta, L Carley, and R Rutenbar, Carnegie Mellon
University, Pittsburgh, PA
15 5 369
4:10 Top-Down, Constraint-Driven Design Methodology
Based Generation of n-bit Interpolative Current Source
D/A Converters
H Chang, E Liu, R Neff, E Felt, E Malavasi, E
Charbon, A Sangiovanni-Vincentelli and P Gray,
University of California, Berkeley, CA
15 6 373
4:35 A Methodology for Analog High-Level Synthesis
S Donnay, K Swings, G Gielen and W Sansen,
Katholieke Universiteit Leuven, Heverlee, Belgium
SESSION 16 - GOLDEN WEST ROOM
Tuesday Afternoon
2:00 WIRELESS COMMUNICATION LSIs
Chair: Jerry Molnar Co-Chair: Robert Cordell
16 1 379
2:05 INVITED
An All-CMOS Architecture for a Low-Power
Frequency- Hopped 900 MHz Spread Spectrum
Transceiver
J Min, A Rofougaran, H Samueli and A Abidi,
University of California, Los Angeles, Ca
16 2 383
2:55 A 1 2/ m CMOS Implementation of a Low-Power
900-MHz Mobile Radio Frequency Synthesizer
M Thamsirianunt and T Kwasniewski* MITEL, Kanata,
Canada, *Carleton University, Ottawa, Canada
CONTENTS
16 3 387
3:20 1 57 GHz Asynchronous and 1 4 GHz Dual-Modulus
l ^um CMOS Prescalers
R Rogenmoser, Q Huang and F Piazza, Swiss Federal
Institute of Technology, Zurich, Switzerland
16 4 391
3:45 A 0 7-mW/2-GHz Dual Modulus Prescaler 1C
Y Nakasha T Miyata, Y Watanabe, H Ochimizu, S
Kuroda and M Takikawa, Fujitsu Laboratories, Ltd ,
Atsugi, Japan
16 5 395
4:10 An Analog/Digital Interface for Cellular Telephony
N van Bavel, Oasis Design, Austin, TX and P Maulik, K
Albright, X -M Gong, Crystal Semiconductor Corp ,
Austin, TX
16 6 399
4:35 An Integrated 7t/4-Shift QPSK Baseband Modulator
Y Kobayashi, T Hida, K Sawada, K Hodohara, Y Ueda,
K Takasuka and A Barlow* Asahi Kasei Microsystems,
Tokyo, Japan, *Asahi Kasei Microsystems, San Diego, CA
17 7 429
4:35 Improved Estimation of the Switching Activity for
Reliability Prediction in VLSI Circuits
F Najm, University of Illinois, Urbana, IL
SESSION 18 - PRESIDIO ROOM
Tuesday Evening
8:00 EVENING PANEL - Organized by I Kizilyalli and W
Maly 433
Semiconductor Industry and ASICs in the Age of Mega-
Fabs
SESSION 19 - GOLDEN WEST ROOM
Tuesday Evening
8:00 EVENING PANEL - Organized by Y A Haque 435
Has Analog Simulation Capability Fundamentally
Improved in the Last Decade?
SESSION 17 - CALIFORNIA ROOM
Tuesday Afternoon
2:00 TEST AND RELIABILITY
Chair: Fadi Maamari Co-Chair: Peng Feng
17 1 405
2:05 lDDO Testing on a Custom Automotive 1C
S Mallarapu and A Hoffman, Delco Electronics Corp ,
Kokomo, IN
17 2 409
2:30 Diagnosing CMOS Bridging Faults with Stuck-At,
IDDQ, and Voting Model Fault Dictionaries
S Millman, Motorola, Tempe, AZ and J Acken, Intel
Corporation, Santa Clara, CA
17 3 413
2:55 Analog Testability Analysis and Fault Diagnosis using
Behavioral Modeling
E Liu, W Kao, E Felt and A Sangiovanni-Vincentelli*,
Cadence Design Systems, Inc , Dale City, CA and
*University of California, Berkeley, CA
17 4 417
3:20 Circuit Partitioning for Pipelined Pseudo-Exhaustive
Testing Using Simulated Annealing
H-Y Liou, T-T Lin, L-T Liu, C-K Cheng, University of
California, La Jolla, CA
17 5 421
3:45 iRULE: Fast Hot-Carrier Reliability Diagnosis Using
Macro-Models
C Teng W Sun, S Kang, P Fang* and J Yue*,
University of Illinois, Urbana, IL and *Advanced Micro
Device, Sunnyvale, CA
17 6 425
4:10 Slope Considerations in Probabilistic Simulation
G Stamoulis and I Hajj, University of Illinois, Urbana, IL
SESSION 20 • CALIFORNIA ROOM
Tuesday Evening
8:00 EVENING PANEL - Organized by S D Millman 437
Cycle Time Reduction: What is the Minimum?
SESSION 21 - PRESIDIO ROOM
Wednesday Morning
8:30 MIXED-MODE SIMULATION AND BEHAVIORAL
MODELING
Chair: Dundar Dumlugol Co-Chair: Shye-Jye Jou
21 1 441
8:35 INVITED
Benchmark Circuits for Mixed-Mode Simulators
R Saleh, S Jou*, D Overhauser**,X Xu, Y Wang**,
University of Illinois, Urbana, IL, *National Central
University, Taiwan, ROC, **Duke University, Durham,
NC
21 2 449
9:25 Behavioral Simulation for Analog System Design
Verification
B Antao, A Brodersen*, University of Illinois, Urbana,
IL, *Vanderbilt University, Nashville, TN
21 3 453
9:50 Behavioral Simulation Techniques for
Phase/Delay-Locked Systems
A Demir, E Liu, A Sangiovanni-Vincentelli and I
Vassiliou, University of California, Berkeley, CA
CONTENTS
i
21 4 457
10:15 Fully Symbolic Analysis of Large Analog Integrated
Circuits
J Hsu and C Sechen, University of Washington, Seattle,
WA
21 5 461
10:40 Efficient Symbolic Computation of Approximated
Small-Signal Characteristics
P Wambacq, F Fernandez, G Gielen and W Sansen,
Katholieke Universiteit Leuven, Heverlee, Belgium
21 6 465
11:05 Automated Load-Independent Cell Library
Macromodeling for Efficient and Accurate Waveform
Simulation
D Ciplickas and R Rohrer, Carnegie Mellon University,
Pittsburgh, PA
SESSION 22 - FRIARS/PADRE/SIERRA ROOMS
Wednesday Morning
8:30 1C FABRICATION TECHNOLOGY
Chair: Michiel Beunder Co-Chair: Isik Kizilyalli
22 1 471
8:35 TUTORIAL
Micro Systems Technology
J Fluitman, University of Twente, Enschede, The
Netherlands
22 2 479
9:25 Advanced High Performance CCD Technology for a
1/4 - Inch 560k Pixel IT-CCD Image Sensor
S Terakawa, Y Sano, T Imanishi, and Y Hiroshima,
Matsushita Electronics Corporation, Kyoto, Japan
22 3 484
9:50 Improved Reliability of Amorphous Silicon Anti-Fuse
Used in High Speed FPGA
S Nariani, C Gabriel and V Jain*, VLSI Technology,
San Jose, CA, *Intel Corp , Santa Clara, CA
22 4 488
10:15 An Advanced CMOS EPROM Technology for High
Speed/High Density Programmable Logic Devices
and Memory Applications
G Hu, R Madurawe*, M Cleeves, A Dejenfelt, C
Pass*, M Carpenter, P Zicolello, C Malmfeldt*, K
Norman*, Cypress Semiconductor, San Jose, CA, *Altera
Corporation, San Jose, CA
SESSION 23 - GOLDEN WEST ROOM
Wednesday Morning
8:30 DATA CONVERTERS
Chair: Venu Gopinathan Co-Chair: Corey Petersen
23 1 495
8:35 A 85-mW, 10-bit 40-MS/s ADC with Decimated
Parallel Architecture, K Nakamura
M Hotta, Hitachi, Ltd , Tokyo, Japan R Carley and D
Allstot, Carnegie Mellon University, Pittsburgh, PA
23 2 499
9:00 A 10-bit, 20-MS/s, 35-mW Pipeline A/D Converter
T Cho and P Gray, University of California, Berkeley,
CA
23 3 503
9:25 Parallel Delta-Sigma A/D Conversion
E King, F Aram, T Fiez and I Galton*, Washington
State University, Pullman, WA, *University of California,
Irvine, CA
23 4 509
9:50 Active Compensation of Parasitic Capacitances in a
10-bit 50 MHz CMOS D/A Converter
S Brigati, G Caiulo*, F Maloberti, G Torelli,
University of Pavia, Pavia, Italy, *Italtel Sit, Milan, Italy
23 5 511
10:15 A 130/1W DAC for Low-Power Video Systems
D Nairn, Queen’s University, Kingston, Ontario, Canada
23 6 515
10:40 A 12 bit 1MHz ADC with ImW Power Consumption
K Satou, K Tsuji, M Sahoda, H Otsuka, K Mori and
T Iida, Toshiba Corporation, Kawasaki, Japan
23 7 519
11:05 A Low Power 20 Bit Instrumentation Delta-Sigma
ADC
K Yamamura and A Nogi, Asahi Kasei Microsystems,
Tokyo, Japan, and A Barlow, Asahi Kasei Microsystems,
San Diego, CA
SESSION 24 - CALIFORNIA ROOM
Wednesday Morning
8:30 PHYSICAL DESIGN ANALYSIS AND OPTIMIZATION
Chair: Shojiro Mori Co-Chair: T Yanagawa
24 1 525
8:35 Imposing Tight Specifications on Analog ICs
Through Simultaneous Placement and Module
Optimization
E Charbon, *E Malavasi, *D Pandini, and A
Sangiovanni-Vincentelli, University of California,
Berkeley, CA, *University of Padova, Padova, Italy
24 2 529
9:00 Substrate-Aware Mixed-Signal Macro-Cell Placement
in WRIGHT
S Mitra, R Rutenbar, L Carley and D Allstot, Carnegie
Mellon University, Pittsburgh, PA
24 3 533
9:25 Mixed-Signal Noise-Decoupling via Simultaneous
Power Distribution Design and Cell Customization in
Rail
B Stanisic, R Rutenbar* and L Carley*, IBM
Rochester, MN, *Carnegie Mellon University, Pittsburgh,
PA
24 4 537
9:50 LAYIN: Toward a Global Solution for Parasitic
Coupling Modeling and Visualization
F Clement, E Zysman, M Kayal and M Declercq, Swiss
Federal Institute of Technology, Lausanne, Switzerland
CONTENTS
24 5 541
10:15 Transistor Size Optimization in Layout Design Rule
Migration
S Kishida, Y Shibayama, H Tanizaki, A Hanami, and I
Ohkura, Mitsubishi Electric Corporation, Hyogo, Japan
24 6 545
10:40 Compaction with Shape Optimization
K Okada, H Onodera and K Tamaru, Kyoto University,
Kyoto, Japan
24 7 549
11:05 Interconnect Design Using Convex Optimization
P Sancheti and S Sapatnekar, Iowa State University,
Ames, IA
SESSION 25 - PRESIDIO ROOM
Wednesday Afternoon
1:30 PLLs, NEURAL NETS AND HIGH-VOLTAGE
CIRCUITS
Chair: Takayasu Sakurai Co-Chair: Brian Fitzgerald
25 1 555
1:35 A 1 5% Jitter PLL Clock Generation System for a
500-MHz RISC Processor
H Igura, K Suzuki, T Nakayama, M Izumikawa, M
Nomura, J Goto, T Inoue, H Abiko, K Okabe, A Ono,
M Yamashina and H Yamada, NEC Corporation,
Kanagawa, Japan
25 2 559
2:00 PLL Timing Design Techniques for Large-scale,
High-speed, Low-power, and Low-cost SRAMS
K Nakamura, S Kuhara, T Kimura, M Takada, H
Suzuki, H Yoshida, and T Yamazaki, NEC Corporation,
Kanagawa, Japan
25 3 563
2:25 A GaAs on Si PLL Frequency Synthesizer 1C using
Chip on Chip Technology
S Sekine, K Takada, H Suzuki, K Kodama, S Moriya
and M Kubota, Fujitsu Ltd , Kanagawa, Japan
25 4 567
2:50 Digitally-Programmable Analog Cells for Artificial
Neural Networks
A Passos Almeida and J Franca, Instituto Superio
Tecnico, Lisban, Portugal
25 5 570
3:15 A Programmable Analogue CMOS Chip for High
Speed Image Processing Based on Cellular Neural
Networks
P Kinget and M Steyaert, Katholieke Universiteit
Leuven, Heverlee, Belgium
25 6 574
3:40 Design and Optimization of High Voltage Analog
and Digital Circuits Built in a Standard 5V CMOS
Technology
H Ballan, M Declercq and F Krummenacher, Swiss
Federal Institute of Technology, Lausanne, Switzerland
25 7 578
4:05 50-V LCD Driver Integrated in Standard 5-V CMOS
Process
V Valencic, H Ballan*, P Deval, B Hochet and M
Declercq*, MEAD Microelectronics, St Sulpice,
Switzerland, * EPFL, Lausanne, Switzerland
SESSION 26 - FRIARS/PADRE/SIERRA ROOMS
Wednesday Afternoon
1:30 HIGH PERFORMANCE MEMORIES AND GATE
ARRAYS
Chair: Manmohan Mittal Co-Chair: Ken Au
26 1 585
1:35 Embedded Memory Design for a Four Issue
Superscaler RISC Microprocessor
T Takayanagi, K Sawada, T Sakurai, Y Parameswar, S
Tanaka, N Ikumi, M Nagamatsu, Y Kondo amp;
K Minagawa, Toshiba Corp, Kawasaki, Japan amp;
J Brennan, P Hsu, P Rodman, J Bratt, J Scanlon, M
Tang, C Joshi and M Nofal, Silicon Graphic, Mt View,
CA
26 2 591
2:00 A 180MHz Multiple-Registered DRAM for Low-cost
2MB/chip Secondary Cache
H Iwamoto, N Watanabe, A Yamazaki, S Sawada, Y
Murai, Y Konishi, H Itoh, T Miyamoto and M
Kumanoya, Mitsubishi Electric Corp , Hyogo, Japan
26 3 595
2:25 A 400MHz, 300mW, 8kb, CMOS SRAM Macro with a
Current Sensing Scheme
M Izumikawa, K Suzuki, M Nomura, H Igura, H
Abiko, K Okabe, A Ono, T Nakayama, M Yamashina
and H Yamada, NEC Corp , Kanagawa, Japan
26 4 599
2:50 A 4 4-ns CMOS 54X54-b Multiplier Using
Pass-transistor Multiplexer
N Ohkubo, M Suzuki, T Shinbo, T Yamanaka, A
Shimizu, K Sasaki*, Y Nakagome, Hitachi, Tokyo,
Japan, * Hitachi America, Ltd , Brisbane, CA
26 5 603
3:15 Lean Integration: Achieving a Quantum Leap in
Performance and Cost of Logic LSIs
K Yano, Y Sasaki, K Rikino and K Seki, Hitachi,
Tokyo, Japan
26 6 607
3:40 0 5 micron Low-Power BiCMOS Gate Array for
B-ISDN 622 Mb/s User-Network Interface
Y Hayakawa, T Hanibuchi, K Sawada, M Ueda, K
Suda and S Kato, Mitsubishi Electric Corporation,
Hyogo, Japan
26 7 611
4:05 GaAs HBT Gate Array For High Performance ASICs
S Yinger, F Lee, R Huang, K Schneider and E Wang,
Rockwell International Corporation, Newbury Park, CA,
K Smith, M Penugonda, S Jacobs, T Carter, University
of Utah, Salt Lake City, UT
CONTENTS
i
SESSION 27 • GOLDEN WEST ROOM
Wednesday Afternoon
1:30 BROADBAND COMMUNICATIONS
Chair: Stefan Wurster Co-Chair: Robert Cordell
27 1 617
1:35 INVITED
Silicon Bipolar Chipset for SONET/SDH 10 Gbit/s
Fiber-Optic Links
I Andersson, B Rudberg and T Lewin, Ericsson Radar
Electronics Molndal, Sweden and M Reed S Planer
and S Sundaram Motorola SPS Mesa AZ
27 2 621
2:25 A 20 Gb/s 2:1 Data Selector
J Doernberg, A Armstrong* Hewlett Packard, Palo
Alto, CA, *Hewlett Packard, Santa Rosa, CA
27 3 625
2:50 A Monolithic 625Mb/s Data Recovery Circuit in
l fym CMOS
J Kang, W Liu and R Cavin, North Carolina State
University, Raleigh, NC
27 4 629
3:15 A Wide-Dynamic-Range and Extremely
High-Sensitivity CMOS Optical Receiver 1C Using
Feed-Forward Auto-Bias Adjustment
M Nakamura, N Ishihara, Y Akazawa and H Kimura,
NTT LSI Laboratories, Kanagawa Japan
28 3 651
2:25 A New Efficient Routing Method for Channel-less
Sea-of-Gates Arrays
M Terai, K Takahashi, H Shirota, and K Sato,
Mitsubishi Electric Corporation, Hyogo Japan
28 4 655
2:50 A Performance-Driven Routing Approach for Thick
Film MCMs
Q Yu, B Sandeep, J Lai and N Sherwani, Western
Michigan University, Kalamazoo, MI
28 5 659
3:15 Circuit Partitioning Under Capacity and I/O
Constraints
M Shih and E Kuh, University of California, Berkeley,
CA
28 6 663
3:40 Minimum Delay Placement with Influence of Nets
and Hierarchical Clustering
M Tanaka, Y Miyazawa* H Aizawa and M Minowa,
NEC Corporation, Kawasaki, Japan, *NEC Scientific
Information System Development Ltd , Kawasaki, Japan
28 7 667
4:05 A Multi-Port RAM Generator with Novel Memory Cell
for CMOS Sea-of-Gates
K Nii, H Maeno, T Osawa and S Iwade, Mitsubishi
Electric Corp , Hyogo, Japan
27 5 633
3:40 Low Power 11x320Mbps Parallel Transmitter/
Receiver LSIs for 2 4Gbps Optical Link
T Kamei, N Miyahara, T Taya and S Yamaoka, OKI
Electric Industry Co , Ltd , Tokyo, Japan
27 6 637
4:05 An Efficient Self-Timed Queue Architecture for ATM
Switch LSIs
H Kondoh, H Yamanaka*, M Ishiwaki, Y Matsuda and
M Nakaya, Mitsubishi Electric Corp , Itami, Japan and
‘Mitsubishi Electric Corp , Kamakura Japan
SESSION 28 - CALIFORNIA ROOM
Wednesday Afternoon
1:30 PHYSICAL DESIGN FOR ADVANCED
TECHNOLOGIES
Chair: Sachin Sapatnekar Co-Chair: H Onodera
28 1 643
1:35 Three-Layer Channel Routing for Standard Cells
with Column-Dependent Variable Over-the-Cell
Routing Capacities
T Koide, M Tsuchiya, S Wakabayashi and N Yoshida,
Hiroshima University, Higashi-Hiroshima, Japan
28 2 647
2:00 A New Triple-Layer OTC Channel Router
|
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| spelling | Custom Integrated Circuits Conference 16 1994 San Diego, Calif. Verfasser (DE-588)5147458-X aut Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 New York, NY 1994 670 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift gnd-content Institute of Electrical and Electronics Engineers Sonstige (DE-588)1692-5 oth HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018377286&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 |
| subject_GND | (DE-588)1071861417 |
| title | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 |
| title_auth | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 |
| title_exact_search | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 |
| title_full | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 |
| title_fullStr | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 |
| title_full_unstemmed | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference San Diego, California, May 1 - 4, 1994 |
| title_short | Proceedings of the IEEE 1994 Custom Integrated Circuits Conference |
| title_sort | proceedings of the ieee 1994 custom integrated circuits conference san diego california may 1 4 1994 |
| title_sub | San Diego, California, May 1 - 4, 1994 |
| topic_facet | Konferenzschrift |
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