Transistor sizing for timing optimization of combinational digital CMOS circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Mikrofilm Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
1990
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| Ausgabe: | [Mikrofiche-Ausg.] |
| Schlagworte: | |
| Beschreibung: | Mikrofiche-Ausg.: 2 Mikrofiches |
| Beschreibung: | IX, 102 Bl. graph. Darst. |
Internformat
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| 100 | 1 | |a Heusler, Lucas S. |e Verfasser |4 aut | |
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| 264 | 1 | |c 1990 | |
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| 500 | |a Mikrofiche-Ausg.: 2 Mikrofiches | ||
| 502 | |a Zürich, Techn. Hochsch., Diss. | ||
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| 650 | 0 | 7 | |a Schaltnetz |0 (DE-588)4052053-5 |2 gnd |9 rswk-swf |
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Datensatz im Suchindex
| _version_ | 1804140360542191616 |
|---|---|
| any_adam_object | |
| author | Heusler, Lucas S. |
| author_facet | Heusler, Lucas S. |
| author_role | aut |
| author_sort | Heusler, Lucas S. |
| author_variant | l s h ls lsh |
| building | Verbundindex |
| bvnumber | BV024396511 |
| classification_rvk | ZN 4960 |
| ctrlnum | (OCoLC)916439755 (DE-599)BVBBV024396511 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | [Mikrofiche-Ausg.] |
| format | Thesis Microfilm Book |
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| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV024396511 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:58:45Z |
| institution | BVB |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018375431 |
| oclc_num | 916439755 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | IX, 102 Bl. graph. Darst. |
| publishDate | 1990 |
| publishDateSearch | 1990 |
| publishDateSort | 1990 |
| record_format | marc |
| spelling | Heusler, Lucas S. Verfasser aut Transistor sizing for timing optimization of combinational digital CMOS circuits presented by Lucas Sebastian Heusler [Mikrofiche-Ausg.] 1990 IX, 102 Bl. graph. Darst. txt rdacontent h rdamedia he rdacarrier Mikrofiche-Ausg.: 2 Mikrofiches Zürich, Techn. Hochsch., Diss. Transistor (DE-588)4060646-6 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf Bemessung (DE-588)4005461-5 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Schaltnetz (DE-588)4052053-5 gnd rswk-swf Nichtlineare Optimierung (DE-588)4128192-5 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Schaltnetz (DE-588)4052053-5 s CMOS (DE-588)4010319-5 s Transistor (DE-588)4060646-6 s Nichtlineare Optimierung (DE-588)4128192-5 s DE-604 CMOS-Schaltung (DE-588)4148111-2 s Bemessung (DE-588)4005461-5 s |
| spellingShingle | Heusler, Lucas S. Transistor sizing for timing optimization of combinational digital CMOS circuits Transistor (DE-588)4060646-6 gnd CMOS (DE-588)4010319-5 gnd Bemessung (DE-588)4005461-5 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Schaltnetz (DE-588)4052053-5 gnd Nichtlineare Optimierung (DE-588)4128192-5 gnd |
| subject_GND | (DE-588)4060646-6 (DE-588)4010319-5 (DE-588)4005461-5 (DE-588)4148111-2 (DE-588)4052053-5 (DE-588)4128192-5 (DE-588)4113937-9 |
| title | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_auth | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_exact_search | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_full | Transistor sizing for timing optimization of combinational digital CMOS circuits presented by Lucas Sebastian Heusler |
| title_fullStr | Transistor sizing for timing optimization of combinational digital CMOS circuits presented by Lucas Sebastian Heusler |
| title_full_unstemmed | Transistor sizing for timing optimization of combinational digital CMOS circuits presented by Lucas Sebastian Heusler |
| title_short | Transistor sizing for timing optimization of combinational digital CMOS circuits |
| title_sort | transistor sizing for timing optimization of combinational digital cmos circuits |
| topic | Transistor (DE-588)4060646-6 gnd CMOS (DE-588)4010319-5 gnd Bemessung (DE-588)4005461-5 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Schaltnetz (DE-588)4052053-5 gnd Nichtlineare Optimierung (DE-588)4128192-5 gnd |
| topic_facet | Transistor CMOS Bemessung CMOS-Schaltung Schaltnetz Nichtlineare Optimierung Hochschulschrift |
| work_keys_str_mv | AT heuslerlucass transistorsizingfortimingoptimizationofcombinationaldigitalcmoscircuits |