Computer arithmetics for nanoelectronics:
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| Format: | Buch |
| Sprache: | English |
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Boca Raton [u.a.]
CRC Press
2009
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| Beschreibung: | XXVI, 825 S. Ill., graph. Darst. |
| ISBN: | 9781420066210 |
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| 100 | 1 | |a Šmerko, Vlad P. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Computer arithmetics for nanoelectronics |c Vlad P. Shmerko ; Svetlana N. Yanushkevich ; Sergey Edward Lyshevski |
| 264 | 1 | |a Boca Raton [u.a.] |b CRC Press |c 2009 | |
| 300 | |a XXVI, 825 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 650 | 4 | |a Mathematik | |
| 650 | 4 | |a Nanoelectronics |x Mathematics | |
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| 700 | 1 | |a Lyshevski, Sergey Edward |e Verfasser |0 (DE-588)123119359 |4 aut | |
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Datensatz im Suchindex
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| adam_text | COMPUTER ARITHMETICS FOR NANOELECTRONICS VLAD P. SHMERKO SVETLANA N.
YANUSHKEVICH SERGEY EDWARD LYSHEVSKI LFSS) CRC PRESS V J TAYLOR &
FRANCIS GROUP BOCA RATON LONDON NEW YORK CRC PRESS IS AN IMPRINT OF THE
TAYLOR & FRANCIS CROUP, AN INFORMA BUSINESS CONTENTS PREFACE XXI 1
INTRODUCTION 1 1.1 COMPUTATIONAL PARADIGMS FOR NANOCOMPUTING STRUCTURES
... 1 1.2 BIOLOGICAL INSPIRATION FOR COMPUTING 8 1.2.1 ARTIFICIAL NEURAL
NETWORKS 8 1.2.2 EVOLUTIONARY ALGORITHMS AND EVOLVABLE HARDWARE ... 10
1.2.3 SELF-ASSEMBLY 11 1.3 MOLECULAR COMPUTING DEVICES 14 1.4 FAULT
TOLERANCE 20 1.5 COMPUTING IN 3D 22 1.6 MULTIVALUED PROCESSING 23 1.7
FURTHER STUDY 24 2 COMPUTATIONAL NANOSTRUCTURES 29 2.1 INTRODUCTION 29
2.2 THEORETICAL BACKGROUND 30 2.3 ANALYSIS AND SYNTHESIS 31 2.3.1 DESIGN
HIERARCHY 32 2.3.2 TOP-DOWN DESIGN METHODOLOGY 33 2.3.3 BOTTOM-UP DESIGN
METHODOLOGY 34 2.3.4 DESIGN STYLES 35 2.3.5 MODELING AND SIMULATION 35
2.4 IMPLEMENTATION TECHNOLOGIES 36 2.5 PREDICTABLE TECHNOLOGIES 40 2.6
NANOELECTRONIC NETWORKS 42 2.6.1 CMOS-MOLECULAR ELECTRONICS 42 2.6.2
NEUROMORPHIC COMPUTING PARADIGM 42 2.6.3 INTERCONNECT 43 2.6.4
CARBON-NANOTUBE-BASED LOGIC DEVICES 44 2.6.5 CROSSBAR-BASED COMPUTING
STRUCTURES 44 2.6.6 NOISE 45 2.7 SWITCH-BASED COMPUTING STRUCTURES 46
2.7.1 SWITCHES 46 VLLL CONTENTS 2.7.2 SWITCH-BASED NETWORKS REPRESENTED
BY DECISION DIAGRAMS 48 2.8 SPATIAL COMPUTATIONAL NANOSTRUCTURES 51
2.8.1 GRAPH EMBEDDING PROBLEM 52 2.8.2 EMBEDDING DECISION TREE INTO
SPATIAL DIMENSIONS ... 53 2.9 FURTHER STUDY 54 3 BINARY ARITHMETIC 59
3.1 INTRODUCTION 59 3.2 POSITIONAL NUMBERS 60 3.2.1 THE DECIMAL SYSTEM
60 3.2.2 NUMBER RADIX 61 3.2.3 FRACTIONAL BINARY NUMBERS 64 3.2.4 WORD
SIZE 65 3.3 COUNTING IN A POSITIONAL NUMBER SYSTEM 65 3.4 BASIC
ARITHMETIC OPERATIONS IN VARIOUS NUMBER SYSTEMS .... 66 3.5 BINARY
ARITHMETIC 66 3.6 RADIX-COMPLEMENT REPRESENTATIONS 69 3.6.1 10 S AND 9 S
COMPLEMENT SYSTEMS 70 3.6.2 L S COMPLEMENT SYSTEM 71 3.6.3 2 S
COMPLEMENT 72 3.7 CONVERSION OF NUMBERS IN VARIOUS RADICES 73 3.8
OVERFLOW 76 3.9 IMPLEMENTATION OF BINARY ARITHMETIC 80 3.10 OTHER BINARY
CODES 80 3.10.1 GRAY CODE 81 3.10.2 WEIGHTED CODES 83 3.10.3
BINARY-CODED DECIMAL 84 3.11 FURTHER STUDY 85 4 RESIDUE ARITHMETIC 87
4.1 INTRODUCTION 87 4.2 THE BASICS OF RESIDUE ARITHMETIC 87 4.3 ADDITION
IN RESIDUE ARITHMETIC 89 4.4 MULTIPLICATION IN RESIDUE ARITHMETIC 89 4.5
COMPUTING POWERS IN RESIDUE ARITHMETIC 91 4.6 SOLVING MODULAR EQUATIONS
92 4.7 COMPLETE RESIDUE SYSTEMS 92 4.8 FURTHER STUDY 93 5 GRAPH-BASED
DATA STRUCTURES 97 5.1 INTRODUCTION 97 5.2 GRAPHS IN DISCRETE DEVICE AND
SYSTEM DESIGN 97 5.2.1 GRAPHS AT THE LOGICAL LEVEL 97 5.2.2 GRAPHS AT
THE PHYSICAL DESIGN LEVEL 99 IX 5.3 BASIC DEFINITIONS 99 5.3.1 DIRECTED
GRAPHS 100 5.3.2 FLOW GRAPHS 101 5.3.3 UNDIRECTED GRAPHS . 102 5.3.4 A
PATH IN A GRAPH 103 5.3.5 ISOMORPHISM 103 5.3.6 A SUBGRAPH AND SPANNING
TREE 104 5.3.7 CARTESIAN PRODUCT 106 5.3.8 PLANARITY 106 5.3.9
OPERATIONS ON GRAPHS 107 5.3.10 EMBEDDING 108 5.4 TREE-LIKE GRAPHS AND
DECISION TREES 108 5.4.1 BASIC DEFINITIONS 109 5.4.2 LATTICE TOPOLOGY OF
GRAPHS 110 5.4.3 H-TREES ILL 5.4.4 BINARY DECISION TREES AND FUNCTIONS
112 5.4.5 THE RELATIONSHIP BETWEEN DECISION TREES AND CUBE-LIKE GRAPHS
113 5.4.6 THE SIMPLIFICATION OF GRAPHS 113 5.5 VORONOI DIAGRAMS 115
5.5.1 DIRECT AND INVERSE VORONOI TRANSFORM 118 5.5.2 DISTANCE MAPPING OF
FEATURE POINTS 120 5.5.3 DISTANCE MAP 121 5.6 FURTHER STUDY 124
FOUNDATION OF BOOLEAN DATA STRUCTURES 131 6.1 INTRODUCTION 131 6.2
DEFINITION OF ALGEBRA OVER THE SET {0,1} 132 6.2.1 BOOLEAN ALGEBRA OVER
THE SET {0,1} 132 6.2.2 POSTULATES 132 6.2.3 THE PRINCIPLE OF DUALITY
133 6.2.4 SWITCH-BASED INTERPRETATION 136 6.2.5 BOOLEAN ALGEBRA OVER
BOOLEAN VECTORS 136 6.2.6 DEMORGAN S LAW 138 6.3 BOOLEAN FUNCTIONS 138
6.3.1 BOOLEAN FORMULAS 138 6.3.2 BOOLEAN FUNCTIONS 139 6.4 FUNDAMENTALS
OF COMPUTING BOOLEAN FUNCTIONS 140 6.4.1 LITERALS AND TERMS 141 6.4.2
MINTERMS AND MAXTERMS 141 6.4.3 CANONICAL SOP AND POS EXPRESSIONS 142
6.4.4 ALGEBRAIC CONSTRUCTION OF STANDARD SOP AND POS FORMS 145 6.5
PROVING THE VALIDITY OF BOOLEAN EQUATIONS 145 6.6 GATES 147 X CONTENTS
6.6.1 ELEMENTARY BOOLEAN FUNCTIONS 147 6.6.2 SWITCH MODELS FOR LOGIC
GATES 147 6.6.3 TIMING DIAGRAMS 150 6.6.4 PERFORMANCE PARAMETERS 153 6.7
LOCAL TRANSFORMATIONS 153 6.8 PROPERTIES OF BOOLEAN FUNCTIONS 154 6.8.1
SELF-DUAL BOOLEAN FUNCTIONS 155 6.8.2 MONOTONIE BOOLEAN FUNCTIONS 156
6.8.3 LINEAR FUNCTIONS 162 6.8.4 UNIVERSAL SET OF FUNCTIONS 163 6.9
FURTHER STUDY 166 7 BOOLEAN DATA STRUCTURES 169 7.1 INTRODUCTION 169 7.2
DATA STRUCTURE TYPES 170 7.3 RELATIONSHIPS BETWEEN DATA STRUCTURES 170
7.4 THE TRUTH TABLE 171 7.4.1 CONSTRUCTION OF THE TRUTH TABLE 171 7.4.2
TRUTH TABLES FOR INCOMPLETELY SPECIFIED FUNCTIONS . . . 172 7.4.3 TRUTH
VECTOR 173 7.4.4 MINTERM AND MAXTERM REPRESENTATIONS 174 7.4.5 REDUCTION
OF TRUTH TABLES 174 7.4.6 PROPERTIES OF THE TRUTH TABLE 175 7.4.7
DERIVING STANDARD SOP AND POS EXPRESSIONS FROM A TRUTH TABLE 176 7.5
K-MAP 176 7.5.1 REPRESENTATION OF STANDARD SOP AND POS EXPRESSIONS USING
K-MAPS 178 7.5.2 A K-MAP FOR A BOOLEAN FUNCTION OF TWO VARIABLES . . .
178 7.5.3 A K-MAP FOR A BOOLEAN FUNCTION OF THREE VARIABLES . . 178
7.5.4 A K-MAP FOR A BOOLEAN FUNCTION OF FOUR VARIABLES . . . 179 7.5.5 A
K-MAP FOR AN INCOMPLETELY SPECIFIED BOOLEAN FUNCTION 180 7.6 CUBE DATA
STRUCTURE 182 7.7 GRAPHICAL DATA STRUCTURE FOR CUBE REPRESENTATION 184
7.8 LOGIC NETWORKS 190 7.8.1 DESIGN GOALS 190 7.8.2 BASIC COMPONENTS OF
A LOGIC NETWORK 191 7.8.3 SPECIFICATION 193 7.8.4 NETWORK VERIFICATION
193 7.9 NETWORKS OF THRESHOLD GATES 195 7.9.1 THRESHOLD FUNCTIONS 195
7.9.2 MCCULLOCH-PITTS MODELS OF BOOLEAN FUNCTIONS 196 7.9.3 THRESHOLD
NETWORKS 197 7.10 BINARY DECISION TREES 198 CONTENTS XI 7.10.1
REPRESENTATION OF ELEMENTARY BOOLEAN FUNCTIONS USING DECISION TREES 199
7.10.2 MINTERM AND MAXTERM EXPRESSION REPRESENTATIONS USING DECISION
TREES 199 7.10.3 REPRESENTATION OF ELEMENTARY BOOLEAN FUNCTIONS BY
INCOMPLETE DECISION TREES 202 7.11 DECISION DIAGRAMS 204 7.12 FURTHER
STUDY 205 8 FUNDAMENTAL EXPANSIONS 209 8.1 INTRODUCTION 209 8.2 SHANNON
EXPANSION 211 8.2.1 EXPANSION WITH RESPECT TO A SINGLE VARIABLE 211
8.2.2 EXPANSION WITH RESPECT TO A GROUP OF VARIABLES .... 214 8.2.3
EXPANSION WITH RESPECT TO ALL VARIABLES 216 8.2.4 VARIOUS FORMS OF
SHANNON EXPANSIONS 218 8.3 SHANNON EXPANSION FOR SYMMETRIC BOOLEAN
FUNCTIONS 219 8.3.1 SYMMETRIC FUNCTIONS 220 8.3.2 PARTIALLY SYMMETRIC
BOOLEAN FUNCTIONS 221 8.3.3 TOTALLY SYMMETRIC BOOLEAN FUNCTIONS 221
8.3.4 DETECTION OF SYMMETRIC BOOLEAN FUNCTIONS 223 8.3.5 CHARACTERISTIC
SET 223 8.3.6 ELEMENTARY SYMMETRIC FUNCTIONS 224 8.3.7 OPERATIONS ON
ELEMENTARY SYMMETRIC FUNCTIONS .... 225 8.3.8 SHANNON EXPANSION WITH
RESPECT TO A GROUP OF SYMMETRIC VARIABLES 227 8.4 TECHNIQUES FOR
COMPUTING SYMMETRIC FUNCTIONS 227 8.4.1 COMPUTING PARTIALLY SYMMETRIC
FUNCTIONS 227 8.4.2 COMPUTING TOTALLY SYMMETRIC FUNCTIONS 228 8.4.3
CARRIER VECTOR 232 8.5 THE LOGIC TAYLOR EXPANSION 233 8.5.1 CHANGE IN A
DIGITAL SYSTEM 234 8.5.2 BOOLEAN DIFFERENCE 234 8.5.3 BOOLEAN DIFFERENCE
AND SHANNON EXPANSION 236 8.5.4 PROPERTIES OF BOOLEAN DIFFERENCE 237
8.5.5 THE LOGIC TAYLOR EXPANSION 238 8.6 GRAPHICAL REPRESENTATION OF
FUNDAMENTAL EXPANSIONS 244 8.6.1 SHANNON EXPANSION AS A DECISION TREE
NODE FUNCTION . . 244 8.6.2 MATRIX NOTATION OF THE NODE FUNCTION 245
8.6.3 USING SHANNON EXPANSION IN DECISION TREES 245 8.7 FURTHER STUDY :
248 9 ARITHMETIC OF THE POLYNOMIALS 255 9.1 INTRODUCTION 255 9.2 ALGEBRA
OF THE POLYNOMIAL FORMS 263 CONTENTS 9.2.1 THEORETICAL BACKGROUND 263
9.2.2 POLYNOMIALS FOR BOOLEAN FUNCTIONS 265 9.3 GF(2) ALGEBRA 266 9.3.1
OPERATIONAL AND FUNCTIONAL DOMAINS 269 9.3.2 THE FUNCTIONAL TABLE 270
9.3.3 THE FUNCTIONAL MAP 271 9.3.4 POLARIZED MINTERMS 271 9.4
RELATIONSHIP BETWEEN STANDARD SOP AND POLYNOMIAL FORMS . . 277 9.5 LOCAL
TRANSFORMATIONS FOR EXOR EXPRESSIONS 278 9.6 FACTORIZATION OF
POLYNOMIALS 279 9.7 VALIDITY CHECK FOR EXOR NETWORKS 281 9.8 FIXED- AND
MIXED-POLARITY POLYNOMIAL FORMS 282 9.8.1 FIXED-POLARITY POLYNOMIAL
FORMS 283 9.8.2 DERIVING POLYNOMIAL EXPRESSIONS FROM SOP FORMS . . . 286
9.8.3 CONVERSION BETWEEN POLARITIES 286 9.8.4 DERIVING POLYNOMIAL
EXPRESSIONS FROM K-MAPS 286 9.8.5 SIMPLIFICATION OF POLYNOMIAL
EXPRESSIONS 287 9.9 COMPUTING THE COEFFICIENTS OF POLYNOMIAL FORMS 288
9.9.1 MATRIX OPERATIONS OVER GF(2) 289 9.9.2 POLARIZED LITERALS AND
MINTERMS IN MATRIX FORM .... 290 9.9.3 COMPUTING THE COEFFICIENTS IN
FIXED-POLARITY FORMS . . . 293 9.10 DECISION DIAGRAMS 298 9.10.1
FUNCTION OF THE NODES 298 9.10.2 ALGEBRAIC FORM OF THE POSITIVE DAVIO
EXPANSIONS . . . . 299 9.10.3 ALGEBRAIC FORM OF THE NEGATIVE DAVIO
EXPANSION .... 300 9.10.4 MATRIX FORMS OF POSITIVE AND NEGATIVE DAVIO
EXPANSIONS 303 9.10.5 GATE-LEVEL IMPLEMENTATION OF SHANNON AND DAVIO
EXPANSIONS 303 9.11 TECHNIQUES FOR FUNCTIONAL DECISION TREE CONSTRUCTION
305 9.11.1 THE STRUCTURE OF FUNCTIONAL DECISION TREES 305 9.11.2 DESIGN
EXAMPLE: MANIPULATION OF PD AND ND NODES . 306 9.11.3 DESIGN EXAMPLE:
APPLICATION OF MATRIX TRANSFORMS . . . 306 9.11.4 DESIGN EXAMPLE:
MINTERM COMPUTING 310 9.12 FUNCTIONAL DECISION TREE REDUCTION 311 9.12.1
ELIMINATION RULE 311 9.12.2 MERGING RULE 312 9.13 FURTHER STUDY 315
OPTIMIZATION OF COMPUTATIONAL STRUCTURES 321 10.1 INTRODUCTION 321 10.2
MINTERM AND MAXTERM EXPANSIONS 322 10.3 OPTIMIZATION OF BOOLEAN
FUNCTIONS IN ALGEBRAIC FORM 325 10.3.1 THE CONSENSUS THEOREM 326 10.3.2
COMBINING TERMS 327 CONTENTS ** 10.3.3 ELIMINATING TERMS 327 10.3.4
ELIMINATING LITERALS 327 10.3.5 ADDING REDUNDANT TERMS 329 10.4
IMPLEMENTING SOP EXPRESSIONS USING LOGIC GATES 330 10.4.1 TWO-LEVEL
LOGIC NETWORKS 330 10.4.2 MULTILEVEL LOGIC NETWORKS 332 10.4.3
CONVERSION OF FACTORED EXPRESSIONS INTO LOGIC NETWORKS 334 10.5
MINIMIZATION OF BOOLEAN FUNCTIONS USING K-MAPS 335 10.6 OPTIMIZATION OF
BOOLEAN FUNCTIONS USING DECISION TREES AND DECISION DIAGRAMS 341 10.6.1
THE FORMAL BASIS FOR THE REDUCTION OF DECISION TREES AND DIAGRAMS 342
10.6.2 DECISION TREE REDUCTION RULES 342 10.7 DECISION DIAGRAMS FOR
SYMMETRIC BOOLEAN FUNCTIONS 351 10.8 MEASUREMENT OF THE EFFICIENCY OF
DECISION DIAGRAMS 356 10.9 EMBEDDING DECISION DIAGRAMS INTO LATTICE
STRUCTURES 356 10.10 FURTHER STUDY 358 11 MULTIVALUED DATA STRUCTURES
363 11.1 INTRODUCTION 363 11.2 REPRESENTATION OF MULTIVALUED FUNCTIONS
365 11.3 MULTIVALUED LOGIC 368 11.3.1 OPERATIONS OF MULTIVALUED LOGIC
368 11.3.2 MULTIVALUED ALGEBRAS 372 11.4 GALOIS FIELDS GF(M) 375 11.4.1
ALGEBRAIC STRUCTURE FOR GALOIS FIELD REPRESENTATIONS . . 378 11.4.2
GALOIS FIELD EXPANSIONS 378 11.5 FAULT MODELS BASED ON THE CONCEPT OF
CHANGE 379 11.6 POLYNOMIAL REPRESENTATIONS OF MULTIVALUED LOGIC
FUNCTIONS . . 381 11.7 POLYNOMIAL REPRESENTATIONS USING ARITHMETIC
OPERATIONS .... 388 11.7.1 DIRECT AND INVERSE ARITHMETIC TRANSFORMS 391
11.7.2 POLARITY 391 11.7.3 WORD-LEVEL REPRESENTATION 393 11.8
FUNDAMENTAL EXPANSIONS 396 11.8.1 LOGIC DIFFERENCE 396 11.8.2 LOGIC
TAYLOR EXPANSION OF A MULTIVALUED FUNCTION . . . 403 11.8.3 COMPUTING
POLYNOMIAL EXPRESSIONS 403 11.8.4 COMPUTING POLYNOMIAL EXPRESSIONS IN
MATRIX FORM . . 405 11.8.5 A/ -HYPERCUBE REPRESENTATION 406 11.9 FURTHER
STUDY 406 12 COMPUTATIONAL NETWORKS 413 12.1 INTRODUCTION 413 12.2 DATA
TRANSFER LOGIC 414 12.2.1 SHARED DATA PATH 414 CONTENTS 12.2.2
MULTIPLEXER 416 12.2.3 MULTIPLEXERS AND THE SHANNON EXPANSION THEOREM .
. . 418 12.2.4 SINGLE-BIT (2-TO-L) MULTIPLEXER 419 12.2.5 WORD-LEVEL
MULTIPLEXER 419 12.3 IMPLEMENTATION OF BOOLEAN FUNCTIONS USING
MULTIPLEXERS . . .421 12.3.1 MULTIPLEXER TREE 423 12.3.2 COMBINATION OF
DESIGN APPROACHES USING MULTIPLEXERS . 424 12.4 DEMULTIPLEXERS 429 12.5
DECODERS 432 12.6 IMPLEMENTATION OF BOOLEAN FUNCTIONS USING DECODERS . .
. . . 436 12.7 ENCODERS 439 12.7.1 COMPARATORS 441 12.7.2 CODE DETECTORS
442 12.8 DESIGN EXAMPLES: ADDERS AND MULTIPLIERS 443 12.9 DESIGN
EXAMPLE: MAGNITUDE COMPARATOR 452 12.10 DESIGN EXAMPLE: BCD ADDER 457
12.11 THE VERIFICATION PROBLEM 459 12.11.1 FORMAL VERIFICATION 461
12.11.2 EQUIVALENCE-CHECKING PROBLEM 461 12.11.3 DESIGN EXAMPLE 1:
FUNCTIONALLY EQUIVALENT NETWORKS . 462 12.11.4 DESIGN EXAMPLE 2:
VERIFICATION OF LOGIC NETWORKS USING DECISION DIAGRAMS 464 12.12
DECOMPOSITION 467 12.12.1 DISJOINT AND NONDISJOINT DECOMPOSITION 468
12.12.2 DECOMPOSITION CHART 468 12.12.3 DISJOINT BI-DECOMPOSITION 469
12.12.4 DESIGN EXAMPLE: THE OR TYPE BI-DECOMPOSITION .... 470 12.12.5
DESIGN EXAMPLE: AND TYPE BI-DECOMPOSITION 470 12.12.6 FUNCTIONAL
DECOMPOSITION USING DECISION DIAGRAMS . . 472 12.12.7 DESIGN EXAMPLE:
SHANNON DECOMPOSITION OF BOOLEAN FUNCTION WITH RESPECT TO A SUBFUNCTION
472 12.13 FURTHER STUDY 475 SEQUENTIAL LOGIC NETWORKS 481 13.1
INTRODUCTION 481 13.2 PHYSICAL PHENOMENA AND DATA STORAGE 481 13.3 BASIC
PRINCIPLES 482 13.3.1 FEEDBACK 483 13.3.2 CLOCKING TECHNIQUES 485 1314
DATA STRUCTURES FOR SEQUENTIAL LOGIC NETWORKS 485 13.4.1 CHARACTERISTIC
EQUATIONS 485 13.4.2 STATE TABLES AND DIAGRAMS 486 13.5 LATCHES 487
13.5.1 SR LATCH 487 13.5.2 GATED SR LATCH 489 CONTENTS XV 13.5.3 D LATCH
489 13.6 FLIP-FLOPS 492 13.6.1 THE MASTER-SLAVE PRINCIPLE IN FLIP-FLOP
DESIGN 492 13.6.2 D FLIP-FLOP 494 13.6.3 JK FLIP-FLOP 494 13.6.4 T
FLIP-FLOP 496 13.7 REGISTERS 497 13.7.1 STORING REGISTER 497 13.7.2
SHIFT REGISTER 500 13.7.3 OTHER SHIFT REGISTERS: FIFO AND LIFO 502 13.8
COUNTERS 502 13.8.1 BINARY COUNTERS 504 13.8.2 COUNTDOWN CHAINS 506 13.9
SEQUENTIAL LOGIC NETWORK DESIGN 507 13.10 MEALY AND MOORE MODELS OF
SEQUENTIAL NETWORKS 509 13.11 DATA STRUCTURES FOR ANALYSIS OF SEQUENTIAL
NETWORKS 509 13.11.1 STATE EQUATIONS 510 13.11.2 EXCITATION AND OUTPUT
EQUATIONS 511 13.11.3 STATE TABLE 511 13.11.4 STATE DIAGRAM 513 13.12
ANALYSIS OF SEQUENTIAL NETWORKS WITH VARIOUS TYPES OF FLIP-FLOPS 514
13.12.1 ANALYSIS OF A SEQUENTIAL NETWORK WITH D FLIP-FLOPS . . . 514
13.12.2 ANALYSIS OF A SEQUENTIAL NETWORK WITH JK FLIP-FLOPS . . 514
13.12.3 ANALYSIS OF A SEQUENTIAL NETWORK WITH T FLIP-FLOPS . . . 516
13.13 TECHNIQUES FOR THE SYNTHESIS OF SEQUENTIAL NETWORKS 517 13.13.1
SYNTHESIS OF A SEQUENTIAL NETWORK USING D FLIP-FLOPS . . 519 13.13.2
SYNTHESIS OF SEQUENTIAL NETWORKS USING JK FLIP-FLOPS . .519 13.13.3
SYNTHESIS OF SEQUENTIAL NETWORKS USING T FLIP-FLOPS . . . 522 13.14
REDESIGN 522 13.15 FURTHER STUDY 524 14 MEMORY DEVICES FOR BINARY DATA
527 14.1 INTRODUCTION 527 14.2 PROGRAMMABLE DEVICES 528 14.3
RANDOM-ACCESS MEMORY 531 14.3.1 MEMORY ARRAY 531 14.3.2 WORDS 532 14.3.3
ADDRESS 533 14.3.4 MEMORY CAPACITY 533 14.3.5 WRITE AND READ OPERATIONS
534 14.3.6 ADDRESS MANAGEMENT 535 14.4 READ-ONLY MEMORY 535 14.4.1
PROGRAMMING ROM 536 14.4.2 PROGRAMMING THE DECODER 537 14.4.3
COMBINATIONAL LOGIC NETWORK IMPLEMENTATION 537 CONTENTS 14.5 MEMORY
EXPANSION 538 14.6 PROGRAMMABLE LOGIC 540 14.6.1 PROGRAMMABLE LOGIC
ARRAY (PLA) 541 14.6.2 THE PLA S CONNECTION MATRICES 541 14.6.3
IMPLEMENTATION OF BOOLEAN FUNCTIONS USING PLAS . . . 543 14.6.4
PROGRAMMABLE ARRAY LOGIC 544 14.6.5 USING PLAS AND PALS FOR EXOR
POLYNOMIAL COMPUTING 545 14.7 FIELD PROGRAMMABLE GATE ARRAYS 545 14.8
FURTHER STUDY 548 SPATIAL COMPUTING STRUCTURES 551 15.1 INTRODUCTION 551
15.2 THE FUNDAMENTAL PRINCIPLES OF A 3D COMPUTING 554 15.3 SPATIAL
STRUCTURES 555 15.4 HYPERCUBE DATA STRUCTURE 557 15.5 ASSEMBLING OF
HYPERCUBES 559 15.6 A/*-HYPERCUBE 560 15.6.1 EXTENSION OF A HYPERCUBE TO
A^-HYPERCUBE 561 15.6.2 DEGREE OF FREEDOM AND ROTATION 561 15.6.3
COORDINATE DESCRIPTION 562 15.6.4 A/ -HYPERCUBE DESIGN FOR N 3
DIMENSIONS 565 15.7 EMBEDDING A BINARY DECISION TREE INTO AN AMRYPERCUBE
. . . 566 15.8 ASSEMBLING A^-HYPERCUBES 569 15.8.1 INCOMPLETE
A -HYPERCUBES 570 15.8.2 EMBEDDING TECHNIQUE 570 15.9 REPRESENTATION OF
J F- HYPERCUBES USING H-TREE 571 15.10 SPATIAL TOPOLOGICAL MEASUREMENTS
573 15.11 FURTHER STUDY 576 LINEAR CELLULAR ARRAYS 583 16.1 INTRODUCTION
583 16.2 LINEAR ARRAYS BASED ON SYSTOLIC COMPUTING PARADIGM 586 16.2.1
TERMINOLOGY 586 16.2.2 DESIGN PRINCIPLES OF PARALLEL-PIPELINE COMPUTING
STRUCTURES 587 16.2.3 DESIGN PHASES 588 16.2.4 FORMAL DESCRIPTION OF A
LINEAR SYSTOLIC ARRAY 588 16.2.5 IMPLEMENTATION 590 16.2.6 COMPUTING
POLYNOMIAL FORMS USING LOGICAL OPERATIONS 592 16.2.7 COMPUTING
DIFFERENCES USING LOGICAL OPERATIONS .... 594 16.2.8 COMPUTING
POLYNOMIAL FORMS USING ARITHMETIC OPERATIONS 597 16.2.9 COMPUTING
DIFFERENCES USING ARITHMETIC OPERATIONS . . 597 16.2.10 COMPUTING WALSH
EXPRESSIONS 599 CONTENTS XVN 16.2.11 COMPATIBILITY OF POLYNOMIAL DATA
STRUCTURES 599 16.3 SPATIAL SYSTOLIC ARRAYS 601 16.3.1 3D CELLULAR ARRAY
DESIGN 601 16.3.2 3D SYSTOLIC ARRAY DESIGN USING EMBEDDING TECHNIQUES .
601 16.3.3 3D HYPERCUBE SYSTOLIC ARRAYS 603 16.4 LINEAR ARRAYS BASED ON
LINEAR DECISION DIAGRAMS 604 16.4.1 GROUPING 606 16.4.2 COMPUTING THE
COEFFICIENTS 608 16.4.3 WEIGHT ASSIGNMENT 609 16.4.4 MASKING 611 16.5
LINEAR MODELS OF ELEMENTARY FUNCTIONS 611 16.5.1 BOOLEAN FUNCTIONS OF
TWO AND THREE VARIABLES 611 16.5.2 FUNDAMENTAL THEOREMS OF LINEARIZATION
611 16.5.3 GARBAGE FUNCTIONS 613 16.5.4 GRAPHICAL REPRESENTATION OF
LINEAR MODELS 614 16.6 LOGIC NETWORKS AND LINEAR DECISION DIAGRAMS 615
16.7 LINEAR MODELS FOR LOGIC NETWORKS 619 16.8 LINEAR MODELS FOR
MULTIVALUED LOGIC NETWORKS 620 16.8.1 APPROACH TO LINEARIZATION 621
16.8.2 MANIPULATION OF THE LINEAR MODEL 623 16.8.3 LIBRARY OF LINEAR
MODELS OF MULTIVALUED GATES 625 16.8.4 REPRESENTATION OF MULTIVALUED
LOGIC NETWORKS 626 16.8.5 LINEAR DECISION DIAGRAMS 628 16.9 LINEAR
WORD-LEVEL REPRESENTATION OF MULTIVALUED FUNCTIONS USING LOGIC
OPERATIONS 628 16.9.1 LINEAR WORD-LEVEL FOR MAX EXPRESSIONS 628 16.10 3D
COMPUTING ARRAYS DESIGN 632 16.11 FURTHER STUDY 632 17 INFORMATION AND
DATA STRUCTURES 637 17.1 INTRODUCTION 637 17.2 INFORMATION-THEORETIC
MEASURES 637 17.3 INFORMATION-THEORETIC MEASURES 641 17.3.1 QUANTITY OF
INFORMATION 642 17.3.2 CONDITIONAL ENTROPY AND RELATIVE INFORMATION 642
17.3.3 ENTROPY OF A VARIABLE AND A FUNCTION 644 17.3.4 MUTUAL
INFORMATION 646 17.3.5 INTERPRETATION OF MUTUAL INFORMATION 647 17.3.6
CONDITIONAL MUTUAL INFORMATION 648 17.4 INFORMATION MEASURES OF
ELEMENTARY BOOLEAN FUNCTION OF TWO VARIABLES 648 17.5
INFORMATION-THEORETIC MEASURES IN DECISION TREES AND DIAGRAMS 651 17.5.1
DECISION TREE INDUCTION 652 17.5.2 INFORMATION-THEORETIC NOTATION OF
SHANNON AND DAVIO EXPANSION 652 XVIII CONTENTS 17.5.3 OPTIMIZATION OF
VARIABLE ORDERING IN A DECISION TREE . . 655 17.6 INFORMATION-THEORETIC
MEASURES IN MULTIVALUED FUNCTIONS . . . 656 17.6.1 INFORMATION NOTATION
OF S EXPANSION 657 17.6.2 INFORMATION NOTATIONS OF PD AND ND EXPANSION
.... 660 17.6.3 INFORMATION CRITERION FOR DECISION TREE DESIGN 660
17.6.4 REMARKS ON INFORMATION-THEORETIC MEASURES IN DECISION DIAGRAMS
662 17.7 TERNARY AND PSEUDO-TERNARY DECISION TREES 663 17.8 FURTHER
STUDY 665 18 DESIGN FOR TESTABILITY 673 18.1 INTRODUCTION 673 18.2 FAULT
MODELS 675 18.2.1 THE SINGLE STUCK-AT MODEL 676 18.2.2 FAULT COVERAGE
677 18.3 CONTROLLABILITY AND OBSERVABILITY 678 18.3.1 OBSERVABILITY AND
BOOLEAN DIFFERENCES 681 18.3.2 ENHANCING OBSERVABILITY AND
CONTROLLABILITY 683 18.3.3 DETECTION OF STUCK-AT FAULTS 685 18.3.4
TESTING DECISION-TREE-BASED LOGIC NETWORKS 689 18.4 FUNCTIONAL DECISION
DIAGRAMS FOR COMPUTING BOOLEAN DIFFERENCES 690 18.5 RANDOM TESTING 691
18.6 DESIGN FOR TESTABILITY TECHNIQUES 693 18.6.1 SELF-CHECKING LOGIC
NETWORKS 693 18.6.2 BUILT-IN SELF-TEST (BIST) 693 18.6.3 EASILY TESTABLE
EXOR LOGIC NETWORKS 694 18.6.4 IMPROVING TESTABILITY USING LOCAL
TRANSFORMATIONS . . . 695 18.7 FURTHER STUDY 696 19 ERROR DETECTION AND
ERROR CORRECTION 699 19.1 INTRODUCTION 699 19.2 CHANNEL MODELS 702 19.3
THE SIMPLEST ERROR-DETECTING NETWORK 704 19.3.1 ERROR CORRECTION 707
19.4 DISCRETE MEMORYLESS CHANNEL 710 19.5 LINEAR BLOCK CODES 715 19.5.1
VECTOR SPACES 715 19.5.2 GENERATOR MATRIX, PARITY CHECK MATRIX, SYNDROME
. . 716 19.5.3 STANDARD ARRAY AND ERROR CORRECTION 718 19.5.4 DISTANCE
AND ERROR-CONTROL CAPABILITY 719 19.5.5 OPTIMAL DECODER 721 19.6 CYCLIC
CODES 722 19.6.1 SYSTEMATIC ENCODING 724 19.6.2 IMPLEMENTATION OF MODULO
G(X) DIVISION 725 CONTENTS XIX 19.7 BLOCK CODES 727 19.7.1 HAMMING CODES
727 19.7.2 BCH CODES 729 19.7.3 REED-SOLOMON CODES 730 19.8 ARITHMETIC
CODES 735 19.8.1 AN CODES 736 19.8.2 SEPARATE CODES 738 19.8.3 RESIDUE
CODES 739 19.9 FUERTHER STUDY 740 20 NATURAL COMPUTING 745 20.1
INTRODUCTION 745 20.2 INTERMEDIATE DATA STRUCTURES 749 20.3 QUANTUM DOT
PHENOMENA ENCODING 754 20.4 COMPLEMENTARY BIOMOLECULAR PHENOMENA
ENCODING 757 20.5 FRACTAL-BASED MODELS FOR SELF-ASSEMBLY 767 20.5.1
SIERPINSKI TRIANGLE FOR BOOLEAN FUNCTIONS 768 20.5.2 TRANSEUNT TRIANGLES
FOR BOOLEAN FUNCTIONS 770 20.5.3 FORWARD AND INVERSE PROCEDURES 772
20.5.4 THE NUMBER OF SELF-SIMILAR TRIANGLES 775 20.5.5 TRANSEUNT
TRIANGLES AND DECISION TREES 777 20.5.6 USING TRANSEUNT TRIANGLES FOR
REPRESENTATION OF MIXED-POLARITY POLYNOMIALS 780 20.5.7 TRANSEUNT
TRIANGLES FOR THE REPRESENTATION OF MULTIVALUED LOGIC FUNCTIONS 780
20.5.8 SIERPINSKI TRIANGLE GENERATION USING CELLULAR AUTOMATA 782 20.6
EVOLUTIONARY LOGIC NETWORK DESIGN 784 20.6.1 TERMINOLOGY OF EVOLUTIONARY
ALGORITHMS 784 20.6.2 DESIGN STYLE 786 20.6.3 CODING OF A TARGET DESIGN
STYLE 788 20.6.4 DESIGN EXAMPLE 790 20.6.5 INFORMATION ESTIMATIONS AS
FITNESS FUNCTION 791 20.6.6 PARTITIONING OF LOGIC NETWORK SEARCH SPACE
794 20.6.7 2-DIGIT TERNARY ADDER 795 20.6.8 2-DIGIT TERNARY MULTIPLIER
796 20.7 NEURAL-BASED COMPUTING 797 20.7.1 COMPUTING PARADIGM 797 20.7.2
NEURON CELLS 799 20.7.3 RELAXATION 799 20.7.4 IMPROVED HOPFIELD NETWORK
801 20.7.5 DESIGN EXAMPLE 802 20.8 FURTHER STUDY 805 INDEX 815
|
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| author | Šmerko, Vlad P. Januškevič, Svetlana N. Lyshevski, Sergey Edward |
| author_GND | (DE-588)123119359 |
| author_facet | Šmerko, Vlad P. Januškevič, Svetlana N. Lyshevski, Sergey Edward |
| author_role | aut aut aut |
| author_sort | Šmerko, Vlad P. |
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| building | Verbundindex |
| bvnumber | BV023805609 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.84 |
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| callnumber-sort | TK 47874.84 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| ctrlnum | (OCoLC)276225078 (DE-599)BVBBV023805609 |
| dewey-full | 621.381 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381 |
| dewey-search | 621.381 |
| dewey-sort | 3621.381 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV023805609 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:37:12Z |
| institution | BVB |
| isbn | 9781420066210 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017447784 |
| oclc_num | 276225078 |
| open_access_boolean | |
| owner | DE-634 DE-29T |
| owner_facet | DE-634 DE-29T |
| physical | XXVI, 825 S. Ill., graph. Darst. |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | CRC Press |
| record_format | marc |
| spelling | Šmerko, Vlad P. Verfasser aut Computer arithmetics for nanoelectronics Vlad P. Shmerko ; Svetlana N. Yanushkevich ; Sergey Edward Lyshevski Boca Raton [u.a.] CRC Press 2009 XXVI, 825 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Mathematik Nanoelectronics Mathematics Computerarithmetik (DE-588)4135485-0 gnd rswk-swf Nanoelektronik (DE-588)4732034-5 gnd rswk-swf Nanoelektronik (DE-588)4732034-5 s DE-604 Computerarithmetik (DE-588)4135485-0 s Januškevič, Svetlana N. Verfasser aut Lyshevski, Sergey Edward Verfasser (DE-588)123119359 aut GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017447784&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Šmerko, Vlad P. Januškevič, Svetlana N. Lyshevski, Sergey Edward Computer arithmetics for nanoelectronics Mathematik Nanoelectronics Mathematics Computerarithmetik (DE-588)4135485-0 gnd Nanoelektronik (DE-588)4732034-5 gnd |
| subject_GND | (DE-588)4135485-0 (DE-588)4732034-5 |
| title | Computer arithmetics for nanoelectronics |
| title_auth | Computer arithmetics for nanoelectronics |
| title_exact_search | Computer arithmetics for nanoelectronics |
| title_full | Computer arithmetics for nanoelectronics Vlad P. Shmerko ; Svetlana N. Yanushkevich ; Sergey Edward Lyshevski |
| title_fullStr | Computer arithmetics for nanoelectronics Vlad P. Shmerko ; Svetlana N. Yanushkevich ; Sergey Edward Lyshevski |
| title_full_unstemmed | Computer arithmetics for nanoelectronics Vlad P. Shmerko ; Svetlana N. Yanushkevich ; Sergey Edward Lyshevski |
| title_short | Computer arithmetics for nanoelectronics |
| title_sort | computer arithmetics for nanoelectronics |
| topic | Mathematik Nanoelectronics Mathematics Computerarithmetik (DE-588)4135485-0 gnd Nanoelektronik (DE-588)4732034-5 gnd |
| topic_facet | Mathematik Nanoelectronics Mathematics Computerarithmetik Nanoelektronik |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017447784&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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