The art of analog layout:
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ
Prentice Hall
2006
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| Ausgabe: | 2. ed., Internat. ed. |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXI, 648 S. graph. Darst. |
| ISBN: | 013129329X |
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MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV023804511 | ||
| 003 | DE-604 | ||
| 005 | 20090426000000.0 | ||
| 007 | t | ||
| 008 | 081119s2006 d||| |||| 00||| eng d | ||
| 020 | |a 013129329X |9 0-13-129329-X | ||
| 035 | |a (OCoLC)254457958 | ||
| 035 | |a (DE-599)BVBBV023804511 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 | ||
| 082 | 0 | |a 621.3815 | |
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 100 | 1 | |a Hastings, Alan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a The art of analog layout |c Alan Hastings |
| 250 | |a 2. ed., Internat. ed. | ||
| 264 | 1 | |a Upper Saddle River, NJ |b Prentice Hall |c 2006 | |
| 300 | |a XXI, 648 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Layout |g Mikroelektronik |0 (DE-588)4264372-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Layout |g Mikroelektronik |0 (DE-588)4264372-7 |D s |
| 689 | 1 | |5 DE-604 | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017446687&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-017446687 | ||
Datensatz im Suchindex
| _version_ | 1804139003799142400 |
|---|---|
| adam_text | IMAGE 1
THE ART OF ANALOG LAYOUT
SECOND EDITION
ALAN HASTINGS
3 EARSON
PEARSON EDUCATION INTERNATIONAL
IMAGE 2
CONTENTS
PREFACE TO THE SECOND EDITION XVII PREFACE TO THE FIRST EDITION XIX
ACKNOWLEDGMENTS XXI
1 DEVICE PHYSICS 1
1.1 SEMICONDUCTORS 1
1.1.1. GENERATION AND RECOMBINATION 4 1.1.2. EXTRINSIC SEMICONDUCTORS 6
1.1.3. DIFFUSION AND DRIFT 9 1.2 PN JUNCTIONS 11
1.2.1. DEPLETION REGIONS 11 1.2.2. PN DIODES 13 1.2.3. SCHOTTKY DIODES
16 1.2.4. ZENER DIODES 18 1.2.5. OHMIC CONTACTS 19 1.3 BIPOLAR JUNCTION
TRANSISTORS 21
1.3.1. BETA 23
1.3.2. I-V CHARACTERISTICS 24 1.4 MOS TRANSISTORS 25
1.4.1. THRESHOLDVOLTAGE 27 1.4.2. I-V CHARACTERISTICS 29 1.5 JFET
TRANSISTORS 32
1.6 SUMMARY 34
1.7 EXERCISES 35
2 SEMICONDUCTOR FABRICATION 37 2.1 SILICON MANUFACTURE 37
2.1.1. CRYSTAL GROWTH 38 2.1.2. WAFER MANUFACTURING 39 2.1.3. THE
CRYSTAL STRUCTURE OF SILICON 39 2.2 PHOTOLITHOGRAPHY 41
2.2.1. PHOTORESISTS 41 2.2.2. PHOTOMASKS AND RETICLES 42 2.2.3.
PATTERNING 43 2.3 OXIDE GROWTH AND REMOVAL 43 2.3.1. OXIDE GROWTH AND
DEPOSITION 44 2.3.2. OXIDE REMOVAL 45 2.3.3. OTHER EFFECTS OF OXIDE
GROWTH AND REMOVAL 47 2.3.4. LOCAL OXIDATION OF SILICON (LOCOS) 49 2.4
DIFFUSION AND ION IMPLANTATION 50 2.4.1. DIFFUSION 51
2.4.2. OTHER EFFECTS OF DIFFUSION 53 2.4.3. ION IMPLANTATION 55
VLL
IMAGE 3
VUEI CONTENTS
M-
2.5 SILICON DEPOSITION AND ETCHING 57
2.5.1. EPITAXY 57
2.5.2. POLYSILICON DEPOSITION 59 2.5.3. DIELECTRIC ISOLATION 60 2.6
METALLIZATION 62
2.6.1. DEPOSITION AND REMOVAL OF ALUMINUM 63 2.6.2. REFRACTORY BARRIER
METAL 65 2.6.3. SILICIDATION 67
2.6.4. INTERLEVEL OXIDE, INTERLEVEL NITRIDE, AND PROTECTIVE OVERCOAT 69
2.6.5. COPPER METALLIZATION 71 2.7 ASSEMBLY 73
2.7.1. MOUNT AND BOND 74
2.7.2. PACKAGING 77
2.8 SUMMARY 78
2.9 EXERCISES 78
3 REPRESENTATIVE PROCESSES 80 3.1 STANDARD BIPOLAR 81
3.1.1. ESSENTIAL FEATURES 81
3.1.2. FABRICATION SEQUENCE 82 STARTING MATERIAL 82 N-BURIED LAYER 82
EPITAXIAL GROWTH 83 ISOLATION DIFFUSION 83
DEEP-N+ 83
BASE IMPLANT 84
EMITTER DIFFUSION 84
CONTACT 85
METALLIZATION 85
PROTECTIVE OVERCOAT 86 3.1.3. AVAILABLE DEVICES 86 NPN TRANSISTORS 86
PNP TRANSISTORS 88
RESISTORS 90
CAPACITORS 92
3.1.4. PROCESS EXTENSIONS 93 UP-DOWN ISOLATION 93 DOUBLE-LEVEL METAL 94
SCHOTTKY DIODES 94
HIGH-SHEET RESISTORS 94 SUPER-BETA TRANSISTORS 96 3.2 POLYSILICON-GATE C
M OS 96
3.2.1. ESSENTIAL FEATURES 97
3.2.2. FABRICATION SEQUENCE 98 STARTING MATERIAL 98 EPITAXIAL GROWTH 98
N-WELL DIFFUSION 98
INVERSE MOAT 99
CHANNEL STOP IMPLANTS 100 LOCOS PROCESSING AND DUMMY GATE OXIDATION 100
THRESHOLD ADJUST 101
IMAGE 4
CONTENTS IX
POLYSILICON DEPOSITION AND PATTERNING 102 SOURCE/DRAIN IMPLANTS 102
CONTACTS 103 METALLIZATION 103 PROTECTIVE OVERCOAT 103 3.2.3. AVAILABLE
DEVICES 104
NMOS TRANSISTORS 104 PMOS TRANSISTORS 106 SUBSTRATE PNP TRANSISTORS 107
RESISTORS 107
CAPACITORS 109 3.2.4. PROCESS EXTENSIONS 109 DOUBLE-LEVEL METAL 110
SHALLOW TRENCH ISOLATION 110
SILICIDATION 111 LIGHTLY DOPED DRAIN (LDD) TRANSISTORS 112
EXTENDED-DRAIN, HIGH-VOLTAGE TRANSISTORS 113 3.3 ANALOG BICMOS 114
3.3.1. ESSENTIAL FEATURES 115 3.3.2. FABRICATION SEQUENCE 116 STARTING
MATERIAL 116 N-BURIED LAYER 116
EPITAXIAL GROWTH 117 N-WELL DIFFUSION AND DEEP-N+ 117 BASE IMPLANT 118
INVERSE MOAT 118
CHANNEL STOP IMPLANTS 119 LOCOS PROCESSING AND DUMMY GATE OXIDATION 119
THRESHOLD ADJUST 119 POLYSILICON DEPOSITION AND PATTERN 120 SOURCE/DRAIN
IMPLANTS 120 METALLIZATION AND PROTECTIVE OVERCOAT 120 PROCESS
COMPARISON 121 3.3.3. AVAILABLE DEVICES 121
NPN TRANSISTORS 121 PNP TRANSISTORS 123 RESISTORS 125 3.3.4. PROCESS
EXTENSIONS 125 ADVANCED METAL SYSTEMS 126 DIELECTRIC ISOLATION 126 3.4
SUMMARY 130
3.5 EXERCISES 131
4 FAILURE MECHANISMS 133 4.1 ELECTRICAL OVERSTRESS 133 4.1.1.
ELECTROSTATIC DISCHARGE (ESD) 134 EFFECTS 135
PREVENTATIVE MEASURES 135 4.1.2. ELECTROMIGRATION 136 EFFECTS 136
PREVENTATIVE MEASURES 137
IMAGE 5
X CONTENTS
4.1.3. DIELECTRIC BREAKDOWN 138 EFFECTS 138 PREVENTATIVE MEASURES 139
4.1.4. THE ANTENNA EFFECT 141
EFFECTS 141 PREVENTATIVE MEASURES 142 4.2 CONTAMINATION 143
4.2.1. DRY CORROSION 144 EFFECTS 144 PREVENTATIVE MEASURES 145 4.2.2.
MOBILE ION CONTAMINATION 145
EFFECTS 145 PREVENTATIVE MEASURES 146 4.3 SURFACE EFFECTS 148
4.3.1. HOT CARRIER INJECTION 148 EFFECTS 148 PREVENTATIVE MEASURES 150
4.3.2. ZENERWALKOUT 151
EFFECTS 151 PREVENTATIVE MEASURES 152 4.3.3. AVALANCHE-INDUCED BETA
DEGRADATION 153 EFFECTS 153
PREVENTATIVE MEASURES 154 4.3.4. NEGATIVE BIAS TEMPERATURE INSTABILITY
154 EFFECTS 155
PREVENTATIVE MEASURES 155 4.3.5. PARASITIC CHANNELS AND CHARGE SPREADING
156 EFFECTS 156
PREVENTATIVE MEASURES (STANDARD BIPOLAR) 159 PREVENTATIVE MEASURES (CMOS
AND BICMOS) 162 4.4 PARASITICS 164
4.4.1. SUBSTRATE DEBIASING 165 EFFECTS 166 PREVENTATIVE MEASURES 167
4.4.2. MINORITY-CARRIER INJECTION 169
EFFECTS 169 PREVENTATIVE MEASURES (SUBSTRATE INJECTION) 172 PREVENTATIVE
MEASURES (CROSS-INJECTION) 178 4.4.3. SUBSTRATE INFLUENCE 180
EFFECTS 180 PREVENTATIVE MEASURES 180 4.5 SUMMARY 183
4.6 EXERCISES 183
5 RESISTORS 185
5.1 RESISTIVITY AND SHEET RESISTANCE 185 5.2 RESISTOR LAYOUT 187
5.3 RESISTOR VARIABILITY 191 5.3.1. PROCESS VARIATION 191 5.3.2.
TEMPERATURE VARIATION 192
IMAGE 6
CONTENTS XI
5.3.3. NONLINEARITY 193 5.3.4. CONTACT RESISTANCE 196 5.4 RESISTOR
PARASITICS 197
5.5 COMPARISONOF AVAILABLE RESISTORS 200 5.5.1. BASE RESISTORS 200
5.5.2. EMITTER RESISTORS 201 5.5.3. BASE PINCH RESISTORS 202 5.5.4.
HIGH-SHEET RESISTORS 202 5.5.5. EPI PINCH RESISTORS 205 5.5.6. METAL
RESISTORS 206 5.5.7. POLY RESISTORS 208 5.5.8. NSD AND PSD RESISTORS 211
5.5.9. N-WELL RESISTORS 211 5.5.10. THIN-FILM RESISTORS 212 5.6
ADJUSTING RESISTOR VALUES 213
5.6.1. TWEAKING RESISTORS 213 SLIDING CONTACTS 214 SLIDING HEADS 215
TROMBONE SUEDES 215 METAL OPTIONS 215 5.6.2. TRIMMING RESISTORS 216
FUSES 216 ZENER ZAPS 219 EPROMTRIMS 221 LASER TRIMS 222
5.7 SUMMARY 223
5.8 EXERCISES 224
6 CAPACITORS AND INDUCTORS 226 6.1 CAPACITANCE 226
6.1.1. CAPACITORVARIABILITY 232 PROCESS VARIATION 232 VOLTAGE MODULATION
AND TEMPERATURE VARIATION 233 6.1.2. CAPACITOR PARASITICS 235 6.1.3.
COMPARISONOF AVAILABLE CAPACITORS 237
BASE-EMITTER JUNCTION CAPACITORS 237 MOS CAPACITORS 239 POLY-POLY
CAPACITORS 241 STACK CAPACITORS 243
LATERAL FLUX CAPACITORS 245 HIGH-PERMITTIVITY CAPACITORS 246 6.2
INDUCTANCE 246
6.2.1. INDUCTOR PARASITICS 248 6.2.2. INDUCTOR CONSTRUCTION 250
GUIDELINES FOR INTEGRATING INDUCTORS 251 6.3 SUMMARY 252
6.4 EXERCISES 253
7 MATCHING OF RESISTORS AND CAPACITORS 254 7.1 MEASURING MISMATCH 254
IMAGE 7
CONTENTS
7.2 CAUSES OF MISMATCH 257
7.2.1. RANDOM VARIATION 257 CAPACITORS 258 RESISTORS 258 7.2.2. PROCESS
BIASES 260 7.2.3. INTERCONNECTION PARASITICS 261 7.2.4. PATTERN SHIFT
263 7.2.5. ETCH RATE VARIATIONS 265 7.2.6. PHOTOLITHOGRAPHIC EFFECTS 267
7.2.7. DIFFUSION INTERACTIONS 268 7.2.8. HYDROGENATION 270 7.2.9.
MECHANICAL STRESS AND PACKAGE SHIFT 271 7.2.10. STRESS GRADIENTS 274
PIEZORESISTIVITY 274 GRADIENTS AND CENTROIDS 275 COMMON-CENTROID LAYOUT
277 LOCATION AND ORIENTATION 281 7.2.11. TEMPERATURE GRADIENTS AND
THERMOELECTRICS 283
THERMAL GRADIENTS 285 THERMOELECTRIC EFFECTS 287 7.2.12. ELECTROSTATIC
INTERACTIONS 288 VOLTAGE MODULATION 288
CHARGE SPREADING 292 DIELECTRIC POLARIZATION 293 DIELECTRIC RELAXATION
294 7.3 RULES FOR DEVICE MATCHING 295
7.3.1. RULES FOR RESISTOR MATCHING 296 7.3.2. RULES FOR CAPACITOR
MATCHING 300 7.4 SUMMARY 303
7.5 EXERCISES 304
BIPOLAR TRANSISTORS 306 8.1 TOPICS IN BIPOLAR TRANSISTOR OPERATION 306
8.1.1. BETA ROLLOFF 308 8.1.2. AVALANCHE BREAKDOWN 308
8.1.3. THERMAL RUNAWAY AND SECONDARY BREAKDOWN 310 8.1.4. SATURATION IN
NPN TRANSISTORS 312 8.1.5. SATURATION IN LATERAL PNP TRANSISTORS 315
8.1.6. PARASITICS OF BIPOLAR TRANSISTORS 318 8.2 STANDARD BIPOLAR
SMALL-SIGNAL TRANSISTORS 320
8.2.1. THE STANDARD BIPOLAR NPN TRANSISTOR 320 CONSTRUCTION OF
SMALL-SIGNAL NPN TRANSISTORS 322 8.2.2. THE STANDARD BIPOLAR SUBSTRATE
PNP TRANSISTOR 326 CONSTRUCTION OF SMALL-SIGNAL SUBSTRATE PNP
TRANSISTORS 328 8.2.3. THE STANDARD BIPOLAR LATERAL PNP TRANSISTOR 330
CONSTRUCTION OF SMALL-SIGNAL LATERAL PNP TRANSISTORS 332 8.2.4.
HIGH-VOLTAGE BIPOLAR TRANSISTORS 337 8.2.5. SUPER-BETA NPN TRANSISTORS
340 8.3 CMOS AND BICMOS SMALL-SIGNAL BIPOLAR TRANSISTORS 341
8.3.1. CMOS PNP TRANSISTORS 341 8.3.2. SHALLOW-WELL TRANSISTORS 345
IMAGE 8
CONTENTS XUEI
8.3.3. ANALOG BICMOS BIPOLAR TRANSISTORS 347 8.3.4. FAST BIPOLAR
TRANSISTORS 349 8.3.5. POLYSILICON-EMITTER TRANSISTORS 351 8.3.6.
OXIDE-ISOLATED TRANSISTORS 354 8.3.7. SILICON-GERMANIUM TRANSISTORS 356
8.4 SUMMARY 358
8.5 EXERCISES 358
9 APPLICATIONS OF BIPOLAR TRANSISTORS 360 9.1 POWER BIPOLAR TRANSISTORS
361 9.1.1. FAILURE MECHANISMS OF NPN POWER TRANSISTORS 362 EMITTER
DEBIASING 362
THERMAL RUNAWAY AND SECONDARY BREAKDOWN 364 KIRK EFFECT 366 9.1.2.
LAYOUT OF POWER NPN TRANSISTORS 368 THE INTERDIGITATED-EMITTER
TRANSISTOR 369
THE WIDE-EMITTER NARROW-CONTACT TRANSISTOR 371 THE CHRISTMAS-TREE DEVICE
372 THE CRUCIFORM-EMITTER TRANSISTOR 373 POWER TRANSISTOR LAYOUT IN
ANALOG BICMOS 374 SELECTING A POWER TRANSISTOR LAYOUT 376 9.1.3. POWER
PNP TRANSISTORS 376 9.1.4. SATURATION DETECTION AND LIMITING 378 9.2
MATCHING BIPOLAR TRANSISTORS 381
9.2.1. RANDOM VARIATIONS 382 9.2.2. EMITTER DEGENERATION 384 9.2.3.
NBLSHADOW 386 9.2.4. THERMAL GRADIENTS 387 9.2.5. STRESS GRADIENTS 391
9.2.6. FILLER-INDUCED STRESS 393 9.2.7. OTHER CAUSES OF SYSTOMATIC
MISMATCH 395 9.3 RULES FOR BIPOLAR TRANSISTOR MATCHING 396
9.3.1. RULES FOR MATCHING VERTICAL TRANSISTORS 397 9.3.2. RULES FOR
MATCHING LATERAL TRANSISTORS 402 9.4 SUMMARY 402
9.5 EXERCISES 403
10 DIODES 406
10.1 DIODES IN STANDARD BIPOLAR 406 U 10.1.1. DIODE-CONNECTED
TRANSISTORS 406
10.1.2. ZENER DIODES 409 SURFACE ZENER DIODES 410 BURIED ZENERS 412
10.1.3. SCHOTTKY DIODES 415
10.1.4. POWER DIODES 420 10.2 DIODES IN CMOS AND BICMOS PROCESSES 422
10.2.1. CMOS JUNCTION DIODES 422
10.2.2. CMOS AND BICMOS SCHOTTKY DIODES 423 10.3 MATCHING DIODES 425
10.3.1. MATCHING PN JUNCTION DIODES 425
IMAGE 9
XIV CONTENTS
10.3.2. MATCHINGZENERDIODES 426 * ; ;
10.3.3. MATCHING SCHOTTKY DIODES 428 10.4 SUMMARY 428 10.5 EXERCISES 429
1 I FIELD-EFFECT TRANSISTORS 430 11.1 TOPICS IN MOS TRANSISTOR OPERATION
431 11.1.1. MODELING THE MOS TRANSISTOR 431 DEVICE TRANSCONDUCTANCE 432
THRESHOLD VOLTAGE 434 11.1.2. PARASITICS OF MOS TRANSISTORS 438
BREAKDOWN MECHANISMS 440 CMOS LATCHUP 442
LEAKAGE MECHANISMS 443 11.2 CONSTRUCTING CMOS TRANSISTORS 446 11.2.1.
CODING THE MOS TRANSISTOR 447 WIDTH AND LENGTH 448
11.2.2. N-WELL AND P-WELL PROCESSES 449 11.2.3. CHANNEL STOP IMPLANTS
452 11.2.4. THRESHOLD ADJUST IMPLANTS 453 11.2.5. SCALING THE TRANSISTOR
456 11.2.6. VARIANT STRUCTURES 459
SERPENTINE TRANSISTORS 461 ANNULAR TRANSISTORS 462 11.2.7. BACKGATE
CONTACTS 464 11.3 FLOATING-GATE TRANSISTORS 467
11.3.1. PRINCIPLES OF FLOATING-GATE TRANSISTOR OPERATION 469 11.3.2.
SINGLE-POLY EEPROM MEMORY 472 11.4 THE JFET TRANSISTOR 474 11.4.1.
MODELING THE JFET 474
11.4.2. JFET LAYOUT 476 11.5 SUMMARY 479 11.6 EXERCISES 479
12 APPLICATIONS OFMOS TRANSISTORS 482 12.1 EXTENDED-VOLTAGE TRANSISTORS
482 12.1.1. LDD AND DDD TRANSISTORS 483 12.1.2. EXTENDED-DRAIN
TRANSISTORS 486
EXTENDED-DRAIN NMOS TRANSISTORS 487 EXTENDED-DRAIN PMOS TRANSISTORS 488
12.1.3. MULTIPLE GATE OXIDES 489 12.2 POWER MOS TRANSISTORS 491 12.2.1.
MOS SAFE OPERATING AREA 492 ELECTRICAL SOA 493 ELECTROTHERMAL SOA 496
RAPID TRANSIENT OVERLOAD 497 12.2.2. CONVENTIONAL MOS POWER TRANSISTORS
498
THE RECTANGULAR DEVICE 499 THE DIAGONAL DEVICE 500 COMPUTATION OFR M 501
IMAGE 10
CONTENTS XV
OTHER CONSIDERATIONS 502 NONCONVENTIONAL STRUCTURES 503 12.2.3. DMOS
TRANSISTORS 505 THE LATERAL DMOS TRANSISTOR 506
RESURF TRANSISTORS 508 THE DMOS NPN 510 12.3 MOS TRANSISTOR MATCHING 511
12.3.1. GEOMETRIE EFFECTS 513
GATE AREA 513 GATE OXIDE THICKNESS 514 CHANNEL LENGTH MODULATION 515
ORIENTATION 515 12.3.2. DIFFUSION AND ETCH EFFECTS 516 POLYSILICON ETCH
RATE VARIATIONS 516 DIFFUSION PENETRATION OF POLYSILICON 517
CONTACTS OVER ACTIVE GATE 518 DIFFUSIONS NEAR THE CHANNEL 518 PMOS
VERSUS NMOS TRANSISTORS 519 12.3.3. HYDROGENATION 520
FILL METAL AND MOS MATCHING 521 12.3.4. THERMAL AND STRESS EFFECTS 521
OXIDE THICKNESS GRADIENTS 522 STRESS GRADIENTS 522
THERMAL GRADIENTS 522 12.3.5. COMMON-CENTROID LAYOUT OF MOS TRANSISTORS
523 12.4 RULES FOR MOS TRANSISTOR MATCHING 528 12.5 SUMMARY 531
12.6 EXERCISES 531
13 SPECIAL TOPICS 534 13.1 MERGED DEVICES 534 13.1.1. FLAWED DEVICE
MERGERS 535 13.1.2. SUCCESSFUL DEVICE MERGERS 539
13.1.3. LOW-RISK MERGED DEVICES 541 13.1.4. MEDIUM-RISK MERGED DEVICES
542 13.1.5. DEVISING NEW MERGED DEVICES 544 13.1.6. THE ROLE OF MERGED
DEVICES IN ANALOG BICMOS 544 13.2 GUARD RINGS 545
13.2.1. STANDARD BIPOLAR ELECTRON GUARD RINGS 546 13.2.2. STANDARD
BIPOLAR HOLE GUARD RINGS 547 13.2.3. GUARD RINGS IN CMOS AND BICMOS
DESIGNS 548 13.3 SINGLE-LEVEL INTERCONNECTION 551
13.3.1. MOCK LAYOUTS AND STICK DIAGRAMS 551 13.3.2. TECHNIQUES FOR
CROSSING LEADS 553 13.3.3. TYPESOFTUNNELS 555 13.4 CONSTRUCTING THE
PADRING 557 13.4.1. SCRIBE STREETS AND ALIGNMENT MARKERS 557 13.4.2.
BONDPADS, TRIMPADS, AND TESTPADS 558 13.5 ESD STRUCTURES 562 13.5.1.
ZENERCLAMP 563 13.5.2. TWO-STAGE ZENER CLAMPS 565
IMAGE 11
XVI CONTENTS
13.5.3. BUFFERED ZENER CLAMP 566 13.5.4. V CES CLAMP 568 13.5.5. V ECS
CLAMP 569 13.5.6. ANTIPARALLEL DIODE CLAMPS 570
13.5.7. GROUNDED-GATE NMOS CLAMPS 570 13.5.8. CDM CLAMPS 572 13.5.9.
LATERAL SCR CLAMPS 573 13.5.10. SELECTING ESD STRUCTURES 575 13.6
EXERCISES 578
14 ASSEMBLING THE DIE 581 14.1 DIEPLANNING 581
14.1.1. CELL AREA ESTIMATION 582 RESISTORS 582 CAPACITORS 582 VERTICAL
BIPOLAR TRANSISTORS 583 LATERAL PNP TRANSISTORS 583 MOS TRANSISTORS 583
MOS POWER TRANSISTORS 584
COMPUTING CELL AREA 584 14.1.2. DIE AREA ESTIMATION 584 14.1.3. GROSS
PROFIT MARGIN 587 14.2 FLOORPLANNING 588
14.3 TOP-LEVEL INTERCONNECTION 594 14.3.1. PRINCIPLES OF CHANNEL ROUTING
594 14.3.2. SPECIAL ROUTING TECHNIQUES 596 KELVIN CONNECTIONS 597
NOISY SIGNALS AND SENSITIVE SIGNALS 598 14.3.3. ELECTROMIGRATION 600
14.3.4. MINIMIZING STRESS EFFECTS 603 14.4 CONCLUSION 604 14.5 EXERCISES
605
APPENDICES A. TABLE OF ACRONYMS USED IN THE TEXT 607 B. THE MILLER
INDICES OF A CUBIC CRYSTAL 611 C. SAMPLE LAYOUT RULES 614
D. MATHEMATICAL DERIVATIONS 622 E. SOURCES FOR LAYOUT EDITOR SOFTWARE
627
INDEX 628
|
| any_adam_object | 1 |
| author | Hastings, Alan |
| author_facet | Hastings, Alan |
| author_role | aut |
| author_sort | Hastings, Alan |
| author_variant | a h ah |
| building | Verbundindex |
| bvnumber | BV023804511 |
| classification_rvk | ZN 4904 |
| ctrlnum | (OCoLC)254457958 (DE-599)BVBBV023804511 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. ed., Internat. ed. |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01496nam a2200397zc 4500</leader><controlfield tag="001">BV023804511</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20090426000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">081119s2006 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">013129329X</subfield><subfield code="9">0-13-129329-X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)254457958</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV023804511</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4904</subfield><subfield code="0">(DE-625)157419:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Hastings, Alan</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">The art of analog layout</subfield><subfield code="c">Alan Hastings</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">2. ed., Internat. ed.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Upper Saddle River, NJ</subfield><subfield code="b">Prentice Hall</subfield><subfield code="c">2006</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXI, 648 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Layout</subfield><subfield code="g">Mikroelektronik</subfield><subfield code="0">(DE-588)4264372-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Layout</subfield><subfield code="g">Mikroelektronik</subfield><subfield code="0">(DE-588)4264372-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017446687&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-017446687</subfield></datafield></record></collection> |
| id | DE-604.BV023804511 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:37:11Z |
| institution | BVB |
| isbn | 013129329X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017446687 |
| oclc_num | 254457958 |
| open_access_boolean | |
| owner | DE-634 |
| owner_facet | DE-634 |
| physical | XXI, 648 S. graph. Darst. |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Prentice Hall |
| record_format | marc |
| spelling | Hastings, Alan Verfasser aut The art of analog layout Alan Hastings 2. ed., Internat. ed. Upper Saddle River, NJ Prentice Hall 2006 XXI, 648 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Layout Mikroelektronik (DE-588)4264372-7 s GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017446687&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Hastings, Alan The art of analog layout Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4264372-7 (DE-588)4179389-4 |
| title | The art of analog layout |
| title_auth | The art of analog layout |
| title_exact_search | The art of analog layout |
| title_full | The art of analog layout Alan Hastings |
| title_fullStr | The art of analog layout Alan Hastings |
| title_full_unstemmed | The art of analog layout Alan Hastings |
| title_short | The art of analog layout |
| title_sort | the art of analog layout |
| topic | Integrierte Schaltung (DE-588)4027242-4 gnd Layout Mikroelektronik (DE-588)4264372-7 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Integrierte Schaltung Layout Mikroelektronik Schaltungsentwurf |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017446687&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT hastingsalan theartofanaloglayout |