Statistical analysis and optimization for VLSI: timing and power
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Springer
2005
|
| Schlagworte: | |
| Beschreibung: | IX, 279 S. graph. Darst. |
| ISBN: | 0387257381 |
Internformat
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Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Srivastava, Ashish |
| author_facet | Srivastava, Ashish |
| author_role | aut |
| author_sort | Srivastava, Ashish |
| author_variant | a s as |
| building | Verbundindex |
| bvnumber | BV023801866 |
| ctrlnum | (OCoLC)254901053 (DE-599)BVBBV023801866 |
| dewey-full | 621.395 510 |
| dewey-hundreds | 600 - Technology (Applied sciences) 500 - Natural sciences and mathematics |
| dewey-ones | 621 - Applied physics 510 - Mathematics |
| dewey-raw | 621.395 510 |
| dewey-search | 621.395 510 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations 510 - Mathematics |
| discipline | Mathematik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV023801866 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:37:07Z |
| institution | BVB |
| isbn | 0387257381 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017444065 |
| oclc_num | 254901053 |
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| physical | IX, 279 S. graph. Darst. |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | Springer |
| record_format | marc |
| spelling | Srivastava, Ashish Verfasser aut Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw New York, NY Springer 2005 IX, 279 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s CAD (DE-588)4069794-0 s DE-604 Sylvester, Dennis Sonstige oth Blaauw, David T. Sonstige oth |
| spellingShingle | Srivastava, Ashish Statistical analysis and optimization for VLSI timing and power VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4069794-0 (DE-588)4312536-0 |
| title | Statistical analysis and optimization for VLSI timing and power |
| title_auth | Statistical analysis and optimization for VLSI timing and power |
| title_exact_search | Statistical analysis and optimization for VLSI timing and power |
| title_full | Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw |
| title_fullStr | Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw |
| title_full_unstemmed | Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw |
| title_short | Statistical analysis and optimization for VLSI |
| title_sort | statistical analysis and optimization for vlsi timing and power |
| title_sub | timing and power |
| topic | VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | VLSI CAD Entwurfsautomation |
| work_keys_str_mv | AT srivastavaashish statisticalanalysisandoptimizationforvlsitimingandpower AT sylvesterdennis statisticalanalysisandoptimizationforvlsitimingandpower AT blaauwdavidt statisticalanalysisandoptimizationforvlsitimingandpower |