Rapid system prototyping with FPGAs: [accelerating the design process]
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam [u.a.]
Elsevier
2006
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| Schriftenreihe: | Embedded technology series
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XV, 301 S. Ill., graph. Darst. |
| ISBN: | 0750678666 |
Internformat
MARC
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| 245 | 1 | 0 | |a Rapid system prototyping with FPGAs |b [accelerating the design process] |c by R. C. Cofer and Benjamin F. Harding |
| 264 | 1 | |a Amsterdam [u.a.] |b Elsevier |c 2006 | |
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Datensatz im Suchindex
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| adam_text | RAPID SYSTEM PROTOTYPING WITH FPGAS BY R.C. COFERAND BENJAMIN F. HARDING
AMSTERDAM * BOSTON * HEIDELBERG * LONDON NEW YORK * OXFORD * PARIS * SAN
DIEGO SAN FRANCISCO * SINGAPORE * SYDNEY * TOKYO NEWNES IS AN IMPRINT OF
ELSEVIER NEWNES % CONTENTS CHAPTER 1: INTRODUCTION 1 1.1 FPGA RAPID
DESIGN IMPLEMENTATION POTENTIAL 2 1.2 RAPIDLY EVOLVING TECHNOLOGY FIELD
4 1.3 DESIGN SKILL SET CROSSOVER 4 1.4 HARDWARE KNOWLEDGE FOR
SOFTWARE/FIRMWARE DESIGNERS 6 1.5 SOFTWARE KNOWLEDGE FOR HARDWARE
DESIGNERS 7 1.6 WHEN FPGA TECHNOLOGY MAY NOT BE AN IDEAL FIT 8 1.7 WHEN
FPGAS TECHNOLOGY MAY BE APPROPRIATE 9 1.8 SUMMARY 11 CHAPTER 2: FPGA
FUNDAMENTALS 13 2.1 OVERVIEW 13 2.1.1 CATEGORIES OF PROGRAMMABLE LOGIC
13 2.1.2 SPLD DEVICE OVERVIEW 16 2.1.3 CPLD DEVICE OVERVIEW 17 2.1.4
FPGA DEVICE OVERVIEW 20 2.1.5 FPGATYPES 22 2.2 SRAM-BASED FPGA
ARCHITECTURE 24 2.2.1 FPGA LOGIC BLOCK STRUCTURE 25 2.2.2 FPGA ROUTING
MATRIX AND GLOBAL SIGNALS 27 2.2.3 FPGA I/O BLOCKS 28 2.2.4 FPGA CLOCK
RESOURCES 30 2.2.5 FPGA MEMORY 32 2.3 ADVANCED FPGA FEATURES 32 2.4
SUMMARY 33 VII CONTENTS CHAPTER 3: OPTIMIZING THE DEVELOPMENT CYCLE 35
3.1 OVERVIEW 35 3.2 FPGA DESIGN FLOW 36 3.2.1 REQUIREMENTS PHASE 41
3.2.2 ARCHITECTURE AND DESIGN PHASE 42 3.2.3 IMPLEMENTATION PHASE 46
3.2.4 VERIFLCATION PHASE 48 3.3 SUMMARY 49 CHAPTER 4: SYSTEM ENGINEERING
51 4.1 OVERVIEW 51 4.2 COMMON DESIGN CHALLENGES AND MISTAKES 52 4.3
DEFINED FPGA DESIGN PROCESS 53 4-4 PROJECT ENGINEERING AND MANAGEMENT 55
4.4.1 TEAM COMMUNICATION 56 4-4.2 DESIGN REVIEWS 57 4-4.3 BUDGETS AND
SCHEDULING 59 4.5 TRAINING 61 4.6 SUPPORT 63 4.7 DESIGN CONFIGURATION
MANAGEMENT 64 4-7.1 CONTROLLING THE FPGA DESIGN IN THE LAB 67 4-7.2
ARCHIVING THE DESIGN ...68 4.8 SUMMARY 70 CHAPTER 5: FPCA DEVICE-LEVEL
DESIGN DECISIONS 71 5.1 OVERVIEW 71 5.2 FPGA SELECTION CATEGORIES 72
5.2.1 FPGA MANUFACTURER SELECTION 72 5.2.2 FAMILY SELECTION 73 5.2.3
DEVICE SELECTION 74 5.2.4 PACKAGE SELECTION 77 5.3 DESIGN DECISIONS 78
5.3.1 DATA FLOW THROUGH THE FPGA 78 5.3.2 INFORMED I/O PIN ASSIGNMENTS
79 5.4 DEVICE SELECTION CHECKLIST 83 5.5 SUMMARY 85 VIII CONTENTS
CHAPTER 6: BOARD-LEVEL DESIGN DECISIONS AND ALLOCATION 87 6.1 OVERVIEW
87 6.2 PACKAGING 88 6.3 BGA COMPONENT CONSIDERATIONS 90 6.3.1 BGA SIGNAL
BREAKOUT 90 6.3.2 MOUNTING AND REWORKING BGA COMPONENTS 92 6.3.3 BGA I/O
TO SIGNAL ASSIGNMENT 93 6.3.4 BGA TRACE SIGNAL ACCESS 94 6.4 I/O
ASSIGNMENT ITERATION 95 6.5 FPGA DEVICE SCHEMATIC SYMBOL GENERATION 96
6.6 THERMAL 96 6.7 BOARD LAYOUT 97 6.7.1 DEVICE PLACEMENT AND
ORIENTATION 98 6.7.2 HEADERS AND INTERNAL SIGNAL ACCESS (TEST AND
CONFIGURATION CABLE)98 6.8 SIGNAL INTEGRITY 99 6.8.1 SIGNAL PROTOCOL
CHOICES AND IMPLEMENTATION 99 6.9 POWER 100 6.9.1 DEVICE DECOUPLING
CONSIDERATIONS 100 6.10 SUMMARY 102 CHAPTER 7: DESIGN IMPLEMENTATION 103
7.1 OVERVIEW 103 7.2 DESIGN ARCHITECTURE 104 7.2.1 SYNCHRONOUS DESIGN
105 7.2.2 HIERARCHICAL VERSUS FIAT DESIGN 106 7.2.3 IMPLEMENTING A
HIERARCHICAL DESIGN 108 7.3 DESIGN ENTRY 109 7.3.1 DUALNATURE OF HDL
LANGUAGES 111 7.3.2 HDL CODING GUIDANCE 111 7.3.3 TOOLS 114 7.4 RTL 115
7.5 SYNTHESIS 118 7.5.1 LOGICAL SYNTHESIS 118 7.5.2 PHYSICAL SYNTHESIS
120 7.5.3 PREPARING A DESIGN FOR SYNTHESIS 120 7.5.4 DESIGN INFERENCE
VERSUS INSTANTIATION 122 IX CONTENTS 7.6 PLACE AND ROUTE 122 7.7 SUMMARY
124 CHAPTER 8: DESIGN SIMULATION 727 8.1 OVERVIEW 127 8.2 STAGES OF
SIMULATION 128 8.3 TYPES OF SIMULATION FILES 129 8.4 HOW MUCH
SIMULATION? 131 8.5 HIERARCHICAL DESIGN AND SIMULATION 132 8.6 COMMON
SIMULATION MISTAKES AND TIPS 132 8.7 SUMMARY 135 CHAPTER 9: DESIGN
CONSTRAINTS AND OPTIMIZATION 137 9.1 OVERVIEW 137 9.2 DESIGN CONSTRAINT
MANAGEMENT 137 9.2.1 AVOIDING DESIGN OVER-CONSTRAINT 138 9.2.2 SYNTHESIS
CONSTRAINTS 138 9.2.3 PIN CONSTRAINTS 140 9.2.4 TIMING CONSTRAINTS 144
9.2.5 AREA CONSTRAINTS AND FLOORPLANNING 146 9.2.6 CONSTRAINT EXAMPLE
147 9.2.7 CONSTRAINTS CHECKLIST 149 9.3 DESIGN OPTIMIZATION 149 9.3.1
FPGA DESIGN OPTIMIZATION PROCESS 150 9.4 SUMMARY 153 CHAPTER 10:
CONFIGURATION 755 10.1 OVERVIEW 155 10.2 ON-BOARD DEVICE CONFIGURATION
156 10.3 CONFIGURATION CABLE INTERFACE 156 10.4 JTAG STANDARD 158 10.4.1
UNDERSTANDING PIN OPERATIONAL STATES 159 10.5 DESIGN SECURITY 160 10.6
SUMMARY 161 CHAPTER 11: BOARD-LEVEL TESTING 163 11.1 OVERVIEW 163 11.1.1
FPGA DESIGN VALIDATION APPROACHES 164 11.1.2 ACCESS TO CRITICAL INTERNAL
SIGNALS 164 X CONTENTS 11.1.3 BOUNDARY SCAN SUPPORT 11.2 DESIGN DEBUG
CHECKLIST 11.3 SUMMARY CHAPTER 12: ADVANCED TOPICS INTRODUCTION. 12.1
OVERVIEW 12.2 REDUCED POWER CONSUMPTION 12.3 VOLUME PRODUCTION OPTIONS
12.4 SUMMARY CHAPTER 13: CORES AND INTELLECTUAL PROPERTY.. 13.1 OVERVIEW
13.2 TYPESOFLP 13.3 CATEGORIES OF IP 13.4 TRADE STUDIES 13.5 MAKE VERSUS
BUY? 13.5.1 SOURCESOFLP 13.5.2 EVALUATING IP OPTIONS 13.5.3 QUALIFYING
AN IP VENDOR.... 13.5.4 LICENSING ISSUES 13.6 IP IMPLEMENTATION/TOOLS
13.7 IP TESTING/DEBUG 13.8 SUMMARY CHAPTER 14: EMBEDDED PROCESSING
CORES. 14.1 OVERVIEW 14.2 FPGA EMBEDDED PROCESSOR TYPES 14.3 FPGA
PROCESSOR USE CONSIDERATIONS 14-4 SYSTEM DESIGN CONSIDERATIONS 14.4.1
CO-DESIGN 14-4.2 PROCESSOR ARCHITECTURE 14.4.3 PROCESSOR IMPLEMENTATION
OPTIONS 14.4.4 PROCESSOR CORE AND PERIPHERAL SELECTION 14.4.5 HARDWARE
IMPLEMENTATION FACTORS 14.4.6 SOFTWARE IMPLEMENTATION FACTORS 14-5 FPGA
EMBEDDED PROCESSOR CONCEPT EXAMPLE.... 14.6 FPGA EMBEDDED PROCESSOR
DESIGN CHECKLIST 14.7 SUMMARY 165 166 166 167 167 168 168 169 171 171
173 175 175 176 178 178 179 181 182 182 183 185 185 186 188 190 190 192
195 196 198 199 201 208 209 CONTENTS CHAPTER 15: DIGITAL SIGNAL
PROCESSING 211 15.1 OVERVIEW 211 15.2 BASIC DSP SYSTEM 212 15.3
ESSENTIAL DSP TERMS 213 15.4 ARCHITECTURES 215 15.5 PARALLEL EXECUTION
IN DSP COMPONENTS 216 15.6 PARALLEL EXECUTION IN FPGA 217 15.7 WHEN TO
USE FPGAS FOR DSP 219 15.8 FPGA DSP DESIGN CONSIDERATIONS 220 15.8.1
CLOCKING AND SIGNAL ROUTING 220 15.8.2 PIPELINING 221 15.8.3 ALGORITHM
IMPLEMENTATION CHOICES 221 15.8.4 DSP INTELLECTUAL PROPERTY (IP) 222
15.9 FIR FILTER CONCEPT EXAMPLE 222 15.10 SUMMARY 224 CHAPTER 16:
ADVANCED INTERCONNECT 227 16.1 OVERVIEW 227 16.2 INTERCONNECTION
CATEGORIES 227 16.3 ADVANCED I/O INTERFACE CHALLENGES 230 16.4
IMPLEMENTING AN ADVANCED PARALLEL I/O INTERFACE 231 16.5 IMPLEMENTING AN
ADVANCED SERIAL I/O INTERFACE ...233 16.6 SUMMARY 236 CHAPTER 17:
BRINGING IT ALL TOGETHER 237 17.1 SYSTEM OVERVIEW 237 17.2 REQUIREMENTS
PHASE 238 17.3 ARCHITECTURAL PHASE 240 17.4 IMPLEMENTATION PHASE 243
17.5 VERIFICATION PHASE 245 17.6 PROTOTYPE DELIVERY 247 17.7 SUMMARY 247
APPENDIX A: RAPID SYSTEM PROTOTYPING TECHNICAL REFERENCES 249 APPENDIX
B: DESIGN PHASES 271 ABBREVIATIONS AND ACRONYMS 287 INDEX 295 XII
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| institution | BVB |
| isbn | 0750678666 |
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| physical | XV, 301 S. Ill., graph. Darst. |
| publishDate | 2006 |
| publishDateSearch | 2006 |
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| publisher | Elsevier |
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| spelling | Cofer, R. C. Verfasser aut Rapid system prototyping with FPGAs [accelerating the design process] by R. C. Cofer and Benjamin F. Harding Amsterdam [u.a.] Elsevier 2006 XV, 301 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Embedded technology series Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Rapid Prototyping Fertigung (DE-588)4389159-7 gnd rswk-swf Rapid Prototyping Fertigung (DE-588)4389159-7 s Field programmable gate array (DE-588)4347749-5 s DE-604 Harding, Benjamin F. Verfasser aut GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017439575&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Cofer, R. C. Harding, Benjamin F. Rapid system prototyping with FPGAs [accelerating the design process] Field programmable gate array (DE-588)4347749-5 gnd Rapid Prototyping Fertigung (DE-588)4389159-7 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4389159-7 |
| title | Rapid system prototyping with FPGAs [accelerating the design process] |
| title_auth | Rapid system prototyping with FPGAs [accelerating the design process] |
| title_exact_search | Rapid system prototyping with FPGAs [accelerating the design process] |
| title_full | Rapid system prototyping with FPGAs [accelerating the design process] by R. C. Cofer and Benjamin F. Harding |
| title_fullStr | Rapid system prototyping with FPGAs [accelerating the design process] by R. C. Cofer and Benjamin F. Harding |
| title_full_unstemmed | Rapid system prototyping with FPGAs [accelerating the design process] by R. C. Cofer and Benjamin F. Harding |
| title_short | Rapid system prototyping with FPGAs |
| title_sort | rapid system prototyping with fpgas accelerating the design process |
| title_sub | [accelerating the design process] |
| topic | Field programmable gate array (DE-588)4347749-5 gnd Rapid Prototyping Fertigung (DE-588)4389159-7 gnd |
| topic_facet | Field programmable gate array Rapid Prototyping Fertigung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017439575&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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