Fundamentals of computer organization and design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York [u.a.]
Springer
2003
|
| Schriftenreihe: | Texts in computer science
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturverz. S. 1033 - 1035 |
| Beschreibung: | XXVIII, 1060 S. graph. Darst. 24 cm |
| ISBN: | 038795211X |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV023528792 | ||
| 003 | DE-604 | ||
| 005 | 20140604 | ||
| 007 | t | ||
| 008 | 030625s2003 xxud||| |||| 00||| eng d | ||
| 015 | |a 03,A14,1063 |2 dnb | ||
| 016 | 7 | |a 966496663 |2 DE-101 | |
| 020 | |a 038795211X |c Pp. : EUR 85.55 |9 0-387-95211-X | ||
| 035 | |a (OCoLC)610821225 | ||
| 035 | |a (DE-599)BVBBV023528792 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 044 | |a xxu |c XD-US | ||
| 049 | |a DE-521 |a DE-634 |a DE-83 | ||
| 050 | 0 | |a TK7885.D283 2003 | |
| 082 | 0 | |a 621.39/1 21 | |
| 084 | |a ST 110 |0 (DE-625)143583: |2 rvk | ||
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a 37 |2 sdnb | ||
| 084 | |a 28 |2 sdnb | ||
| 100 | 1 | |a Dandamudi, Sivarama P. |d 1955- |e Verfasser |0 (DE-588)12076010X |4 aut | |
| 245 | 1 | 0 | |a Fundamentals of computer organization and design |c Sivarama P. Dandamudi |
| 264 | 1 | |a New York [u.a.] |b Springer |c 2003 | |
| 300 | |a XXVIII, 1060 S. |b graph. Darst. |c 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Texts in computer science | |
| 500 | |a Literaturverz. S. 1033 - 1035 | ||
| 650 | 4 | |a Computer engineering | |
| 650 | 4 | |a Computer organization | |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Hardwareentwurf |0 (DE-588)4159103-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Prozessor |0 (DE-588)4176076-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Softwareentwicklung |0 (DE-588)4116522-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Leistungsbewertung |0 (DE-588)4167271-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Rechnerorganisation |0 (DE-588)4177175-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a RISC |0 (DE-588)4191875-7 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Rechnerorganisation |0 (DE-588)4177175-8 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Rechnerorganisation |0 (DE-588)4177175-8 |D s |
| 689 | 1 | 1 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
| 689 | 1 | 2 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a RISC |0 (DE-588)4191875-7 |D s |
| 689 | 2 | |5 DE-604 | |
| 689 | 3 | 0 | |a Rechnerorganisation |0 (DE-588)4177175-8 |D s |
| 689 | 3 | 1 | |a Prozessor |0 (DE-588)4176076-1 |D s |
| 689 | 3 | 2 | |a Softwareentwicklung |0 (DE-588)4116522-6 |D s |
| 689 | 3 | 3 | |a Hardwareentwurf |0 (DE-588)4159103-3 |D s |
| 689 | 3 | 4 | |a Leistungsbewertung |0 (DE-588)4167271-9 |D s |
| 689 | 3 | |5 DE-604 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016848992&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-016848992 | |
Datensatz im Suchindex
| _version_ | 1808044927602393088 |
|---|---|
| adam_text |
CONTENTS
PREFACE
VII
PART
I:
OVERVIEW
1
1
OVERVIEW
OF
COMPUTER
ORGANIZATION
3
1.1
INTRODUCTION
.
4
1.1.1
BASIC
TERMS
AND
NOTATION
.
6
1.2
PROGRAMMER
'
S
VIEW
.
7
1.2.1
ADVANTAGES
OF
HIGH-LEVEL
LANGUAGES
.
10
1.2.2
WHY
PROGRAM
IN
ASSEMBLY
LANGUAGE?
.
11
1.3
ARCHITECT
'
S
VIEW
.
12
1.4
IMPLEMENTER
'
S
VIEW
.
14
1.5
THE
PROCESSOR
.
16
1.5.1
PIPELINING
.
18
1.5.2
RISC
AND
CISC
DESIGNS
.
19
1.6
MEMORY
.
22
1.6.1
BASIC
MEMORY
OPERATIONS
.
23
1.6.2
BYTE
ORDERING
.
24
1.6.3
TWO
IMPORTANT
MEMORY
DESIGN
ISSUES
.
24
1.7
INPUT/OUTPUT
.
27
1.8
INTERCONNECTION:
THE
GLUE
.
30
1.9
HISTORICAL
PERSPECTIVE
.
31
1.9.1
THE
EARLY
GENERATIONS
.
31
1.9.2
VACUUM
TUBE
GENERATION:
AROUND
THE
1940S
AND
1950S
.
31
1.9.3
TRANSISTOR
GENERATION:
AROUND
THE
1950S
AND
1960S
.
32
1.9.4
IC
GENERATION:
AROUND
THE
1960S
AND
1970S
.
32
1.9.5
VLSI
GENERATIONS:
SINCE
THE
MID-1970S
.
32
1.10
TECHNOLOGICAL
ADVANCES
.
33
1.11
SUMMARY
AND
OUTLINE
.
35
1.12
EXERCISES
.
36
XIV
CONTENTS
PART
II:
DIGITAL
LOGIC
DESIGN
39
2
DIGITAL
LOGIC
BASICS
41
2.1
INTRODUCTION
.
42
2.2
BASIC
CONCEPTS
AND
BUILDING
BLOCKS
.
42
2.2.1
SIMPLE
GATES
.
42
2.2.2
COMPLETENESS
AND
UNIVERSALITY
.
44
2.2.3
IMPLEMENTATION
DETAILS
.
46
2.3
LOGIC
FUNCTIONS
.
49
2.3.1
EXPRESSING
LOGIC
FUNCTIONS
.
49
2.3.2
LOGICAL
CIRCUIT
EQUIVALENCE
.
52
2.4
BOOLEAN
ALGEBRA
.
54
2.4.1
BOOLEAN
IDENTITIES
.
54
2.4.2
USING
BOOLEAN
ALGEBRA
FOR
LOGICAL
EQUIVALENCE
.
54
2.5
LOGIC
CIRCUIT
DESIGN
PROCESS
.
55
2.6
DERIVING
LOGICAL
EXPRESSIONS
FROM
TRUTH
TABLES
.
56
2.6.1
SUM-OF-PRODUCTS
FORM
.
56
2.6.2
PRODUCT-OF-SUMS
FORM
.
57
2.6.3
BRUTE
FORCE
METHOD
OF
IMPLEMENTATION
.
58
2.7
SIMPLIFYING
LOGICAL
EXPRESSIONS
.
58
2.7.1
ALGEBRAIC
MANIPULATION
.
58
2.7.2
KARNAUGH
MAP
METHOD
.
60
2.7.3
QUINE-MCCLUSKEY
METHOD
.
67
2.8
GENERALIZED
GATES
.
71
2.9
MULTIPLE
OUTPUTS
.
73
2.10
IMPLEMENTATION
USING
OTHER
GATES
.
75
2.10.1
IMPLEMENTATION
USING
NAND
AND
NOR
GATES
.
75
2.10.2
IMPLEMENTATION
USING
XOR
GATES
.
77
2.11
SUMMARY
.
78
2.12
WEB
RESOURCES
.
79
2.13
EXERCISES
.
79
3
COMBINATIONAL
CIRCUITS
83
3.1
INTRODUCTION
.
83
3.2
MULTIPLEXERS
AND
DEMULTIPLEXERS
.
84
3.2.1
IMPLEMENTATION:
A
MULTIPLEXER
CHIP
.
86
3.2.2
EFFICIENT
MULTIPLEXER
DESIGNS
.
86
3.2.3
IMPLEMENTATION:
A
4-TO-L
MULTIPLEXER
CHIP
.
87
3.2.4
DEMULTIPLEXERS
.
89
3.3
DECODERS
AND
ENCODERS
.
89
3.3.1
DECODER
CHIPS
.
90
3.3.2
ENCODERS
.
92
CONTENTS
XV
3.4
COMPARATORS
.
94
3.4.1
A
COMPARATOR
CHIP
.
94
3.5
ADDERS
.
95
3.5.1
AN
EXAMPLE
ADDER
CHIP
.
98
3.6
PROGRAMMABLE
LOGIC
DEVICES
.
98
3.6.1
PROGRAMMABLE
LOGIC
ARRAYS
(PLAS)
.
98
3.6.2
PROGRAMMABLE
ARRAY
LOGIC
DEVICES
(PALS)
.
100
3.7
ARITHMETIC
AND
LOGIC
UNITS
.
103
3.7.1
AN
EXAMPLE
ALU
CHIP
.
105
3.8
SUMMARY
.
105
3.9
EXERCISES
.
107
4
SEQUENTIAL
LOGIC
CIRCUITS
109
4.1
INTRODUCTION
.
109
4.2
CLOCK
SIGNAL
.
ILL
4.3
LATCHES
.
113
4.3.1
SR
LATCH
.
114
4.3.2
CLOCKED
SR
LATCH
.
115
4.3.3
D
LATCH
.
115
4.4
FLIP-FLOPS
.
116
4.4.1
D
FLIP-FLOPS
.
116
4.4.2
JK
FLIP-FLOPS
.
117
4.4.3
EXAMPLE
CHIPS
.
119
4.5
EXAMPLE
SEQUENTIAL
CIRCUITS
.
120
4.5.1
SHIFT
REGISTERS
.
120
4.5.2
COUNTERS
.
121
4.6
SEQUENTIAL
CIRCUIT
DESIGN
.
127
4.6.1
BINARY
COUNTER
DESIGN
WITH
JK
FLIP-FLOPS
.
127
4.6.2
GENERAL
DESIGN
PROCESS
.
132
4.7
SUMMARY
.
140
4.8
EXERCISES
.
143
PART
III:
INTERCONNECTION
145
5
SYSTEM
BUSES
147
5.1
INTRODUCTION
.
147
5.2
BUS
DESIGN
ISSUES
.
150
5.2.1
BUS
WIDTH
.
150
5.2.2
BUS
TYPE
.
152
5.2.3
BUS
OPERATIONS
.
152
5.3
SYNCHRONOUS
BUS
.
153
5.3.1
BASIC
OPERATION
.
153
XVI
CONTENTS
5.3.2
WAIT
STATES
.
154
5.3.3
BLOCK
TRANSFER
.
155
5.4
ASYNCHRONOUS
BUS
.
157
5.5
BUS
ARBITRATION
.
159
5.5.1
DYNAMIC
BUS
ARBITRATION
.
159
5.5.2
IMPLEMENTATION
OF
DYNAMIC
ARBITRATION
.
161
5.6
EXAMPLE
BUSES
.
165
5.6.1
THE
ISA
BUS
.
166
5.6.2
THE
PCI
BUS
.
168
5.6.3
ACCELERATED
GRAPHICS
PORT
(AGP)
.
180
5.6.4
THEPCI-XBUS
.
182
5.6.5
THE
PCMCIA
BUS
.
185
5.7
SUMMARY
.
190
5.8
WEB
RESOURCES
.
192
5.9
EXERCISES
.
192
PART
IV:
PROCESSORS
195
6
PROCESSOR
ORGANIZATION
AND
PERFORMANCE
197
6.1
INTRODUCTION
.
198
6.2
NUMBER
OF
ADDRESSES
.
199
6.2.1
THREE-ADDRESS
MACHINES
.
199
6.2.2
TWO-ADDRESS
MACHINES
.
200
6.2.3
ONE-ADDRESS
MACHINES
.
201
6.2.4
ZERO-ADDRESS
MACHINES
.
202
6.2.5
A
COMPARISON
.
204
6.2.6
THE
LOAD/STORE
ARCHITECTURE
.
206
6.2.7
PROCESSOR
REGISTERS
.
207
6.3
FLOW
OF
CONTROL
.
208
6.3.1
BRANCHING
.
208
6.3.2
PROCEDURE
CALLS
.
211
6.4
INSTRUCTION
SET
DESIGN
ISSUES
.
213
6.4.1
OPERAND
TYPES
.
214
6.4.2
ADDRESSING
MODES
.
215
6.4.3
INSTRUCTION
TYPES
.
216
6.4.4
INSTRUCTION
FORMATS
.
218
6.5
MICROPROGRAMMED
CONTROL
.
219
6.5.1
HARDWARE
IMPLEMENTATION
.
225
6.5.2
SOFTWARE
IMPLEMENTATION
.
226
6.6
PERFORMANCE
.
236
6.6.1
PERFORMANCE
METRICS
.
237
6.6.2
EXECUTION
TIME
CALCULATION
.
238
CONTENTS
XVII
6.6.3
MEANS
OF
PERFORMANCE
.
238
6.6.4
THE
SPEC
BENCHMARKS
.
241
6.7
SUMMARY
.
246
6.8
EXERCISES
.
247
7
THE
PENTIUM
PROCESSOR
251
7.1
THE
PENTIUM
PROCESSOR
FAMILY
.
251
7.2
THE
PENTIUM
PROCESSOR
.
253
7.3
THE
PENTIUM
REGISTERS
.
256
7.3.1
DATA
REGISTERS
.
256
7.3.2
POINTER
AND
INDEX
REGISTERS
.
257
7.3.3
CONTROL
REGISTERS
.
257
7.3.4
SEGMENT
REGISTERS
.
259
7.4
REAL
MODE
MEMORY
ARCHITECTURE
.
260
7.5
PROTECTED
MODE
MEMORY
ARCHITECTURE
.
265
7.5.1
SEGMENT
REGISTERS
.
265
7.5.2
SEGMENT
DESCRIPTORS
.
266
7.5.3
SEGMENT
DESCRIPTOR
TABLES
.
268
7.5.4
SEGMENTATION
MODELS
.
269
7.5.5
MIXED-MODE
OPERATION
.
270
7.5.6
WHICH
SEGMENT
REGISTER
TO
USE
.
270
7.6
SUMMARY
.
270
7.7
EXERCISES
.
271
8
PIPELINING
AND
VECTOR
PROCESSING
273
8.1
BASIC
CONCEPTS
.
274
8.2
HANDLING
RESOURCE
CONFLICTS
.
277
8.3
DATA
HAZARDS
.
278
8.3.1
REGISTER
FORWARDING
.
279
8.3.2
REGISTER
INTERLOCKING
.
280
8.4
HANDLING
BRANCHES
.
282
8.4.1
DELAYED
BRANCH
EXECUTION
.
283
8.4.2
BRANCH
PREDICTION
.
283
8.5
PERFORMANCE
ENHANCEMENTS
.
286
8.5.1
SUPERSCALAR
PROCESSORS
.
287
8.5.2
SUPERPIPELINED
PROCESSORS
.
288
8.5.3
VERY
LONG
INSTRUCTION
WORD
ARCHITECTURES
.
290
8.6
EXAMPLE
IMPLEMENTATIONS
.
291
8.6.1
PENTIUM
.
291
8.6.2
POWERPC
.
294
8.6.3
SPARC
PROCESSOR
.
297
8.6.4
MIPS
PROCESSOR
.
299
XVIII
CONTENTS
8.7
VECTOR
PROCESSORS
.
299
8.7.1
WHAT
IS
VECTOR
PROCESSING?
.
300
8.7.2
ARCHITECTURE
.
301
8.7.3
ADVANTAGES
OF
VECTOR
PROCESSING
.
303
8.7.4
THE
CRAY
X-MP
.
304
8.7.5
VECTOR
LENGTH
.
306
8.7.6
VECTOR
STRIDE
.
308
8.7.7
VECTOR
OPERATIONS
ON
THE
CRAY
X-MP
.
309
8.7.8
CHAINING
.
311
8.8
PERFORMANCE
.
312
8.8.1
PIPELINE
PERFORMANCE
.
312
8.8.2
VECTOR
PROCESSING
PERFORMANCE
.
314
8.9
SUMMARY
.
315
8.10
EXERCISES
.
317
PART
V:
PENTIUM
ASSEMBLY
LANGUAGE
319
9
OVERVIEW
OF
ASSEMBLY
LANGUAGE
321
9.1
INTRODUCTION
.
322
9.2
ASSEMBLY
LANGUAGE
STATEMENTS
.
322
9.3
DATA
ALLOCATION
.
324
9.3.1
RANGE
OF
NUMERIC
OPERANDS
.
326
9.3.2
MULTIPLE
DEFINITIONS
.
327
9.3.3
MULTIPLE
INITIALIZATIONS
.
329
9.3.4
CORRESPONDENCE
TO
C
DATA
TYPES
.
330
9.3.5
LABEL
DIRECTIVE
.
331
9.4
WHERE
ARE
THE
OPERANDS?
.
332
9.4.1
REGISTER ADDRESSING
MODE
.
332
9.4.2
IMMEDIATE
ADDRESSING
MODE
.
333
9.4.3
DIRECT ADDRESSING
MODE
.
334
9.4.4
INDIRECT ADDRESSING
MODE
.
335
9.5
DATA
TRANSFER
INSTRUCTIONS
.
338
9.5.1
THE
MOV
INSTRUCTION
.
338
9.5.2
THE
XCHG
INSTRUCTION
.
339
9.5.3
THE
XLAT
INSTRUCTION
.
340
9.6
PENTIUM
ASSEMBLY
LANGUAGE
INSTRUCTIONS
.
340
9.6.1
ARITHMETIC
INSTRUCTIONS
.
340
9.6.2
CONDITIONAL
EXECUTION
.
345
9.6.3
ITERATION
INSTRUCTIONS
.
352
9.6.4
LOGICAL
INSTRUCTIONS
.
354
9.6.5
SHIFT
INSTRUCTIONS
.
357
9.6.6
ROTATE
INSTRUCTIONS
.
361
CONTENTS
XIX
9.7
DEFINING
CONSTANTS
.
364
9.7.1
THE
EQU
DIRECTIVE
.
364
9.7.2
THE
=
DIRECTIVE
.
366
9.8
MACROS
.
366
9.9
ILLUSTRATIVE
EXAMPLES
.
368
9.10
SUMMARY
.
379
9.11
EXERCISES
.
380
9.12
PROGRAMMING
EXERCISES
.
383
10
PROCEDURES
AND
THE
STACK
387
10.1
WHAT
IS
A
STACK?
.
388
10.2
PENTIUM
IMPLEMENTATION
OF
THE
STACK
.
388
10.3
STACK
OPERATIONS
.
390
10.3.1
BASIC
INSTRUCTIONS
.
390
10.3.2
ADDITIONAL
INSTRUCTIONS
.
391
10.4
USES
OF
THE
STACK
.
393
10.4.1
TEMPORARY
STORAGE
OF
DATA
.
393
10.4.2
TRANSFER
OF
CONTROL
.
394
10.4.3
PARAMETER
PASSING
.
394
10.5
PROCEDURES
.
394
10.6
ASSEMBLER
DIRECTIVES
FOR
PROCEDURES
.
396
10.7
PENTIUM
INSTRUCTIONS
FOR
PROCEDURES
.
397
10.7.1
HOW
IS
PROGRAM
CONTROL
TRANSFERRED?
.
397
10.7.2
THE
RET
INSTRUCTION
.
398
10.8
PARAMETER
PASSING
.
399
10.8.1
REGISTER
METHOD
.
399
10.8.2
STACK
METHOD
.
402
10.8.3
PRESERVING
CALLING
PROCEDURE
STATE
.
406
10.8.4
WHICH
REGISTERS
SHOULD
BE
SAVED?
.
406
10.8.5
ILLUSTRATIVE
EXAMPLES
.
409
10.9
HANDLING
A
VARIABLE
NUMBER
OF
PARAMETERS
.
417
10.10
LOCAL
VARIABLES
.
420
10.11
MULTIPLE
SOURCE
PROGRAM
MODULES
.
426
10.11.1
PUBLIC
DIRECTIVE
.
427
10.11.2
EXTRN
DIRECTIVE
.
427
10.12
SUMMARY
.
430
10.13
EXERCISES
.
431
10.14
PROGRAMMING
EXERCISES
.
433
11
ADDRESSING
MODES
435
11.1
INTRODUCTION
.
435
XX
CONTENTS
11.2
MEMORY
ADDRESSING
MODES
.
437
11.2.1
BASED
ADDRESSING
.
439
11.2.2
INDEXED
ADDRESSING
.
439
11.2.3
BASED-INDEXED
ADDRESSING
.
441
11.3
ILLUSTRATIVE
EXAMPLES
.
441
11.4
ARRAYS
.
448
11.4.1
ONE-DIMENSIONAL
ARRAYS
.
449
11.4.2
MULTIDIMENSIONAL
ARRAYS
.
450
11.4.3
EXAMPLES
OF
ARRAYS
.
452
11.5
RECURSION
.
455
11.5.1
ILLUSTRATIVE
EXAMPLES
.
456
11.6
SUMMARY
.
464
11.7
EXERCISES
.
464
11.8
PROGRAMMING
EXERCISES
.
465
12
SELECTED
PENTIUM
INSTRUCTIONS
471
12.1
STATUS
FLAGS
.
472
12.1.1
THE
ZERO
FLAG
.
472
12.1.2
THE
CARRY
FLAG
.
474
12.1.3
THE
OVERFLOW
FLAG
.
477
12.1.4
THE
SIGN
FLAG
.
479
12.1.5
THE
AUXILIARY
FLAG
.
480
12.1.6
THE
PARITY
FLAG
.
481
12.1.7
FLAG
EXAMPLES
.
483
12.2
ARITHMETIC
INSTRUCTIONS
.
484
12.2.1
MULTIPLICATION
INSTRUCTIONS
.
485
12.2.2
DIVISION
INSTRUCTIONS
.
488
12.2.3
APPLICATION
EXAMPLES
.
491
12.3
CONDITIONAL
EXECUTION
.
497
12.3.1
INDIRECT
JUMPS
.
497
12.3.2
CONDITIONAL
JUMPS
.
500
12.4
IMPLEMENTING
HIGH-LEVEL
LANGUAGE
DECISION
STRUCTURES
.
504
12.4.1
SELECTIVE
STRUCTURES
.
504
12.4.2
ITERATIVE
STRUCTURES
.
508
12.5
LOGICAL
EXPRESSIONS
IN
HIGH-LEVEL
LANGUAGES
.
510
12.5.1
REPRESENTATION
OF
BOOLEAN
DATA
.
510
12.5.2
LOGICAL
EXPRESSIONS
.
511
12.5.3
BIT
MANIPULATION
.
511
12.5.4
EVALUATION
OF
LOGICAL
EXPRESSIONS
.
511
12.6
BIT
INSTRUCTIONS
.
515
12.6.1
BIT
TEST
AND
MODIFY
INSTRUCTIONS
.
515
12.6.2
BIT
SCAN
INSTRUCTIONS
.
516
CONTENTS
XXI
12.7
ILLUSTRATIVE
EXAMPLES
.
516
12.8
STRING
INSTRUCTIONS
.
526
12.8.1
STRING
REPRESENTATION
.
526
12.8.2
STRING
INSTRUCTIONS
.
527
12.8.3
STRING
PROCESSING
EXAMPLES
.
536
12.8.4
TESTING
STRING
PROCEDURES
.
540
12.9
SUMMARY
.
542
12.10
EXERCISES
.
543
12.11
PROGRAMMING
EXERCISES
.
545
13
HIGH-LEVEL
LANGUAGE
INTERFACE
551
13.1
WHY
PROGRAM
IN
MIXED-MODE?
.
552
13.2
OVERVIEW
.
552
13.3
CALLING
ASSEMBLY
PROCEDURES
FROM
C
.
554
13.3.1
PARAMETER
PASSING
.
554
13.3.2
RETURNING
VALUES
.
556
13.3.3
PRESERVING
REGISTERS
.
556
13.3.4
PUBLICS
AND
EXTERNALS
.
557
13.3.5
ILLUSTRATIVE
EXAMPLES
.
557
13.4
CALLING
C
FUNCTIONS
FROM
ASSEMBLY
.
562
13.5
INLINE
ASSEMBLY
CODE
.
565
13.5.1
COMPILING
INLINE
ASSEMBLY
PROGRAMS
.
565
13.6
SUMMARY
.
566
13.7
EXERCISES
.
567
13.8
PROGRAMMING
EXERCISES
.
567
PART
VI:
RISC
PROCESSORS
569
14
RISC
PROCESSORS
571
14.1
INTRODUCTION
.
572
14.2
EVOLUTION
OF
CISC
PROCESSORS
.
572
14.3
RISC
DESIGN
PRINCIPLES
.
575
14.3.1
SIMPLE
OPERATIONS
.
575
14.3.2
REGISTER-TO-REGISTER
OPERATIONS
.
576
14.3.3
SIMPLE
ADDRESSING
MODES
.
576
14.3.4
LARGE
NUMBER
OF
REGISTERS
.
576
14.3.5
FIXED-LENGTH,
SIMPLE
INSTRUCTION
FORMAT
.
577
14.4
POWERPC
PROCESSOR
.
578
14.4.1
ARCHITECTURE
.
578
14.4.2
POWERPC
INSTRUCTION
SET
.
581
14.5
ITANIUM
PROCESSOR
.
590
14.5.1
ARCHITECTURE
.
591
XXII
CONTENTS
14.5.2
ITANIUM
INSTRUCTION
SET
.
594
14.5.3
HANDLING
BRANCHES
.
604
14.5.4
PREDICATION
TO
ELIMINATE
BRANCHES
.
605
14.5.5
SPECULATIVE
EXECUTION
.
606
14.5.6
BRANCH
PREDICTION
.
610
14.6
SUMMARY
.
611
14.7
EXERCISES
.
612
15
MIPS
ASSEMBLY
LANGUAGE
615
15.1
MIPS
PROCESSOR
ARCHITECTURE
.
616
15.1.1
REGISTERS
.
616
15.1.2
GENERAL-PURPOSE
REGISTER
USAGE
CONVENTION
.
617
15.1.3
ADDRESSING
MODES
.
618
15.1.4
MEMORY
USAGE
.
619
15.2
MIPS
INSTRUCTION
SET
.
619
15.2.1
INSTRUCTION
FORMAT
.
620
15.2.2
DATA TRANSFER
INSTRUCTIONS
.
621
15.2.3
ARITHMETIC
INSTRUCTIONS
.
623
15.2.4
LOGICAL
INSTRUCTIONS
.
627
15.2.5
SHIFT
INSTRUCTIONS
.
627
15.2.6
ROTATE
INSTRUCTIONS
.
628
15.2.7
COMPARISON
INSTRUCTIONS
.
628
15.2.8
BRANCH
AND
JUMP
INSTRUCTIONS
.
630
15.3
SPIM
SYSTEM
CALLS
.
632
15.4
SPIM
ASSEMBLER
DIRECTIVES
.
634
15.5
ILLUSTRATIVE
EXAMPLES
.
636
15.6
PROCEDURES
.
643
15.7
STACK
IMPLEMENTATION
.
648
15.7.1
ILLUSTRATIVE
EXAMPLES
.
649
15.8
SUMMARY
.
657
15.9
EXERCISES
.
658
15.10
PROGRAMMING
EXERCISES
.
659
PART
VII:
MEMORY
663
16
MEMORY
SYSTEM
DESIGN
665
16.1
INTRODUCTION
.
666
16.2
A
SIMPLE
MEMORY
BLOCK
.
666
16.2.1
MEMORY
DESIGN
WITH
D
FLIP-FLOPS
.
667
16.2.2
PROBLEMS
WITH
THE
DESIGN
.
667
16.3
TECHNIQUES
TO
CONNECT
TO
A
BUS
.
669
16.3.1
USING
MULTIPLEXERS
.
669
CONTENTS
XXIII
16.3.2
USING
OPEN
COLLECTOR
OUTPUTS
.
669
16.3.3
USING
TRISTATE
BUFFERS
.
671
16.4
BUILDING
A
MEMORY
BLOCK
.
673
16.5
BUILDING
LARGER
MEMORIES
.
674
16.5.1
DESIGNING
INDEPENDENT
MEMORY
MODULES
.
676
16.5.2
DESIGNING
LARGER
MEMORIES
USING
MEMORY
CHIPS
.
678
16.6
MAPPING
MEMORY
.
681
16.6.1
FULL
MAPPING
.
681
16.6.2
PARTIAL
MAPPING
.
682
16.7
ALIGNMENT
OF
DATA
.
683
16.8
INTERLEAVED
MEMORIES
.
684
16.8.1
THE
CONCEPT
.
685
16.8.2
SYNCHRONIZED
ACCESS
ORGANIZATION
.
686
16.8.3
INDEPENDENT
ACCESS
ORGANIZATION
.
687
16.8.4
NUMBER
OF
BANKS
.
688
16.8.5
DRAWBACKS
.
689
16.9
SUMMARY
.
689
16.10
EXERCISES
.
690
17
CACHE
MEMORY
693
17.1
INTRODUCTION
.
694
17.2
HOW
CACHE
MEMORY
WORKS
.
695
17.3
WHY
CACHE
MEMORY
WORKS
.
697
17.4
CACHE
DESIGN
BASICS
.
699
17.5
MAPPING
FUNCTION
.
700
17.5.1
DIRECT
MAPPING
.
703
17.5.2
ASSOCIATIVE
MAPPING
.
707
17.5.3
SET-ASSOCIATIVE
MAPPING
.
708
17.6
REPLACEMENT
POLICIES
.
711
17.7
WRITE
POLICIES
.
713
17.8
SPACE
OVERHEAD
.
715
17.9
MAPPING
EXAMPLES
.
717
17.10
TYPES
OF
CACHE
MISSES
.
718
17.11
TYPES
OF
CACHES
.
719
17.11.1
SEPARATE
INSTRUCTION
AND
DATA
CACHES
.
719
17.11.2
NUMBER
OF
CACHE
LEVELS
.
720
17.11.3
VIRTUAL
AND
PHYSICAL
CACHES
.
722
17.12
EXAMPLE
IMPLEMENTATIONS
.
722
17.12.1
PENTIUM
.
722
17.12.2
POWERPC
.
724
17.12.3
MIPS
.
726
XXIV
CONTENTS
17.13
CACHE
OPERATION:
A
SUMMARY
.
727
17.13.1
PLACEMENT
OF
A
BLOCK
.
727
17.13.2
LOCATION
OF
A
BLOCK
.
728
17.13.3
REPLACEMENT
POLICY
.
728
17.13.4
WRITE
POLICY
.
728
17.14
DESIGN
ISSUES
.
729
17.14.1
CACHE
CAPACITY
.
729
17.14.2
CACHE
LINE
SIZE
.
729
17.14.3
DEGREE
OF
ASSOCIATIVITY
.
731
17.15
SUMMARY
.
731
17.16
EXERCISES
.
733
18
VIRTUAL
MEMORY
735
18.1
INTRODUCTION
.
736
18.2
VIRTUAL
MEMORY
CONCEPTS
.
737
18.2.1
PAGE
REPLACEMENT
POLICIES
.
738
18.2.2
WRITE
POLICY
.
739
18.2.3
PAGE
SIZE
TRADEOFF
.
740
18.2.4
PAGE
MAPPING
.
741
18.3
PAGE
TABLE
ORGANIZATION
.
741
18.3.1
PAGE
TABLE
ENTRIES
.
742
18.4
THE
TRANSLATION
LOOKASIDE
BUFFER
.
743
18.5
PAGE
TABLE
PLACEMENT
.
744
18.5.1
SEARCHING
HIERARCHICAL
PAGE
TABLES
.
745
18.6
INVERTED
PAGE
TABLE
ORGANIZATION
.
746
18.7
SEGMENTATION
.
748
18.8
EXAMPLE
IMPLEMENTATIONS
.
750
18.8.1
PENTIUM
.
750
18.8.2
POWERPC
.
754
18.8.3
MIPS
.
756
18.9
SUMMARY
.
760
18.10
EXERCISES
.
761
PART
VIII:
INPUT
AND
OUTPUT
765
19
INPUT/OUTPUT
ORGANIZATION
767
19.1
INTRODUCTION
.
768
19.2
ACCESSING
I/O
DEVICES
.
770
19.2.1
I/O
ADDRESS
MAPPING
.
770
19.2.2
ACCESSING
I/O
PORTS
.
770
19.3
AN
EXAMPLE
I/O
DEVICE:
KEYBOARD
.
772
19.3.1
KEYBOARD
DESCRIPTION
.
772
19.3.2
8255
PROGRAMMABLE
PERIPHERAL
INTERFACE
CHIP
.
772
CONTENTS
XXV
19.4
I/O
DATA
TRANSFER
.
774
19.4.1
PROGRAMMED
I/O
.
775
19.4.2
DMA
.
777
19.5
ERROR
DETECTION
AND
CORRECTION
.
784
19.5.1
PARITY
ENCODING
.
784
19.5.2
ERROR
CORRECTION
.
785
19.5.3
CYCLIC
REDUNDANCY
CHECK
.
787
19.6
EXTERNAL
INTERFACE
.
791
19.6.1
SERIAL
TRANSMISSION
.
794
19.6.2
PARALLEL
INTERFACE
.
797
19.7
UNIVERSAL
SERIAL
BUS
.
801
19.7.1
MOTIVATION
.
801
19.7.2
ADDITIONAL
USB
ADVANTAGES
.
802
19.7.3
USB
ENCODING
.
803
19.7.4
TRANSFER
TYPES
.
803
19.7.5
USB
ARCHITECTURE
.
805
19.7.6
USB
TRANSACTIONS
.
807
19.8
IEEE
1394
.
810
19.8.1
ADVANTAGESOF
IEEE
1394
.
810
19.8.2
POWER
DISTRIBUTION
.
811
19.8.3
TRANSFER
TYPES
.
812
19.8.4
TRANSACTIONS
.
813
19.8.5
BUS
ARBITRATION
.
815
19.8.6
CONFIGURATION
.
815
19.9
THE
BUS
WARS
.
820
19.10
SUMMARY
.
821
19.11
WEB
RESOURCES
.
823
19.12
EXERCISES
.
823
20
INTERRUPTS
825
20.1
INTRODUCTION
.
826
20.2
A
TAXONOMY
OF
PENTIUM
INTERRUPTS
.
827
20.3
PENTIUM
INTERRUPT
PROCESSING
.
829
20.3.1
INTERRUPT
PROCESSING
IN
PROTECTED
MODE
.
829
20.3.2
INTERRUPT
PROCESSING
IN
REAL
MODE
.
829
20.4
PENTIUM
SOFTWARE
INTERRUPTS
.
831
20.4.1
DOS
KEYBOARD
SERVICES
.
832
20.4.2
BIOS
KEYBOARD
SERVICES
.
837
20.5
PENTIUM
EXCEPTIONS
.
842
20.6
PENTIUM
HARDWARE
INTERRUPTS
.
847
20.6.1
HOW
DOES
THE
CPU
KNOW
THE
INTERRUPT
TYPE?
.
847
20.6.2
HOW
CAN
MORE
THAN
ONE
DEVICE
INTERRUPT?
.
848
XXVI
CONTENTS
20.6.3
8259
PROGRAMMABLE
INTERRUPT
CONTROLLER
.
848
20.6.4
A
PENTIUM
HARDWARE
INTERRUPT
EXAMPLE
.
850
20.7
INTERRUPT PROCESSING
IN
THE
POWERPC
.
855
20.8
INTERRUPT
PROCESSING
IN
THE
MIPS
.
857
20.9
SUMMARY
.
859
20.10
EXERCISES
.
860
20.11
PROGRAMMING
EXERCISES
.
862
APPENDICES
863
A
COMPUTER ARITHMETIC
865
A.L
POSITIONAL
NUMBER
SYSTEMS
.
865
A.
1.1
NOTATION
.
867
A.2
NUMBER
SYSTEMS
CONVERSION
.
868
A.
2.1
CONVERSION
TO
DECIMAL
.
868
A.
2.2
CONVERSION
FROM
DECIMAL
.
870
A.
2.3
CONVERSION
AMONG
BINARY,
OCTAL,
AND
HEXADECIMAL
.
871
A.
3
UNSIGNED
INTEGER
REPRESENTATION
.
874
A.
3.1
ARITHMETIC
ON
UNSIGNED
INTEGERS
.
875
A.4
SIGNED
INTEGER
REPRESENTATION
.
881
A.4.
1
SIGNED
MAGNITUDE
REPRESENTATION
.
882
A.4.2
EXCESS-M
REPRESENTATION
.
882
A.4.
3
1
'
S
COMPLEMENT
REPRESENTATION
.
883
A.4.4
2
'
S
COMPLEMENT
REPRESENTATION
.
886
A.
5
FLOATING-POINT
REPRESENTATION
.
887
A.
5.1
FRACTIONS
.
887
A.
5.2
REPRESENTING
FLOATING-POINT
NUMBERS
.
890
A.
5.3
FLOATING-POINT
REPRESENTATION
.
891
A.
5.4
FLOATING-POINT
ADDITION
.
896
A.
5.5
FLOATING-POINT
MULTIPLICATION
.
896
A.
6
SUMMARY
.
897
A.
7
EXERCISES
.
898
A.8
PROGRAMMING
EXERCISES
.
900
B
CHARACTER
REPRESENTATION
901
B.L
CHARACTER
SETS
.
901
B.2
UNIVERSAL
CHARACTER
SET
.
903
B.3
UNICODE
.
903
B.4
SUMMARY
.
904
C
ASSEMBLING
AND
LINKING
PENTIUM
ASSEMBLY
LANGUAGE
PROGRAMS
907
C.
1
STRUCTURE
OF
ASSEMBLY
LANGUAGE
PROGRAMS
.
908
CONTENTS
XXVII
C.2
INPUT/OUTPUT
ROUTINES
.
910
C.2.1
CHARACTER
I/O
.
912
C.2.
2
STRING
I/O
.
912
C.2.
3
NUMERIC
I/O
.
913
C.3
ASSEMBLING
AND
LINKING
.
915
C.3.1
THE
ASSEMBLY
PROCESS
.
915
C.3.
2
LINKING
OBJECT
FILES
.
924
C.4
SUMMARY
.
924
C.5
EXERCISES
.
925
C.6
PROGRAMMING
EXERCISES
.
925
D
DEBUGGING
ASSEMBLY
LANGUAGE
PROGRAMS
927
D.
1
STRATEGIES
TO
DEBUG
ASSEMBLY
LANGUAGE
PROGRAMS
.
928
D.2
DEBUG
.
930
D.2.1
DISPLAY
GROUP
.
930
D.2.
2
EXECUTION
GROUP
.
933
D.2.
3
MISCELLANEOUS
GROUP
.
934
D.2.4
AN
EXAMPLE
.
934
D.3
TURBO
DEBUGGER
TD
.
938
D.4
CODEVIEW
.
943
D.5
SUMMARY
.
944
D.6
EXERCISES
.
944
D.7
PROGRAMMING
EXERCISES
.
945
E
RUNNING
PENTIUM
ASSEMBLY
LANGUAGE
PROGRAMS
ON
A
LINUX
SYSTEM
947
E.
1
INTRODUCTION
.
948
E.2
NASM
ASSEMBLY
LANGUAGE
PROGRAM
TEMPLATE
.
948
E.3
ILLUSTRATIVE
EXAMPLES
.
950
E.4
SUMMARY
.
955
E.5
EXERCISES
.
955
E.6
PROGRAMMING
EXERCISES
.
955
F
DIGITAL
LOGIC
SIMULATORS
957
F.
1
TESTING
DIGITAL
LOGIC
CIRCUITS
.
957
F.2
DIGITAL
LOGIC
SIMULATORS
.
958
F.2.
1
DIGSIM
SIMULATOR
.
958
F.2.
2
DIGITAL
SIMULATOR
.
959
F.2.
3
MULTIMEDIA
LOGIC
SIMULATOR
.
961
F.2.4
LOGIKAD
SIMULATOR
.
962
F.3
SUMMARY
.
966
F.4
WEB
RESOURCES
.
966
F.5
EXERCISES
.
967
XXVIII
CONTENTS
G
SPIM
SIMULATOR
AND
DEBUGGER
969
G.L
INTRODUCTION
.
969
G.2
SIMULATOR
SETTINGS
.
972
G.3
RUNNING
AND
DEBUGGING
A
PROGRAM
.
973
G.3.1
LOADING
AND
RUNNING
.
973
G.3.
2
DEBUGGING
.
974
G.4
SUMMARY
.
977
G.5
EXERCISES
.
977
G.6
PROGRAMMING
EXERCISES
.
977
H
THE
SPARC
ARCHITECTURE
979
H.L
INTRODUCTION
.
979
H.2
REGISTERS
.
980
H.3
ADDRESSING
MODES
.
982
H.4
INSTRUCTION
SET
.
984
H.4.1
INSTRUCTION
FORMAT
.
984
H.4.2
DATA
TRANSFER
INSTRUCTIONS
.
984
H.4.3
ARITHMETIC
INSTRUCTIONS
.
986
H.4.4
LOGICAL
INSTRUCTIONS
.
987
H.4.
5
SHIFT
INSTRUCTIONS
.
988
H.4.6
COMPARE
INSTRUCTIONS
.
988
H.4.7
BRANCH
INSTRUCTIONS
.
989
H.5
PROCEDURES
AND
PARAMETER
PASSING
.
993
H.5.1
PROCEDURE
INSTRUCTIONS
.
993
H.5
.2
PARAMETER
PASSING
.
994
H.5.
3
STACK
IMPLEMENTATION
.
995
H.5.
4
WINDOW
MANAGEMENT
.
996
H.6
SUMMARY
.
1000
H.7
WEB
RESOURCES
.
1000
H.8
EXERCISES
.
1000
I
PENTIUM
INSTRUCTION
SET
1001
1.1
PENTIUM
INSTRUCTION
FORMAT
.
1001
1.
1.1
INSTRUCTION
PREFIXES
.
1001
1.1.2
GENERAL
INSTRUCTION
FORMAT
.
1002
1.2
SELECTED
PENTIUM
INSTRUCTIONS
.
1004
BIBLIOGRAPHY
1033
INDEX
1037 |
| adam_txt | |
| any_adam_object | 1 |
| any_adam_object_boolean | |
| author | Dandamudi, Sivarama P. 1955- |
| author_GND | (DE-588)12076010X |
| author_facet | Dandamudi, Sivarama P. 1955- |
| author_role | aut |
| author_sort | Dandamudi, Sivarama P. 1955- |
| author_variant | s p d sp spd |
| building | Verbundindex |
| bvnumber | BV023528792 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.D283 2003 |
| callnumber-search | TK7885.D283 2003 |
| callnumber-sort | TK 47885 D283 42003 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 110 ST 250 |
| ctrlnum | (OCoLC)610821225 (DE-599)BVBBV023528792 |
| dewey-full | 621.39/121 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/1 21 |
| dewey-search | 621.39/1 21 |
| dewey-sort | 3621.39 11 221 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000zc 4500</leader><controlfield tag="001">BV023528792</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20140604</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">030625s2003 xxud||| |||| 00||| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">03,A14,1063</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">966496663</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">038795211X</subfield><subfield code="c">Pp. : EUR 85.55</subfield><subfield code="9">0-387-95211-X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)610821225</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV023528792</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">XD-US</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-521</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7885.D283 2003</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/1 21</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 110</subfield><subfield code="0">(DE-625)143583:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">37</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">28</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dandamudi, Sivarama P.</subfield><subfield code="d">1955-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)12076010X</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Fundamentals of computer organization and design</subfield><subfield code="c">Sivarama P. Dandamudi</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXVIII, 1060 S.</subfield><subfield code="b">graph. Darst.</subfield><subfield code="c">24 cm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Texts in computer science</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Literaturverz. S. 1033 - 1035</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer organization</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hardwareentwurf</subfield><subfield code="0">(DE-588)4159103-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Prozessor</subfield><subfield code="0">(DE-588)4176076-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Softwareentwicklung</subfield><subfield code="0">(DE-588)4116522-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Leistungsbewertung</subfield><subfield code="0">(DE-588)4167271-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Rechnerorganisation</subfield><subfield code="0">(DE-588)4177175-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">RISC</subfield><subfield code="0">(DE-588)4191875-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Rechnerorganisation</subfield><subfield code="0">(DE-588)4177175-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Rechnerorganisation</subfield><subfield code="0">(DE-588)4177175-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="2"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">RISC</subfield><subfield code="0">(DE-588)4191875-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Rechnerorganisation</subfield><subfield code="0">(DE-588)4177175-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="1"><subfield code="a">Prozessor</subfield><subfield code="0">(DE-588)4176076-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="2"><subfield code="a">Softwareentwicklung</subfield><subfield code="0">(DE-588)4116522-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="3"><subfield code="a">Hardwareentwurf</subfield><subfield code="0">(DE-588)4159103-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="4"><subfield code="a">Leistungsbewertung</subfield><subfield code="0">(DE-588)4167271-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016848992&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-016848992</subfield></datafield></record></collection> |
| id | DE-604.BV023528792 |
| illustrated | Illustrated |
| index_date | 2024-07-02T22:34:37Z |
| indexdate | 2024-08-22T00:20:10Z |
| institution | BVB |
| isbn | 038795211X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016848992 |
| oclc_num | 610821225 |
| open_access_boolean | |
| owner | DE-521 DE-634 DE-83 |
| owner_facet | DE-521 DE-634 DE-83 |
| physical | XXVIII, 1060 S. graph. Darst. 24 cm |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Springer |
| record_format | marc |
| series2 | Texts in computer science |
| spelling | Dandamudi, Sivarama P. 1955- Verfasser (DE-588)12076010X aut Fundamentals of computer organization and design Sivarama P. Dandamudi New York [u.a.] Springer 2003 XXVIII, 1060 S. graph. Darst. 24 cm txt rdacontent n rdamedia nc rdacarrier Texts in computer science Literaturverz. S. 1033 - 1035 Computer engineering Computer organization Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Hardwareentwurf (DE-588)4159103-3 gnd rswk-swf Prozessor (DE-588)4176076-1 gnd rswk-swf Softwareentwicklung (DE-588)4116522-6 gnd rswk-swf Leistungsbewertung (DE-588)4167271-9 gnd rswk-swf Rechnerorganisation (DE-588)4177175-8 gnd rswk-swf RISC (DE-588)4191875-7 gnd rswk-swf Rechnerorganisation (DE-588)4177175-8 s DE-604 Logische Schaltung (DE-588)4131023-8 s Schaltungsentwurf (DE-588)4179389-4 s RISC (DE-588)4191875-7 s Prozessor (DE-588)4176076-1 s Softwareentwicklung (DE-588)4116522-6 s Hardwareentwurf (DE-588)4159103-3 s Leistungsbewertung (DE-588)4167271-9 s DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016848992&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Dandamudi, Sivarama P. 1955- Fundamentals of computer organization and design Computer engineering Computer organization Schaltungsentwurf (DE-588)4179389-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Hardwareentwurf (DE-588)4159103-3 gnd Prozessor (DE-588)4176076-1 gnd Softwareentwicklung (DE-588)4116522-6 gnd Leistungsbewertung (DE-588)4167271-9 gnd Rechnerorganisation (DE-588)4177175-8 gnd RISC (DE-588)4191875-7 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4131023-8 (DE-588)4159103-3 (DE-588)4176076-1 (DE-588)4116522-6 (DE-588)4167271-9 (DE-588)4177175-8 (DE-588)4191875-7 |
| title | Fundamentals of computer organization and design |
| title_auth | Fundamentals of computer organization and design |
| title_exact_search | Fundamentals of computer organization and design |
| title_exact_search_txtP | Fundamentals of computer organization and design |
| title_full | Fundamentals of computer organization and design Sivarama P. Dandamudi |
| title_fullStr | Fundamentals of computer organization and design Sivarama P. Dandamudi |
| title_full_unstemmed | Fundamentals of computer organization and design Sivarama P. Dandamudi |
| title_short | Fundamentals of computer organization and design |
| title_sort | fundamentals of computer organization and design |
| topic | Computer engineering Computer organization Schaltungsentwurf (DE-588)4179389-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Hardwareentwurf (DE-588)4159103-3 gnd Prozessor (DE-588)4176076-1 gnd Softwareentwicklung (DE-588)4116522-6 gnd Leistungsbewertung (DE-588)4167271-9 gnd Rechnerorganisation (DE-588)4177175-8 gnd RISC (DE-588)4191875-7 gnd |
| topic_facet | Computer engineering Computer organization Schaltungsentwurf Logische Schaltung Hardwareentwurf Prozessor Softwareentwicklung Leistungsbewertung Rechnerorganisation RISC |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016848992&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT dandamudisivaramap fundamentalsofcomputerorganizationanddesign |