Verfügbarkeit: FSM-based digital design using Verilog HDL

FSM-based digital design using Verilog HDL:

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Bibliographische Detailangaben
Hauptverfasser:	Minns, Peter (VerfasserIn), Elliott, Ian (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Chichester [u.a.] Wiley 2008
Schlagworte:	Verilog (Computer hardware description language) Digital electronics Sequential machine theory VERILOG Digitalelektronik Digitales System
Online-Zugang:	Table of contents only Publisher description Inhaltsverzeichnis
Beschreibung:	XIII, 391 S. Ill., graph. Darst. 1 CD-ROM (12 cm)
ISBN:	9780470060704 0470060700

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Datensatz im Suchindex

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adam_text	FSM-BASED DIGITAL DESIGN USING VERIIOG HDL PETER MINNS LAN ELLIOTT NORTHUMBRIA UNIVERSITY, UK JOHN WILEY & SONS, LTD CONTENTS PREFACE XI ACKNOWLEDGEMENTS XV 1 INTRODUCTION TO FINITE-STATE MACHINES AND STATE DIAGRAMS FOR THE DESIGN OF ELECTRONIC CIRCUITS AND SYSTEMS 1 1.1 INTRODUCTION 1 1.2 LEARNING MATERIAL 2 1.3 SUMMARY 21 2 USING STATE DIAGRAMS TO CONTROL EXTERNAL HARDWARE SUBSYSTEMS 23 2.1 INTRODUCTION 23 2.2 LEARNING MATERIAL 23 2.3 SUMMARY 38 3 SYNTHESIZING HARDWARE FROM A STATE DIAGRAM 39 3.1 INTRODUCTION TO FINITE-STATE MACHINE SYNTHESIS 39 3.2 LEARNING MATERIAL 40 3.3 SUMMARY 66 4 SYNCHRONOUS FINITE-STATE MACHINE DESIGNS 67 4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD 67 4.2 DEALING WITH UNUSED STATES 69 4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM 71 4.3.1 TESTING THE FINITE-STATE MACHINE USING A TEST-BENCH MODULE 75 4.4 SIMPLE WAVEFORM GENERATOR 76 4.4.1 SAMPLING FREQUENCY AND SAMPLES PER WAVEFORM 78 4.5 THE DICE GAME 79 4.5.1 DEVELOPMENT OF THE EQUATIONS FOR THE DICE GAME 81 II CONTENTS 4.6 BINARY DATA SERIAL TRANSMITTER 83 4.6.1 THE RECOUNTER BLOCK IN THE SHIFT REGISTER OFFIGURE 4.15 87 4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER 88 4.7.1 FINITE-STATE MACHINE EQUATIONS 91 4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM 92 4.8.1 TO INCORPORATE THE PARITY 92 4.8.2 OE-TYPE EQUATIONS FOR FIGURE 4.26 94 4.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM 95 4.9.1 EQUATIONS FOR THE ASYNCHRONOUS SERIAL TRANSMITTER 98 4.10 CLOCKEDWATCHDOG TIMER 100 4.10.1 D FLIP-FLOP EQUATIONS 102 4.10.2 OUTPUT EQUATION 102 4.11 SUMMARY 103 5 THE ONE HOT TECHNIQUE IN FINITE-STATE MACHINE DESIGN 105 5.1 THE ONE HOT TECHNIQUE 105 5.2 A DATA ACQUISITION SYSTEM 110 5.3 A SHARED MEMORY SYSTEM 114 5.4 FAST WAVEFORM SYNTHESIZER 116 5.4.1 SPECIFICATION 117 5.4.2 A POSSIBLE SOLUTION 118 5.4.3 EQUATIONS FOR THE D INPUTS TO D FLIP-FLOPS 119 5.4.4 OUTPUT EQUATIONS 120 5.5 CONTROLLING THE FINITE-STATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER 120 5.6 A MEMORY-CHIP TESTER 123 5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHODOFCHAPTER4 126 5.8 A DYNAMIC MEMORY ACCESS CONTROLLER 127 5.8.1 FLIP-FLOP EQUATIONS 131 5.8.2 OUTPUT EQUATIONS 131 5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR 132 5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITE-STATE MACHINE 134 5.11 SUMMARY 143 6 INTRODUCTION TO VERFLOG HDL 145 6.1 A BRIEF BACKGROUND TO HARDWARE DESCRIPTION LANGUAGES 145 6.2 HARDWARE MODELLING WITH VERFLOG HDL: THE MODULE 147 6.3 MODULES WITHIN MODULES: CREATING HIERARCHY 152 6.4 VERFLOG HDL SIMULATION: A COMPLETE EXAMPLE 155 REFERENCES 162 7 ELEMENTS OF VERFLOG HDL 163 7.1 BUILT-IN PRIMITIVES AND TYPES 163 CONTENTS III 7.1.1 VERFLOG TYPES 163 7.1.2 VERFLOG LOGIC AND NUMERIC VALUES 167 7.1.3 SPECIFYING VALUES 169 7.1.4 VERFLOG HDL PRIMITIVE GATES 170 7.2 OPERATORS AND EXPRESSIONS 172 7.3 EXAMPLE ILLUSTRATING THE USE OF VERFLOG HDL OPERATORS: HAMMING CODE ENCODER 185 7.3.1 SIMULATING THE HAMMING ENCODER 188 REFERENCES 195 8 DESCRIBING COMBINATIONAL AND SEQUENTIAL LOGIC USING VERILOG HDL 197 8.1 THE DATA-FLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT 197 8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK 198 8.3 ASSIGNMENTS WITHIN SEQUENTIAL BLOCKS: BLOCKING AND NONBLOCKING 204 8.3.1 SEQUENTIAL STATEMENTS 204 8.4 DESCRIBING COMBINATIONAL LOGIC USING A SEQUENTIAL BLOCK 209 8.5 DESCRIBING SEQUENTIAL LOGIC USING A SEQUENTIAL BLOCK 217 8.6 DESCRIBING MEMORIES 229 8.7 DESCRIBING FINITE-STATE MACHINES 240 8.7.1 EXAMPLE 1: CHESS CLOCK CONTROLLER FINITE-STATE MACHINE 245 8.7.2 EXAMPLE 2: COMBINATION LOCK FINITE-STATE MACHINE WITH AUTOMATIC LOCK FEATURE 252 REFERENCES 265 9 ASYNCHRONOUS FINITE-STATE MACHINES 267 9.1 INTRODUCTION 267 9.2 DEVELOPMENT OF EVENT-DRIVEN LOGIC 269 9.3 USING THE SEQUENTIAL EQUATION TO SYNTHESIZE AN EVENT FINITE-STATE MACHINE 272 9.3.1 SHORT-CUT RULE 275 9.4 IMPLEMENTING THE DESIGN USING SUM OF PRODUCT AS USED IN A PROGRAMMABLE LOGIC DEVICE 276 9.4.1 DROPPING THE PRESENT STATE N AND NEXT STATE N + 1 NOTATION 277 9.5 DEVELOPMENT OF AN EVENT VERSION OF THE SINGLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE 277 9.6 ANOTHER EVENT FINITE-STATE MACHINE DESIGN FROM SPECIFICATION THROUGH TO SIMULATION 280 9.6.1 IMPORTANTNOTE! 280 9.6.2 A MOTOR CONTROLLER WITH FAULT CURRENT MONITORING 281 9.7 THE HOVER MOWER FINITE-STATE MACHINE 285 9.7.1 THE SPECIFICATION AND A POSSIBLE SOLUTION 285 9.8 AN EXAMPLE WITH A TRANSITION WITHOUT ANY INPUT 289 9.9 UNUSUAL EXAMPLE: RESPONDING TO A MICROPROCESSOR-ADDRESSED LOCATION 291 9.10 AN EXAMPLE THAT USES A MEALY OUTPUT 293 9.10.1 TANK WATER LEVEL CONTROL SYSTEM WITH SOLUTIONS 293 9.11 AN EXAMPLE USING A RELAY CIRCUIT 296 IV CONTENTS 9.12 RACE CONDITIONS IN AN EVENT FINITE-STATE MACHINE 299 9.12.1 RACE BETWEEN PRIMARY INPUTS 300 9.12.2 RACE BETWEEN SECONDARY STATE VARIABLES 300 9.12.3 RACE BETWEEN PRIMARY AND SECONDARY VARIABLES 300 9.13 WAIT-STATE GENERATOR FOR A MICROPROCESSOR SYSTEM 301 9.14 DEVELOPMENT OF AN ASYNCHRONOUS FINITE-STATE MACHINE FOR A CLOTHES SPINNER SYSTEM 304 9.15 CAUTION WHEN USING TWO-WAY BRANCHES 309 9.16 SUMMARY 312 REFERENCES 312 10 INTRODUCTION TO PETRI NETS 313 10.1 INTRODUCTION TO SIMPLE PETRI NETS 313 10.2 SIMPLE SEQUENTIAL EXAMPLE USING A PETRI NET 318 10.3 PARALLEL PETRI NETS 319 10.3.1 ANOTHER EXAMPLE OFA PARALLEL PETRI NET 323 10.4 SYNCHRONIZING FLOW IN A PARALLEL PETRI NET 324 10.4.1 ENABLING AND DISABLING ARES 325 10.5 SYNCHRONIZATION OF TWO PETRI NETS USING ENABLING AND DISABLING ARES 326 10.6 CONTROL OF A SHARED RESOURCE 327 10.7 A SERIAL RECEIVER OF BINARY DATA 329 10.7.1 EQUATIONS FOR THE FIRST PETRI NET 333 10.7.2 OUTPUT 333 10.7.3 EQUATIONS FOR THE MAIN PETRI NET 333 10.7.4 OUTPUTS 333 10.7.5 THE SHIFT REGISTER 334 10.7.6 EQUATIONS FOR THE SHIFT REGISTER 334 10.7.7 THE DIVIDE-BY-11 COUNTER 335 10.7.8 THE DATA LATCH 335 10.8 SUMMARY 336 REFERENCES 336 APPENDIX A: LOGIC GATES AND BOOLEAN ALGEBRA USED IN THE BOOK 337 A. 1 BASIC GATE SYMBOLS USED IN THE BOOK WITH BOOLEAN EQUATIONS 337 A.2 THE EXCLUSIVE OR AND EXCLUSIVE NOR 338 A.3 LAWS OF BOOLEAN ALGEBRA 338 A.3.1 BASIC ORRULES 339 A.3.2 BASIC AND RULES 339 A.3.3 ASSOCIATIVE AND COMMUTATIVE LAWS 340 A.3.4 DISTRIBUTIVE LAWS 340 A.3.5 AUXILIARY LAW FOR STATIC 1 HAZARD REMOVAL 341 A.3.5.1 PROOFOF AUXILIARY RULE 341 A.3.6 CONSENSUS THEOREM 342 A.3.7 THE EFFECT OF SIGNAL DELAY IN LOGIC GATES 343 A.3.8 DE MORGAN S THEOREM 343 CONTENTS V A.4 EXAMPLES OF APPLYING THE LAWS OF BOOLEAN ALGEBRA 345 A.4.1 EXAMPLE: CONVERTING AND-OR TO NAND 345 A.4.2 EXAMPLE: CONVERTING AND-OR TO NOR 345 A.4.3 LOGICAL ADJACENCY RULE 345 A.5 SUMMARY 346 APPENDIX B: COUNTING AND SHIFTING CIRCUIT TECHNIQUES 347 B. 1 BASIC UP AND DOWN SYNCHRONOUS BINARY COUNTER DEVELOPMENT 347 B.2 EXAMPLE FOR A 4-BIT SYNCHRONOUS UP-COUNTER USING T-TYPE FLIP-FLOPS 349 B.3 PARALLEL-LOADING COUNTERS: USING T FLIP-FLOPS 352 B.4 USING D FLIP-FLOPS TO BUILD PARALLEL-LOADING COUNTERS WITH CHEAP PROGRAMMABLE LOGIC DEVICES 353 B.5 SIMPLE BINARY UP-COUNTER: WITH PARALLEL INPUTS 354 B.6 CLOCK CIRCUIT TO DRIVE THE COUNTER (AND FINITE-STATE MACHINES) 355 B.7 COUNTER DESIGN USING DON T CARE STATES 355 B.8 SHIFT REGISTERS 357 B.9 ASYNCHRONOUS RECEIVER DETAILS OF CHAPTER 4 358 B.9.1 THE 11-BIT SHIFT REGISTERS FOR THE ASYNCHRONOUS RECEIVER MODULE 360 B.9.2 DIVIDE-BY-11 COUNTER 362 B.9.3 COMPLETE SIMULATION OF THE ASYNCHRONOUS RECEIVER MODULE OF CHAPTER 4 364 B.10 SUMMARY 365 APPENDIX C: TUTORIAL ON THE USE OF VERILOG HDL TO SIMULATE A FINITE-STATE MACHINE DESIGN 367 C. 1 INTRODUCTION 367 C.2 THE SINGLE PULSE WITH MEMORY SYNCHRONOUS FINITE-STATE MACHINE DESIGN: USING VERILOG HDL TO SIMULATE 367 C.2.1 SPECIFICATION 367 C.2.2 BLOCK DIAGRAM 367 C.2.3 STATE DIAGRAM 368 C.2.4 EQUATIONS FROM THE STATE DIAGRAM 368 C.2.5 TRANSLATION INTO A VERILOG DESCRIPTION 369 C.3 TEST-BENCH MODULE AND ITS PURPOSE 372 C.4 USING SYNAPTICAD S VERILOGGER EXTREME SIMULATOR 376 C.5 SUMMARY 378 APPENDIX D: IMPLEMENTING STATE MACHINES USING VERILOG BEHAVIOURAL MODE 379 D.L INTRODUCTION 379 D.2 THE SINGLE-PULSE/MULTIPLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE REVISITED 379 D.3 THE MEMORY TESTER FINITE-STATE MACHINE IN SECTION 5.6 383 D.4 SUMMARY 386 INDEX 387
adam_txt	FSM-BASED DIGITAL DESIGN USING VERIIOG HDL PETER MINNS LAN ELLIOTT NORTHUMBRIA UNIVERSITY, UK JOHN WILEY & SONS, LTD CONTENTS PREFACE XI ACKNOWLEDGEMENTS XV 1 INTRODUCTION TO FINITE-STATE MACHINES AND STATE DIAGRAMS FOR THE DESIGN OF ELECTRONIC CIRCUITS AND SYSTEMS 1 1.1 INTRODUCTION 1 1.2 LEARNING MATERIAL 2 1.3 SUMMARY 21 2 USING STATE DIAGRAMS TO CONTROL EXTERNAL HARDWARE SUBSYSTEMS 23 2.1 INTRODUCTION 23 2.2 LEARNING MATERIAL 23 2.3 SUMMARY 38 3 SYNTHESIZING HARDWARE FROM A STATE DIAGRAM 39 3.1 INTRODUCTION TO FINITE-STATE MACHINE SYNTHESIS 39 3.2 LEARNING MATERIAL 40 3.3 SUMMARY 66 4 SYNCHRONOUS FINITE-STATE MACHINE DESIGNS 67 4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD 67 4.2 DEALING WITH UNUSED STATES 69 4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM 71 4.3.1 TESTING THE FINITE-STATE MACHINE USING A TEST-BENCH MODULE 75 4.4 SIMPLE WAVEFORM GENERATOR 76 4.4.1 SAMPLING FREQUENCY AND SAMPLES PER WAVEFORM 78 4.5 THE DICE GAME 79 4.5.1 DEVELOPMENT OF THE EQUATIONS FOR THE DICE GAME 81 II CONTENTS 4.6 BINARY DATA SERIAL TRANSMITTER 83 4.6.1 THE RECOUNTER BLOCK IN THE SHIFT REGISTER OFFIGURE 4.15 87 4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER 88 4.7.1 FINITE-STATE MACHINE EQUATIONS 91 4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM 92 4.8.1 TO INCORPORATE THE PARITY 92 4.8.2 OE-TYPE EQUATIONS FOR FIGURE 4.26 94 4.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM 95 4.9.1 EQUATIONS FOR THE ASYNCHRONOUS SERIAL TRANSMITTER 98 4.10 CLOCKEDWATCHDOG TIMER 100 4.10.1 D FLIP-FLOP EQUATIONS 102 4.10.2 OUTPUT EQUATION 102 4.11 SUMMARY 103 5 THE ONE HOT TECHNIQUE IN FINITE-STATE MACHINE DESIGN 105 5.1 THE ONE HOT TECHNIQUE 105 5.2 A DATA ACQUISITION SYSTEM 110 5.3 A SHARED MEMORY SYSTEM 114 5.4 FAST WAVEFORM SYNTHESIZER 116 5.4.1 SPECIFICATION 117 5.4.2 A POSSIBLE SOLUTION 118 5.4.3 EQUATIONS FOR THE D INPUTS TO D FLIP-FLOPS 119 5.4.4 OUTPUT EQUATIONS 120 5.5 CONTROLLING THE FINITE-STATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER 120 5.6 A MEMORY-CHIP TESTER 123 5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHODOFCHAPTER4 126 5.8 A DYNAMIC MEMORY ACCESS CONTROLLER 127 5.8.1 FLIP-FLOP EQUATIONS 131 5.8.2 OUTPUT EQUATIONS 131 5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR 132 5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITE-STATE MACHINE 134 5.11 SUMMARY 143 6 INTRODUCTION TO VERFLOG HDL 145 6.1 A BRIEF BACKGROUND TO HARDWARE DESCRIPTION LANGUAGES 145 6.2 HARDWARE MODELLING WITH VERFLOG HDL: THE MODULE 147 6.3 MODULES WITHIN MODULES: CREATING HIERARCHY 152 6.4 VERFLOG HDL SIMULATION: A COMPLETE EXAMPLE 155 REFERENCES 162 7 ELEMENTS OF VERFLOG HDL 163 7.1 BUILT-IN PRIMITIVES AND TYPES 163 CONTENTS III 7.1.1 VERFLOG TYPES 163 7.1.2 VERFLOG LOGIC AND NUMERIC VALUES 167 7.1.3 SPECIFYING VALUES 169 7.1.4 VERFLOG HDL PRIMITIVE GATES 170 7.2 OPERATORS AND EXPRESSIONS 172 7.3 EXAMPLE ILLUSTRATING THE USE OF VERFLOG HDL OPERATORS: HAMMING CODE ENCODER 185 7.3.1 SIMULATING THE HAMMING ENCODER 188 REFERENCES 195 8 DESCRIBING COMBINATIONAL AND SEQUENTIAL LOGIC USING VERILOG HDL 197 8.1 THE DATA-FLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT 197 8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK 198 8.3 ASSIGNMENTS WITHIN SEQUENTIAL BLOCKS: BLOCKING AND NONBLOCKING 204 8.3.1 SEQUENTIAL STATEMENTS 204 8.4 DESCRIBING COMBINATIONAL LOGIC USING A SEQUENTIAL BLOCK 209 8.5 DESCRIBING SEQUENTIAL LOGIC USING A SEQUENTIAL BLOCK 217 8.6 DESCRIBING MEMORIES 229 8.7 DESCRIBING FINITE-STATE MACHINES 240 8.7.1 EXAMPLE 1: CHESS CLOCK CONTROLLER FINITE-STATE MACHINE 245 8.7.2 EXAMPLE 2: COMBINATION LOCK FINITE-STATE MACHINE WITH AUTOMATIC LOCK FEATURE 252 REFERENCES 265 9 ASYNCHRONOUS FINITE-STATE MACHINES 267 9.1 INTRODUCTION 267 9.2 DEVELOPMENT OF EVENT-DRIVEN LOGIC 269 9.3 USING THE SEQUENTIAL EQUATION TO SYNTHESIZE AN EVENT FINITE-STATE MACHINE 272 9.3.1 SHORT-CUT RULE 275 9.4 IMPLEMENTING THE DESIGN USING SUM OF PRODUCT AS USED IN A PROGRAMMABLE LOGIC DEVICE 276 9.4.1 DROPPING THE PRESENT STATE N AND NEXT STATE N + 1 NOTATION 277 9.5 DEVELOPMENT OF AN EVENT VERSION OF THE SINGLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE 277 9.6 ANOTHER EVENT FINITE-STATE MACHINE DESIGN FROM SPECIFICATION THROUGH TO SIMULATION 280 9.6.1 IMPORTANTNOTE! 280 9.6.2 A MOTOR CONTROLLER WITH FAULT CURRENT MONITORING 281 9.7 THE HOVER MOWER FINITE-STATE MACHINE 285 9.7.1 THE SPECIFICATION AND A POSSIBLE SOLUTION 285 9.8 AN EXAMPLE WITH A TRANSITION WITHOUT ANY INPUT 289 9.9 UNUSUAL EXAMPLE: RESPONDING TO A MICROPROCESSOR-ADDRESSED LOCATION 291 9.10 AN EXAMPLE THAT USES A MEALY OUTPUT 293 9.10.1 TANK WATER LEVEL CONTROL SYSTEM WITH SOLUTIONS 293 9.11 AN EXAMPLE USING A RELAY CIRCUIT 296 IV CONTENTS 9.12 RACE CONDITIONS IN AN EVENT FINITE-STATE MACHINE 299 9.12.1 RACE BETWEEN PRIMARY INPUTS 300 9.12.2 RACE BETWEEN SECONDARY STATE VARIABLES 300 9.12.3 RACE BETWEEN PRIMARY AND SECONDARY VARIABLES 300 9.13 WAIT-STATE GENERATOR FOR A MICROPROCESSOR SYSTEM 301 9.14 DEVELOPMENT OF AN ASYNCHRONOUS FINITE-STATE MACHINE FOR A CLOTHES SPINNER SYSTEM 304 9.15 CAUTION WHEN USING TWO-WAY BRANCHES 309 9.16 SUMMARY 312 REFERENCES 312 10 INTRODUCTION TO PETRI NETS 313 10.1 INTRODUCTION TO SIMPLE PETRI NETS 313 10.2 SIMPLE SEQUENTIAL EXAMPLE USING A PETRI NET 318 10.3 PARALLEL PETRI NETS 319 10.3.1 ANOTHER EXAMPLE OFA PARALLEL PETRI NET 323 10.4 SYNCHRONIZING FLOW IN A PARALLEL PETRI NET 324 10.4.1 ENABLING AND DISABLING ARES 325 10.5 SYNCHRONIZATION OF TWO PETRI NETS USING ENABLING AND DISABLING ARES 326 10.6 CONTROL OF A SHARED RESOURCE 327 10.7 A SERIAL RECEIVER OF BINARY DATA 329 10.7.1 EQUATIONS FOR THE FIRST PETRI NET 333 10.7.2 OUTPUT 333 10.7.3 EQUATIONS FOR THE MAIN PETRI NET 333 10.7.4 OUTPUTS 333 10.7.5 THE SHIFT REGISTER 334 10.7.6 EQUATIONS FOR THE SHIFT REGISTER 334 10.7.7 THE DIVIDE-BY-11 COUNTER 335 10.7.8 THE DATA LATCH 335 10.8 SUMMARY 336 REFERENCES 336 APPENDIX A: LOGIC GATES AND BOOLEAN ALGEBRA USED IN THE BOOK 337 A. 1 BASIC GATE SYMBOLS USED IN THE BOOK WITH BOOLEAN EQUATIONS 337 A.2 THE EXCLUSIVE OR AND EXCLUSIVE NOR 338 A.3 LAWS OF BOOLEAN ALGEBRA 338 A.3.1 BASIC ORRULES 339 A.3.2 BASIC AND RULES 339 A.3.3 ASSOCIATIVE AND COMMUTATIVE LAWS 340 A.3.4 DISTRIBUTIVE LAWS 340 A.3.5 AUXILIARY LAW FOR STATIC 1 HAZARD REMOVAL 341 A.3.5.1 PROOFOF AUXILIARY RULE 341 A.3.6 CONSENSUS THEOREM 342 A.3.7 THE EFFECT OF SIGNAL DELAY IN LOGIC GATES 343 A.3.8 DE MORGAN'S THEOREM 343 CONTENTS V A.4 EXAMPLES OF APPLYING THE LAWS OF BOOLEAN ALGEBRA 345 A.4.1 EXAMPLE: CONVERTING AND-OR TO NAND 345 A.4.2 EXAMPLE: CONVERTING AND-OR TO NOR 345 A.4.3 LOGICAL ADJACENCY RULE 345 A.5 SUMMARY 346 APPENDIX B: COUNTING AND SHIFTING CIRCUIT TECHNIQUES 347 B. 1 BASIC UP AND DOWN SYNCHRONOUS BINARY COUNTER DEVELOPMENT 347 B.2 EXAMPLE FOR A 4-BIT SYNCHRONOUS UP-COUNTER USING T-TYPE FLIP-FLOPS 349 B.3 PARALLEL-LOADING COUNTERS: USING T FLIP-FLOPS 352 B.4 USING D FLIP-FLOPS TO BUILD PARALLEL-LOADING COUNTERS WITH CHEAP PROGRAMMABLE LOGIC DEVICES 353 B.5 SIMPLE BINARY UP-COUNTER: WITH PARALLEL INPUTS 354 B.6 CLOCK CIRCUIT TO DRIVE THE COUNTER (AND FINITE-STATE MACHINES) 355 B.7 COUNTER DESIGN USING DON'T CARE STATES 355 B.8 SHIFT REGISTERS 357 B.9 ASYNCHRONOUS RECEIVER DETAILS OF CHAPTER 4 358 B.9.1 THE 11-BIT SHIFT REGISTERS FOR THE ASYNCHRONOUS RECEIVER MODULE 360 B.9.2 DIVIDE-BY-11 COUNTER 362 B.9.3 COMPLETE SIMULATION OF THE ASYNCHRONOUS RECEIVER MODULE OF CHAPTER 4 364 B.10 SUMMARY 365 APPENDIX C: TUTORIAL ON THE USE OF VERILOG HDL TO SIMULATE A FINITE-STATE MACHINE DESIGN 367 C. 1 INTRODUCTION 367 C.2 THE SINGLE PULSE WITH MEMORY SYNCHRONOUS FINITE-STATE MACHINE DESIGN: USING VERILOG HDL TO SIMULATE 367 C.2.1 SPECIFICATION 367 C.2.2 BLOCK DIAGRAM 367 C.2.3 STATE DIAGRAM 368 C.2.4 EQUATIONS FROM THE STATE DIAGRAM 368 C.2.5 TRANSLATION INTO A VERILOG DESCRIPTION 369 C.3 TEST-BENCH MODULE AND ITS PURPOSE 372 C.4 USING SYNAPTICAD'S VERILOGGER EXTREME SIMULATOR 376 C.5 SUMMARY 378 APPENDIX D: IMPLEMENTING STATE MACHINES USING VERILOG BEHAVIOURAL MODE 379 D.L INTRODUCTION 379 D.2 THE SINGLE-PULSE/MULTIPLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE REVISITED 379 D.3 THE MEMORY TESTER FINITE-STATE MACHINE IN SECTION 5.6 383 D.4 SUMMARY 386 INDEX 387
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id	DE-604.BV023420373
illustrated	Illustrated
index_date	2024-07-02T21:30:51Z
indexdate	2024-07-09T21:18:15Z
institution	BVB
isbn	9780470060704 0470060700
language	English
lccn	2007043838
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-016602824
oclc_num	180907474
open_access_boolean
owner	DE-573 DE-898 DE-BY-UBR DE-634
owner_facet	DE-573 DE-898 DE-BY-UBR DE-634
physical	XIII, 391 S. Ill., graph. Darst. 1 CD-ROM (12 cm)
publishDate	2008
publishDateSearch	2008
publishDateSort	2008
publisher	Wiley
record_format	marc
spelling	Minns, Peter Verfasser aut FSM-based digital design using Verilog HDL Peter Minns ; Ian Elliott Finite state machine based digital design using Verilog HDL Chichester [u.a.] Wiley 2008 XIII, 391 S. Ill., graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Verilog (Computer hardware description language) Digital electronics Sequential machine theory VERILOG (DE-588)4268385-3 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 gnd rswk-swf Digitales System (DE-588)4012300-5 gnd rswk-swf Digitales System (DE-588)4012300-5 s VERILOG (DE-588)4268385-3 s DE-604 Digitalelektronik (DE-588)4260328-6 s Elliott, Ian Verfasser aut http://www.loc.gov/catdir/enhancements/fy0804/2007043838-t.html Table of contents only http://www.loc.gov/catdir/enhancements/fy0804/2007043838-d.html Publisher description GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016602824&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Minns, Peter Elliott, Ian FSM-based digital design using Verilog HDL Verilog (Computer hardware description language) Digital electronics Sequential machine theory VERILOG (DE-588)4268385-3 gnd Digitalelektronik (DE-588)4260328-6 gnd Digitales System (DE-588)4012300-5 gnd
subject_GND	(DE-588)4268385-3 (DE-588)4260328-6 (DE-588)4012300-5
title	FSM-based digital design using Verilog HDL
title_alt	Finite state machine based digital design using Verilog HDL
title_auth	FSM-based digital design using Verilog HDL
title_exact_search	FSM-based digital design using Verilog HDL
title_exact_search_txtP	FSM-based digital design using Verilog HDL
title_full	FSM-based digital design using Verilog HDL Peter Minns ; Ian Elliott
title_fullStr	FSM-based digital design using Verilog HDL Peter Minns ; Ian Elliott
title_full_unstemmed	FSM-based digital design using Verilog HDL Peter Minns ; Ian Elliott
title_short	FSM-based digital design using Verilog HDL
title_sort	fsm based digital design using verilog hdl
topic	Verilog (Computer hardware description language) Digital electronics Sequential machine theory VERILOG (DE-588)4268385-3 gnd Digitalelektronik (DE-588)4260328-6 gnd Digitales System (DE-588)4012300-5 gnd
topic_facet	Verilog (Computer hardware description language) Digital electronics Sequential machine theory VERILOG Digitalelektronik Digitales System
url	http://www.loc.gov/catdir/enhancements/fy0804/2007043838-t.html http://www.loc.gov/catdir/enhancements/fy0804/2007043838-d.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016602824&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT minnspeter fsmbaseddigitaldesignusingveriloghdl AT elliottian fsmbaseddigitaldesignusingveriloghdl AT minnspeter finitestatemachinebaseddigitaldesignusingveriloghdl AT elliottian finitestatemachinebaseddigitaldesignusingveriloghdl

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