Design of analog CMOS integrated circuits:
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
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Boston [u.a.]
McGraw-Hill
2007
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| Ausgabe: | International ed., [Nachdr.] |
| Schriftenreihe: | McGraw-Hill series in electrical and computer engineering
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XX, 684 S. graph. Darst. |
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Datensatz im Suchindex
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| adam_text | DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS BEHZAD RAZAVI PROFESSOR OF
ELECTRICAL ENGINEERING UNIVERSITY OF CALIFORNIA, LOS ANGELES H BOSTON
BURR RIDGE, IL DUBUQUE, IA MADISON, WI NEW YORK SAN FRANCISCO ST. LOUIS
BANGKOK BOGOTA CARACAS KUALA LUMPUR LISBON LONDON MADRID MEXICO CITY
MILAN MONTREAL NEW DELHI SANTIAGO SEOUL SINGAPORE SYDNEY TAIPEI TORONTO
CONTENTS ABOUT THE AUTHOR VII PREFACE IX ACKNOWLEDGMENTS XI 1
INTRODUCTION TO ANALOG DESIGN 1 1.1 WHY ANALOG? 1 1.2 WHY INTEGRATED? 6
1.3 WHY CMOS? 6 1.4 WHY THIS BOOK? 7 1.5 GENERAL CONCEPTS 7 1.5.1 LEVELS
OF ABSTRACTION 7 1.5.2 ROBUST ANALOG DESIGN 7 2 BASIC MOS DEVICE PHYSICS
9 2.1 GENERAL CONSIDERATIONS 10 2.1.1 MOSFET AS A SWITCH 10 2.1.2 MOSFET
STRUCTURE 10 2.1.3 MOS SYMBOLS 12 2.2 MOS I/V CHARACTERISTICS 13 2.2.1
THRESHOLD VOLTAGE 13 2.2.2 DERIVATION OF I/V CHARACTERISTICS 15 2.3
SECOND-ORDER EFFECTS 23 2.4 MOS DEVICE MODELS 28 2.4.1 MOS DEVICE LAYOUT
28 2.4.2 MOS DEVICE CAPACITANCES 29 2.4.3 MOS SMALL-SIGNAL MODEL 33
2.4.4 MOS SPICE MODEIS 36 2.4.5 NMOS VERSUS PMOS DEVICES 37 2.4.6
LONG-CHANNEL VERSUS SHORT-CHANNEL DEVICES 38 XV XVI CONTENTS 3
SINGLE-STAGE AMPLIFIERS 47 3.1 BASIC CONCEPTS 47 3.2 COMMON-SOURCE STAGE
48 3.2.1 COMMON-SOURCE STAGE WITH RESISTIVE LOAD 48 3.2.2 CS STAGE WITH
DIODE-CONNECTED LOAD 53 3.2.3 CS STAGE WITH CURRENT-SOURCE LOAD 58 3.2.4
CS STAGE WITH TRIODE LOAD 59 3.2.5 CS STAGE WITH SOURCE DEGENERATION 60
3.3 SOURCE FOLLOWER 67 3.4 COMMON-GATE STAGE 76 3.5 CASCODE STAGE 83
3.5.1 FOLDED CASCODE 90 3.6 CHOICE OF DEVICE MODELS 92 4 DIFFERENTIAL
AMPLIFIERS 100 4.1 SINGLE-ENDED AND DIFFERENTIAL OPERATION 100 4.2 BASIC
DIFFERENTIAL PAIR 103 4.2.1 QUALITATIVE ANALYSIS 104 4.2.2 QUANTITATIVE
ANALYSIS 107 4.3 COMMON-MODE RESPONSE 118 4.4 DIFFERENTIAL PAIR WITH MOS
LOADS 124 4.5 GILBERT CELL 126 5 PASSIVE AND ACTIVE CURRENT MIRRORS 135
5.1 BASIC CURRENT MIRRORS 135 5.2 CASCODE CURRENT MIRRORS 139 5.3 ACTIVE
CURRENT MIRRORS 145 5.3.1 LARGE-SIGNAL ANALYSIS 149 5.3.2 SMALL-SIGNAL
ANALYSIS 151 5.3.3 COMMON-MODE PROPERTIES 154 6 FREQUENCY RESPONSE OF
AMPLIFIERS 166 6.1 GENERAL CONSIDERATIONS 166 6.1.1 MILLER EFFECT 166
6.1.2 ASSOCIATION OF POLES WITH NODES 169 6.2 COMMON-SOURCE STAGE 172
6.3 SOURCE FOLLOWERS 178 6.4 COMMON-GATE STAGE 183 6.5 CASCODE STAGE 185
6.6 DIFFERENTIAL PAIR 187 APPENDIX A: DUAL OF MILLER S THEOREM 193 XVII
7 NOISE 201 7.1 STATISTICAL CHARACTERISTICS OF NOISE 201 7.1.1 NOISE
SPECTRUM 203 7.1.2 AMPLITUDE DISTRIBUTION 206 7.1.3 CORRELATED AND
UNCORRELATED SOURCES 207 7.2 TYPES OF NOISE 209 7.2.1 THERMAL NOISE 209
7.2.2 FLICKER NOISE 215 7.3 REPRESENTATION OF NOISE IN CIRCUITS 218 7.4
NOISE IN SINGLE-STAGE AMPLIFIERS 224 7.4.1 COMMON-SOURCE STAGE 225 7.4.2
COMMON-GATE STAGE 228 7.4.3 SOURCE FOLLOWERS 231 7.4.4 CASCODE STAGE 232
7.5 NOISE IN DIFFERENTIAL PAIRS 233 7.6 NOISE BANDWIDTH 239 8 FEEDBACK
246 8.1 GENERAL CONSIDERATIONS 246 8.1.1 PROPERTIES OF FEEDBACK CIRCUITS
247 8.1.2 TYPES OF AMPLIFIERS 254 8.2 FEEDBACK TOPOLOGIES 258 8.2.1
VOLTAGE-VOLTAGE FEEDBACK 258 8.2.2 CURRENT-VOLTAGE FEEDBACK 263 8.2.3
VOLTAGE-CURRENT FEEDBACK 266 8.2.4 CURRENT-CURRENT FEEDBACK 269 8.3
EFFECT OF LOADING 270 8.3.1 TWO-PORT NETWORK MODELS 270 8.3.2 LOADING IN
VOLTAGE-VOLTAGE FEEDBACK 272 8.3.3 LOADING IN CURRENT-VOLTAGE FEEDBACK
275 8.3.4 LOADING IN VOLTAGE-CURRENT FEEDBACK 278 8.3.5 LOADING IN
CURRENT-CURRENT FEEDBACK 281 8.3.6 SUMMARY OF LOADING EFFECTS 283 8.4
EFFECT OF FEEDBACK ON NOISE 284 9 OPERATIONAL AMPLIFIERS 291 9.1 GENERAL
CONSIDERATIONS 291 9.1.1 PERFORMANCE PARAMETERS . 291 9.2 ONE-STAGE OP
AMPS 296 9.3 TWO-STAGE OP AMPS 307 9.4 GAIN BOOSTING 309 9.5 COMPARISON
313 9.6 COMMON-MODE FEEDBACK 314 CONTENTS 9.7 INPUT RANGE LIMITATIONS
325 9.8 SLEW RATE 326 9.9 POWER SUPPLY REJECTION 334 9.10 NOISE IN OP
AMPS 336 10 STABILITY AND FREQUENCY COMPENSATION 345 10.1 GENERAL
CONSIDERATIONS 345 10.2 MULTIPOLE SYSTEMS 349 10.3 PHASE MARGIN 351
10.4 FREQUENCY COMPENSATION 355 10.5 COMPENSATION OF TWO-STAGE OP AMPS
361 10.5.1 SLEWING IN TWO-STAGE OP AMPS 368 10.6 OTHER COMPENSATION
TECHNIQUES 369 11 BANDGAP REFERENCES 377 11.1 GENERAL CONSIDERATIONS 377
11.2 SUPPLY-INDEPENDENT BIASING 377 11.3 TEMPERATURE-INDEPENDENT
REFERENCES 381 11.3.1 NEGATIVE-TC VOLTAGE 381 11.3.2 POSITIVE-TC VOLTAGE
382 11.3.3 BANDGAP REFERENCE 384 11.4 PTAT CURRENT GENERATION 390 11.5
CONSTANT-G M BIASING 392 11.6 SPEED AND NOISE ISSUES 393 11.7 CASE STUDY
397 12 INTRODUCTION TO SWITCHED-CAPACITOR CIRCUITS 405 12.1 GENERAL
CONSIDERATIONS 405 12.2 SAMPLING SWITCHES 410 12.2.1 MOSFETS AS SWITCHES
410 12.2.2 SPEED CONSIDERATIONS 414 12.2.3 PRECISION CONSIDERATIONS 417
12.2.4 CHARGE INJECTION CANCELLATION 421 12.3 SWITCHED-CAPACITOR
AMPLIFIERS 423 12.3.1 UNITY-GAIN SAMPLER/BUFFER 424 12.3.2 NONINVERTING
AMPLIFIER 432 12.3.3 PRECISION MULTIPLY-BY-TWO CIRCUIT 438 12.4
SWITCHED-CAPACITOR INTEGRATOR 439 12.5 SWITCHED-CAPACITOR COMMON-MODE
FEEDBACK 442 13 NONLINEARITY AND MISMATCH 448 13.1 NONLINEARITY 448
13.1.1 GENERAL CONSIDERATIONS 448 XIX 13.1.2 NONLINEARITY OF
DIFFERENTIAL CIRCUITS 452 13.1.3 EFFECT OF NEGATIVE FEEDBACK ON
NONLINEARITY 454 13.1.4 CAPACITOR NONLINEARITY 457 13.1.5 LINEARIZATION
TECHNIQUES 458 13.2 MISMATCH 463 13.2.1 OFFSET CANCELLATION TECHNIQUES
471 13.2.2 REDUCTION OF NOISE BY OFFSET CANCELLATION 476 13.2.3
ALTERNATIVE DEFINITION OF CMRR 478 14 OSCILLATORS 482 14.1 GENERAL
CONSIDERATIONS 482 14.2 RING OSCILLATORS 484 14.3 LC OSCILLATORS 495
14.3.1 CROSSED-COUPLED OSCILLATOR 499 14.3.2 COLPITTS OSCILLATOR 502
14.3.3 ONE-PORT OSCILLATORS 505 14.4 VOLTAGE-CONTROLLED OSCILLATORS 510
14.4.1 TUNING IN RING OSCILLATORS 512 14.4.2 TUNING IN LC OSCILLATORS
521 14.5 MATHEMATICAL MODEL OF VCOS 525 15 PHASE-LOCKED LOOPS 532 15.1
SIMPLE PLL 532 15.1.1 PHASE DETECTOR 532 15.1.2 BASIC PLL TOPOLOGY 533
15.1.3 DYNAMICS OF SIMPLE PLL 542 15.2 CHARGE-PUMP PLLS 549 15.2.1
PROBLEM OF LOCK ACQUISITION 549 15.2.2 PHASE/FREQUENCY DETECTOR AND
CHARGE PUMP 550 15.2.3 BASIC CHARGE-PUMP PLL 556 15.3 NONIDEAL EFFECTS
IN PLLS 562 15.3.1 PFD/CP NONIDEALITIES 562 15.3.2 JITTER IN PLLS 567
15.4 DELAY-LOCKED LOOPS 569 15.5 APPLICATIONS 572 15.5.1 FREQUENCY
MULTIPLICATION AND SYNTHESIS 572 15.5.2 SKEW REDUCTION 574 15.5.3 JITTER
REDUCTION 576 16 SHORT-CHANNEL EFFECTS AND DEVICE MODELS 579 16.1
SCALING THEORY 579 16.2 SHORT-CHANNEL EFFECTS 583 CONTENTS 16.2.1
THRESHOLD VOLTAGE VARIATION 583 16.2.2 MOBILITY DEGRADATION WITH
VERTICAL FIELD 585 16.2.3 VELOCITY SATURATION 587 16.2.4 HOT CARRIER
EFFECTS 589 16.2.5 OUTPUT IMPEDANCE VARIATION WITH DRAIN-SOURCE VOLTAGE
589 16.3 MOS DEVICE MODELS 591 16.3.1 LEVEL 1 MODEL 592 16-3.2 LEVEL 2
MODEL 593 16.3.3 LEVEL 3 MODEL 595 16.3.4 BSIM SERIES 596 16.3.5 OTHER
MODELS 597 16.3.6 CHARGE AND CAPACITANCE MODELING 598 16.3.7 TEMPERATURE
DEPENDENCE 599 16.4 PROCESS CORNERS 599 16.5 ANALOG DESIGN IN A DIGITAL
WORLD 600 17 CMOS PROCESSING TECHNOLOGY 604 17.1 GENERAL CONSIDERATIONS
604 17.2 WAFER PROCESSING 605 17.3 PHOTOLITHOGRAPHY 606 17.4 OXIDATION
608 17.5 ION IMPLANTATION 608 17.6 DEPOSITION AND ETCHING 611 17.7
DEVICE FABRICATION 611 17.7.1 ACTIVE DEVICES 611 17.7.2 PASSIVE DEVICES
616 17.7.3 INTERCONNECTS 624 17.8 LATCH-UP 627 18 LAYOUT AND PACKAGING
631 18.1 GENERAL LAYOUT CONSIDERATIONS 631 18.1.1 DESIGN RULES 632
18.1.2 ANTENNA EFFECT 634 18.2 ANALOG LAYOUT TECHNIQUES 635 18.2.1
MULTIFINGER TRANSISTORS 635 18.2.2 SYMMETRY 637 18.2.3 REFERENCE
DISTRIBUTION 642 18.2.4 PASSIVE DEVICES 644 18.2.5 INTERCONNECTS 653
18.3 SUBSTRATE COUPLING 660 INDEX 677
|
| adam_txt |
DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS BEHZAD RAZAVI PROFESSOR OF
ELECTRICAL ENGINEERING UNIVERSITY OF CALIFORNIA, LOS ANGELES H BOSTON
BURR RIDGE, IL DUBUQUE, IA MADISON, WI NEW YORK SAN FRANCISCO ST. LOUIS
BANGKOK BOGOTA CARACAS KUALA LUMPUR LISBON LONDON MADRID MEXICO CITY
MILAN MONTREAL NEW DELHI SANTIAGO SEOUL SINGAPORE SYDNEY TAIPEI TORONTO
CONTENTS ABOUT THE AUTHOR VII PREFACE IX ACKNOWLEDGMENTS XI 1
INTRODUCTION TO ANALOG DESIGN 1 1.1 WHY ANALOG? 1 1.2 WHY INTEGRATED? 6
1.3 WHY CMOS? 6 1.4 WHY THIS BOOK? 7 1.5 GENERAL CONCEPTS 7 1.5.1 LEVELS
OF ABSTRACTION 7 1.5.2 ROBUST ANALOG DESIGN 7 2 BASIC MOS DEVICE PHYSICS
9 2.1 GENERAL CONSIDERATIONS 10 2.1.1 MOSFET AS A SWITCH 10 2.1.2 MOSFET
STRUCTURE 10 2.1.3 MOS SYMBOLS 12 2.2 MOS I/V CHARACTERISTICS 13 2.2.1
THRESHOLD VOLTAGE 13 2.2.2 DERIVATION OF I/V CHARACTERISTICS 15 2.3
SECOND-ORDER EFFECTS 23 2.4 MOS DEVICE MODELS 28 2.4.1 MOS DEVICE LAYOUT
28 2.4.2 MOS DEVICE CAPACITANCES 29 2.4.3 MOS SMALL-SIGNAL MODEL 33
2.4.4 MOS SPICE MODEIS 36 2.4.5 NMOS VERSUS PMOS DEVICES 37 2.4.6
LONG-CHANNEL VERSUS SHORT-CHANNEL DEVICES 38 XV XVI CONTENTS 3
SINGLE-STAGE AMPLIFIERS 47 3.1 BASIC CONCEPTS 47 3.2 COMMON-SOURCE STAGE
48 3.2.1 COMMON-SOURCE STAGE WITH RESISTIVE LOAD 48 3.2.2 CS STAGE WITH
DIODE-CONNECTED LOAD 53 3.2.3 CS STAGE WITH CURRENT-SOURCE LOAD 58 3.2.4
CS STAGE WITH TRIODE LOAD 59 3.2.5 CS STAGE WITH SOURCE DEGENERATION 60
3.3 SOURCE FOLLOWER 67 3.4 COMMON-GATE STAGE 76 3.5 CASCODE STAGE 83
3.5.1 FOLDED CASCODE 90 3.6 CHOICE OF DEVICE MODELS 92 4 DIFFERENTIAL
AMPLIFIERS 100 4.1 SINGLE-ENDED AND DIFFERENTIAL OPERATION 100 4.2 BASIC
DIFFERENTIAL PAIR 103 4.2.1 QUALITATIVE ANALYSIS 104 4.2.2 QUANTITATIVE
ANALYSIS 107 4.3 COMMON-MODE RESPONSE 118 4.4 DIFFERENTIAL PAIR WITH MOS
LOADS 124 4.5 GILBERT CELL 126 5 PASSIVE AND ACTIVE CURRENT MIRRORS 135
5.1 BASIC CURRENT MIRRORS 135 5.2 CASCODE CURRENT MIRRORS 139 5.3 ACTIVE
CURRENT MIRRORS 145 5.3.1 LARGE-SIGNAL ANALYSIS 149 5.3.2 SMALL-SIGNAL
ANALYSIS 151 5.3.3 COMMON-MODE PROPERTIES 154 6 FREQUENCY RESPONSE OF
AMPLIFIERS 166 6.1 GENERAL CONSIDERATIONS 166 6.1.1 MILLER EFFECT 166
6.1.2 ASSOCIATION OF POLES WITH NODES 169 6.2 COMMON-SOURCE STAGE 172
6.3 SOURCE FOLLOWERS 178 6.4 COMMON-GATE STAGE 183 6.5 CASCODE STAGE 185
6.6 DIFFERENTIAL PAIR 187 APPENDIX A: DUAL OF MILLER'S THEOREM 193 XVII
7 NOISE 201 7.1 STATISTICAL CHARACTERISTICS OF NOISE 201 7.1.1 NOISE
SPECTRUM 203 7.1.2 AMPLITUDE DISTRIBUTION 206 7.1.3 CORRELATED AND
UNCORRELATED SOURCES 207 7.2 TYPES OF NOISE 209 7.2.1 THERMAL NOISE 209
7.2.2 FLICKER NOISE 215 7.3 REPRESENTATION OF NOISE IN CIRCUITS 218 7.4
NOISE IN SINGLE-STAGE AMPLIFIERS 224 7.4.1 COMMON-SOURCE STAGE 225 7.4.2
COMMON-GATE STAGE 228 7.4.3 SOURCE FOLLOWERS 231 7.4.4 CASCODE STAGE 232
7.5 NOISE IN DIFFERENTIAL PAIRS 233 7.6 NOISE BANDWIDTH 239 8 FEEDBACK
246 8.1 GENERAL CONSIDERATIONS 246 8.1.1 PROPERTIES OF FEEDBACK CIRCUITS
247 8.1.2 TYPES OF AMPLIFIERS 254 8.2 FEEDBACK TOPOLOGIES 258 8.2.1
VOLTAGE-VOLTAGE FEEDBACK 258 8.2.2 CURRENT-VOLTAGE FEEDBACK 263 8.2.3
VOLTAGE-CURRENT FEEDBACK 266 8.2.4 CURRENT-CURRENT FEEDBACK 269 8.3
EFFECT OF LOADING 270 8.3.1 TWO-PORT NETWORK MODELS 270 8.3.2 LOADING IN
VOLTAGE-VOLTAGE FEEDBACK 272 8.3.3 LOADING IN CURRENT-VOLTAGE FEEDBACK
275 8.3.4 LOADING IN VOLTAGE-CURRENT FEEDBACK 278 8.3.5 LOADING IN
CURRENT-CURRENT FEEDBACK 281 8.3.6 SUMMARY OF LOADING EFFECTS 283 8.4
EFFECT OF FEEDBACK ON NOISE 284 9 OPERATIONAL AMPLIFIERS 291 9.1 GENERAL
CONSIDERATIONS 291 9.1.1 PERFORMANCE PARAMETERS '. 291 9.2 ONE-STAGE OP
AMPS 296 9.3 TWO-STAGE OP AMPS 307 9.4 GAIN BOOSTING 309 9.5 COMPARISON
313 9.6 COMMON-MODE FEEDBACK 314 CONTENTS 9.7 INPUT RANGE LIMITATIONS
325 9.8 SLEW RATE 326 9.9 POWER SUPPLY REJECTION 334 9.10 NOISE IN OP
AMPS 336 10 STABILITY AND FREQUENCY COMPENSATION 345 10.1 GENERAL
CONSIDERATIONS 345 10.2 MULTIPOLE SYSTEMS 349 10.3 PHASE MARGIN 351
10.4 FREQUENCY COMPENSATION 355 10.5 COMPENSATION OF TWO-STAGE OP AMPS
361 10.5.1 SLEWING IN TWO-STAGE OP AMPS 368 10.6 OTHER COMPENSATION
TECHNIQUES 369 11 BANDGAP REFERENCES 377 11.1 GENERAL CONSIDERATIONS 377
11.2 SUPPLY-INDEPENDENT BIASING 377 11.3 TEMPERATURE-INDEPENDENT
REFERENCES 381 11.3.1 NEGATIVE-TC VOLTAGE 381 11.3.2 POSITIVE-TC VOLTAGE
382 11.3.3 BANDGAP REFERENCE 384 11.4 PTAT CURRENT GENERATION 390 11.5
CONSTANT-G M BIASING 392 11.6 SPEED AND NOISE ISSUES 393 11.7 CASE STUDY
397 12 INTRODUCTION TO SWITCHED-CAPACITOR CIRCUITS 405 12.1 GENERAL
CONSIDERATIONS 405 12.2 SAMPLING SWITCHES 410 12.2.1 MOSFETS AS SWITCHES
410 12.2.2 SPEED CONSIDERATIONS 414 12.2.3 PRECISION CONSIDERATIONS 417
12.2.4 CHARGE INJECTION CANCELLATION 421 12.3 SWITCHED-CAPACITOR
AMPLIFIERS 423 12.3.1 UNITY-GAIN SAMPLER/BUFFER 424 12.3.2 NONINVERTING
AMPLIFIER 432 12.3.3 PRECISION MULTIPLY-BY-TWO CIRCUIT 438 12.4
SWITCHED-CAPACITOR INTEGRATOR 439 12.5 SWITCHED-CAPACITOR COMMON-MODE
FEEDBACK 442 13 NONLINEARITY AND MISMATCH 448 13.1 NONLINEARITY 448
13.1.1 GENERAL CONSIDERATIONS 448 XIX 13.1.2 NONLINEARITY OF
DIFFERENTIAL CIRCUITS 452 13.1.3 EFFECT OF NEGATIVE FEEDBACK ON
NONLINEARITY 454 13.1.4 CAPACITOR NONLINEARITY 457 13.1.5 LINEARIZATION
TECHNIQUES 458 13.2 MISMATCH 463 13.2.1 OFFSET CANCELLATION TECHNIQUES
471 13.2.2 REDUCTION OF NOISE BY OFFSET CANCELLATION 476 13.2.3
ALTERNATIVE DEFINITION OF CMRR 478 14 OSCILLATORS 482 14.1 GENERAL
CONSIDERATIONS 482 14.2 RING OSCILLATORS 484 14.3 LC OSCILLATORS 495
14.3.1 CROSSED-COUPLED OSCILLATOR 499 14.3.2 COLPITTS OSCILLATOR 502
14.3.3 ONE-PORT OSCILLATORS 505 14.4 VOLTAGE-CONTROLLED OSCILLATORS 510
14.4.1 TUNING IN RING OSCILLATORS 512 14.4.2 TUNING IN LC OSCILLATORS
521 14.5 MATHEMATICAL MODEL OF VCOS 525 15 PHASE-LOCKED LOOPS 532 15.1
SIMPLE PLL 532 15.1.1 PHASE DETECTOR 532 15.1.2 BASIC PLL TOPOLOGY 533
15.1.3 DYNAMICS OF SIMPLE PLL 542 15.2 CHARGE-PUMP PLLS 549 15.2.1
PROBLEM OF LOCK ACQUISITION 549 15.2.2 PHASE/FREQUENCY DETECTOR AND
CHARGE PUMP 550 15.2.3 BASIC CHARGE-PUMP PLL 556 15.3 NONIDEAL EFFECTS
IN PLLS 562 15.3.1 PFD/CP NONIDEALITIES 562 15.3.2 JITTER IN PLLS 567
15.4 DELAY-LOCKED LOOPS 569 15.5 APPLICATIONS 572 15.5.1 FREQUENCY
MULTIPLICATION AND SYNTHESIS 572 15.5.2 SKEW REDUCTION 574 15.5.3 JITTER
REDUCTION 576 16 SHORT-CHANNEL EFFECTS AND DEVICE MODELS 579 16.1
SCALING THEORY 579 16.2 SHORT-CHANNEL EFFECTS 583 CONTENTS 16.2.1
THRESHOLD VOLTAGE VARIATION 583 16.2.2 MOBILITY DEGRADATION WITH
VERTICAL FIELD 585 16.2.3 VELOCITY SATURATION 587 16.2.4 HOT CARRIER
EFFECTS 589 16.2.5 OUTPUT IMPEDANCE VARIATION WITH DRAIN-SOURCE VOLTAGE
589 16.3 MOS DEVICE MODELS 591 16.3.1 LEVEL 1 MODEL 592 16-3.2 LEVEL 2
MODEL 593 16.3.3 LEVEL 3 MODEL 595 16.3.4 BSIM SERIES 596 16.3.5 OTHER
MODELS 597 16.3.6 CHARGE AND CAPACITANCE MODELING 598 16.3.7 TEMPERATURE
DEPENDENCE 599 16.4 PROCESS CORNERS 599 16.5 ANALOG DESIGN IN A DIGITAL
WORLD 600 17 CMOS PROCESSING TECHNOLOGY 604 17.1 GENERAL CONSIDERATIONS
604 17.2 WAFER PROCESSING 605 17.3 PHOTOLITHOGRAPHY 606 17.4 OXIDATION
608 17.5 ION IMPLANTATION 608 17.6 DEPOSITION AND ETCHING 611 17.7
DEVICE FABRICATION 611 17.7.1 ACTIVE DEVICES 611 17.7.2 PASSIVE DEVICES
616 17.7.3 INTERCONNECTS 624 17.8 LATCH-UP 627 18 LAYOUT AND PACKAGING
631 18.1 GENERAL LAYOUT CONSIDERATIONS 631 18.1.1 DESIGN RULES 632
18.1.2 ANTENNA EFFECT 634 18.2 ANALOG LAYOUT TECHNIQUES 635 18.2.1
MULTIFINGER TRANSISTORS 635 18.2.2 SYMMETRY 637 18.2.3 REFERENCE
DISTRIBUTION 642 18.2.4 PASSIVE DEVICES 644 18.2.5 INTERCONNECTS 653
18.3 SUBSTRATE COUPLING 660 INDEX 677 |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Razavi, Behzad |
| author_facet | Razavi, Behzad |
| author_role | aut |
| author_sort | Razavi, Behzad |
| author_variant | b r br |
| building | Verbundindex |
| bvnumber | BV023272244 |
| classification_rvk | ZN 4960 |
| ctrlnum | (OCoLC)254608067 (DE-599)BVBBV023272244 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | International ed., [Nachdr.] |
| format | Book |
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| id | DE-604.BV023272244 |
| illustrated | Illustrated |
| index_date | 2024-07-02T20:36:21Z |
| indexdate | 2024-07-09T21:14:39Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016457231 |
| oclc_num | 254608067 |
| open_access_boolean | |
| owner | DE-898 DE-BY-UBR |
| owner_facet | DE-898 DE-BY-UBR |
| physical | XX, 684 S. graph. Darst. |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | McGraw-Hill |
| record_format | marc |
| series2 | McGraw-Hill series in electrical and computer engineering |
| spelling | Razavi, Behzad Verfasser aut Design of analog CMOS integrated circuits Behzad Razavi International ed., [Nachdr.] Boston [u.a.] McGraw-Hill 2007 XX, 684 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier McGraw-Hill series in electrical and computer engineering Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf Analogschaltung (DE-588)4122796-7 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 s CMOS (DE-588)4010319-5 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Analogschaltung (DE-588)4122796-7 s Integrierte Schaltung (DE-588)4027242-4 s 1\p DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016457231&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Razavi, Behzad Design of analog CMOS integrated circuits Integrierte Schaltung (DE-588)4027242-4 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd Analogschaltung (DE-588)4122796-7 gnd CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4112519-8 (DE-588)4122796-7 (DE-588)4010319-5 (DE-588)4179389-4 |
| title | Design of analog CMOS integrated circuits |
| title_auth | Design of analog CMOS integrated circuits |
| title_exact_search | Design of analog CMOS integrated circuits |
| title_exact_search_txtP | Design of analog CMOS integrated circuits |
| title_full | Design of analog CMOS integrated circuits Behzad Razavi |
| title_fullStr | Design of analog CMOS integrated circuits Behzad Razavi |
| title_full_unstemmed | Design of analog CMOS integrated circuits Behzad Razavi |
| title_short | Design of analog CMOS integrated circuits |
| title_sort | design of analog cmos integrated circuits |
| topic | Integrierte Schaltung (DE-588)4027242-4 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd Analogschaltung (DE-588)4122796-7 gnd CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Integrierte Schaltung Analoge integrierte Schaltung Analogschaltung CMOS Schaltungsentwurf |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016457231&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT razavibehzad designofanalogcmosintegratedcircuits |