CMOS: circuit design, layout and simulation
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Piscaaway, NJ [u.a.]
IEEE Press [u.a.]
2008
|
| Ausgabe: | rev. 2. ed. |
| Schriftenreihe: | IEEE Press series on microelectronic systems
|
| Schlagworte: | |
| Online-Zugang: | Beschreibung für Leser kostenfrei Inhaltsverzeichnis |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | XXXI, 1038 S. Ill., graph. Darst. |
| ISBN: | 0470229411 9780470229415 |
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| 245 | 1 | 0 | |a CMOS |b circuit design, layout and simulation |c R. Jacob Baker |
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| 264 | 1 | |a Piscaaway, NJ [u.a.] |b IEEE Press [u.a.] |c 2008 | |
| 300 | |a XXXI, 1038 S. |b Ill., graph. Darst. | ||
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| 490 | 0 | |a IEEE Press series on microelectronic systems | |
| 500 | |a Includes bibliographical references and index | ||
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Datensatz im Suchindex
| _version_ | 1804137545995386880 |
|---|---|
| adam_text | IMAGE 1
CMOS
CIRCUIT DESIGN, LAYOUT, AND SIMULATION REVISED SECOND EDITION
R. JACOB BAKER
IEEE PRESS SERIES ON MICROELECTRONIC SYSTEMS STUART K. TEWKSBURY AND JOE
E. BREWER, SERIES EDITORS
IEEE SOLID-STATE CIRCUITS SOCIETY, SPONSOR
IEEE PRESS
I C E N T E N N I AL
1 I C E N T E N N I AL
WILEY-INTERSCIENCE
A JOHN WILEY & SONS, INC., PUBLICATION
IMAGE 2
CONTENTS
PREFACE XXIX
CHAPTER 1 INTRODUCTION TO CMOS DESIGN 1
1.1 THE CMOS IC DESIGN PROCESS 1
1.1.1 FABRICATION 3
LAYOUT AND CROSS-SECTIONAL VIEWS 4
1.2 CMOS BACKGROUND 6
THE CMOS ACRONYM 6
CMOS INVERTER 7
THE FIRST CMOS CIRCUITS 7
ANALOG DESIGN IN CMOS 8
1.3 AN INTRODUCTION TO SPICE 8
GENERATING A NETLIST FILE 8
OPERATING POINT 9
TRANSFER FUNCTION ANALYSIS 10
THE VOLTAGE-CONTROLLED VOLTAGE SOURCE 11
AN IDEAL OP-AMP 12
THE SUBCIRCUIT 13
DC ANALYSIS 13
PLOTTING IV CURVES 14
DUAL LOOP DC ANALYSIS 15
TRANSIENT ANALYSIS 15
VII
IMAGE 3
THE SIN SOURCE 16
AN RC CIRCUIT EXAMPLE 17
ANOTHER RC CIRCUIT EXAMPLE 18
ACANALYSIS 19
DECADES AND OCTAVES 20
DECIBELS 20
PULSE STATEMENT 21
FINITE PULSE RISE TIME 21
STEP RESPONSE 22
DELAY AND RISE TIME IN RC CIRCUITS 22
PIECE-WISE LINEAR (PWL) SOURCE 23
SIMULATING SWITCHES 24
INITIAL CONDITIONS ON A CAPACITOR 24
INITIAL CONDITIONS IN AN INDUCTOR 25
Q OF AN LC TANK 25
FREQUENCY RESPONSE OF AN IDEAL INTEGRATOR 26
UNITY-GAIN FREQUENCY 26
TIME-DOMAIN BEHAVIOR OF THE INTEGRATOR 27
CONVERGENCE 28
SOME COMMON MISTAKES AND HELPFUI TECHNIQUES 29
CHAPTER 2 THE WELL 31
THE SUBSTRATE (THE UNPROCESSED WAFER) 31
A PARASITIC DIODE 31
USING THE N-WELL AS A RESISTOR 32
2.1 PATTERNING 32
2.1.1 PATTERNING THE N-WELL 35
2.2 LAYING OUT THE N-WELL 36
2.2.1 DESIGN RULES FOR THE N-WELL 36
2.3 RESISTANCE CALCULATION 37
LAYOUT OF CORNERS 38
2.3.1 THE N-WELL RESISTOR 38
2.4 THE N-WELL/SUBSTRATE DIODE 39
2.4.1 A BRIEF INTRODUCTION TO PN JUNCTION PHYSICS 39
CARRIER CONCENTRATIONS 40
FERMI ENERGY LEVEL 42
2.4.2 DEPLETION LAYER CAPACITANCE 43
2.4.3 STORAGE OR DIFFUSION CAPACITANCE 45
IMAGE 4
2.4.4 SPICE MODELING 47
2.5 THE RC DELAY THROUGH THE N-WELL 49
RC CIRCUIT REVIEW 50
DISTRIBUTED RC DELAY 50
DISTRIBUTED RC RISE TIME 52
2.6 TWIN WELL PROCESSES 52
DESIGN RULES FOR THE WELL 53
SEM VIEWS OF WELLS 55
CHAPTER 3 THE METAL LAYERS 59
3.1 THE BONDING PAED 59
3.1.1 LAYING OUT THE PAED I 60
CAPACITANCE OF METAL-TO-SUBSTRATE 60
PASSIVATION 62
AN IMPORTANT NOTE 62
3.2 DESIGN AND LAYOUT USING THE METAL LAYERS 63
3.2.1 METALL AND VIA1 63
AN EXAMPLE LAYOUT 63
3.2.2 PARASITICS ASSOCIATED WITH THE METAL LAYERS 64
INTRINSIC PROPAGATION DELAY 65
3.2.3 CURRENT-CARRYING LIMITATIONS 68
3.2.4 DESIGN RULES FOR THE METAL LAYERS 69
LAYOUT OF TWO SHAPES OR A SINGLE SHAPE 69
A LAYOUT TRICK FOR THE METAL LAYERS 69
3.2.5 CONTACT RESISTANCE 70
3.3 CROSSTALK AND GROUND BOUNCE 71
3.3.1 CROSSTALK 71
3.3.2 GROUND BOUNCE 72
DC PROBLEMS 72
AC PROBLEMS 72
A FINAL COMMENT 74
3.4 LAYOUT EXAMPLES 75
3.4.1 LAYING OUT THE PAED II 75
3.4.2 LAYING OUT METAL TEST STRUCTURES 78
SEM VIEW OF METAL 79
CHAPTER 4 THE ACTIVE AND POLY LAYERS 83
4.1 LAYOUT USING THE ACTIVE AND POLY LAYERS 83
THE ACTIVE LAYER 83
IMAGE 5
X
CONTENTS
THE P- AND N-SELECT LAYERS 84
THE POLY LAYER 86
SELF-ALIGNED GATE 86
THE POLY WIRE 88
SILICIDE BLOCK 89
4.1.1 PROCESS FLOW 89
DAMASCENE PROCESS STEPS 90
4.2 CONNECTING WIRES TO POLY AND ACTIVE 92
CONNECTING THE P-SUBSTRATE TO GROUND 93
LAYOUT OF AN N-WELL RESISTOR 94
LAYOUT OF AN NMOS DEVICE 95
LAYOUT OF A PMOS DEVICE 96
A COMMENT CONCERNING MOSFET SYMBOLS 96
STANDARD CELL FRAME 97
DESIGN RULES 98
4.3 ELECTROSTATIC DISCHARGE (ESD) PROTECTION 100
LAYOUT OF THE DIODES 100
CHAPTER 5 RESISTORS, CAPACITORS, MOSFETS 105
5.1 RESISTORS 105
TEMPERATURE COEFFICIENT (TEMP CO) 105
POLARITY OF THE TEMP CO 106
VOLTAGE COEFFICIENT 107
USING UNIT ELEMENTS 109
GUARD RINGS 110
INTERDIGITATED LAYOUT 110
COMMON-CENTROID LAYOUT 111
DUMMY ELEMENTS 113
5.2 CAPACITORS 113
LAYOUT OF THE POLY-POLY CAPACITOR 114
PARASITICS 115
TEMPERATURE COEFFICIENT (TEMP CO) 116
VOLTAGE COEFFICIENT 116
5.3 MOSFETS 116
LATERAL DIFFUSION 116
OXIDE ENCROACHMENT 116
SOURCE/DRAIN DEPLETION CAPACITANCE 117
SOURCE/DRAIN PARASITIC RESISTANCE 118
IMAGE 6
LAYOUT OF LONG-LENGTH MOSFETS 120
LAYOUT OF LARGE-WIDTH MOSFETS 121
A QUALITATIVE DESCRIPTION OF MOSFET CAPACITANCES 123
5.4 LAYOUT EXAMPLES 125
METAL CAPACITORS 125
POLYSILICON RESISTORS 127
CHAPTER 6 MOSFET OPERATION 131
6.1 MOSFET CAPACITANCE OVERVIEW/REVIEW 132
CASE I: ACCUMULATION 132
CASE II: DEPLETION 133
CASE III: STRONG INVERSION 133
SUMMARY 135
6.2 THE THRESHOLD VOLTAGE 135
CONTACT POTENTIALS 137
THRESHOLD VOLTAGE ADJUST 140
6.3 IV CHARACTERISTICS OF MOSFETS 140
6.3.1 MOSFET OPERATION IN THE TRIODE REGION 141
6.3.2 THE SATURATION REGION 143
CGS CALCULATION IN THE SATURATION REGION 145
6.4 SPICE MODELING OF THE MOSFET 145
LEVEL 1 MODEL PARAMETERS RELATED TO V THN 145
LONG-CHANNEL MOSFET MODELS 146
LEVEL 1 MODEL PARAMETERS RELATED TO 146
TRANSCONDUCTANCE
SPICE MODELING OF THE SOURCE AND DRAIN IMPLANTS 147
SUMMARY 147
6.4.1 SOME SPICE SIMULATION EXAMPLES 148
THRESHOLD VOLTAGE AND BODY EFFECT 148
6.4.2 THE SUBTHRESHOLD CURRENT 149
6.5 SHORT-CHANNEL MOSFETS 151
LIGHTLY DOPED DRAIN (LDD) 151
6.5.1 MOSFET SCALING 152
6.5.2 SHORT-CHANNEL EFFECTS 153
HOTCARRIERS 153
OXIDE BREAKDOWN 154
DRAIN-INDUCED BARRIER LOWERING 154
SUBSTRATE CURRENT-INDUCED BODY EFFECT 154
IMAGE 7
GATE TUNNEL CURRENT
6.5.3 SPICE MODELS FOR OUR SHORT-CHANNEL CMOS PROCESS
BSIM4 MODEL LISTING (NMOS)
BSIM4 MODEL LISTING (PMOS)
SIMULATION RESULTS
C H A P T ER 7 C M OS FABRICATION BY JEFF JESSING
7. 1 CMOS UNIT PROCESSES
7.1.1 WAFER MANUFACTURE
METALLURGICAL GRADE SILICON (MGS)
ELECTRONIC GRADE SILICON (EGS)
CZOCHRALSKI (CZ) GROWTH AND WAFER FORMATION
7.1.2 THERMAL OXIDATION
7.1.3 DOPING PROCESSES
ION IMPLANTATION
SOLID STATE DIFFUSION
7.1.4 PHOTOLITHOGRAPHY
RESOLUTION
DEPTH OF FOCUS
ALIGNING MASKS
7.1.5 THIN FILM REMOVAL
THIN FILM ETCHING
WET ETCHING
DRY ETCHING
CHEMICAL MECHANICAL POLISHING
7.1.6 THIN FILM DEPOSITION
PHYSICAL VAPOR DEPOSITION (PVD)
CHEMICAL VAPOR DEPOSITON (CVD)
7.2 CMOS PROCESS INTEGRATION
FEOL
BEOL
CMOS PROCESS DESCRIPTION
7.2.1 FRONTEND-OF-THE-LINE INTEGRATION
SHALLOW TRENCH ISOLATION MODULE
TWIN TUB MODULE
GATE MODULE
SOURCE/DRAIN MODULE
154
154
154
156
157
161
161 161
162
162
162
163
165
165
166
167
168
168
170
170
170
171
171
173
173
175
176
177
177
177
178
180
181
187
190
193
IMAGE 8
7.2.2 BACKEND-OF-THE-LINE INTEGRATION 199
SELF-ALIGNED SILICIDE (SALICIDE) MODULE 199
PRE-METAL DIELECTRIC 200
CONTACT MODULE 202
METALLIZATION 1 203
INTRA-METAL DIELECTRIC 1 DEPOSITION 205
VIA 1 MODULE 205
METALLIZATION 2 207
ADDITIONAL METAL/DIELETRIC LAYERS 208
FINAL PASSIVATION 208
7.3 BACKEND PROCESSES 209
WAFER PROBE 209
DIE SEPARATION 211
PACKAGING 211
FINAL TEST AND BURN-IN 211
7.4 SUMMARY 211
CHAPTER 8 ELECTRICAL NOISE: AN OVERVIEW 213
8.1 SIGNALS 213
8.1.1 POWER AND ENERGY 213
COMMENTS 215
8.1.2 POWER SPECTRAL DENSITY 215
SPECTRUM ANALYZERS 216
8.2 CIRCUIT NOISE 219
8.2.1 CAICULATING AND MODELING CIRCUIT NOISE 219
INPUT-REFERRED NOISE I 220
NOISE EQUIVALENT BANDWIDTH 220
INPUT-REFERRED NOISE IN CASCADED AMPLIFIERS 223
CAICULATING V ONOISERMS OM A SPECTRUM: A SUMMARY 224
8.2.2 THERMAL NOISE 225
8.2.3 SIGNAL-TO-NOISE RATIO 230
INPUT-REFERRED NOISE II 231
NOISE FIGURE 233
AN IMPORTANT LIMITATION OF THE NOISE FIGURE 233
OPTIMUM SOURCE RESISTANCE 236
SIMULATING NOISELESS RESISTORS 236
NOISE TEMPERATURE 239
AVERAGING WHITE NOISE 240
IMAGE 9
XIV
CONTENTS
8.2.4 SHOT NOISE 242
8.2.5 FLICKER NOISE 244
8.2.6 OTHER NOISE SOURCES 252
BURST (POPCORN) NOISE 252
EXCESS NOISE (FLICKER NOISE) 253
AVALANCHE NOISE 253
8.3 DISCUSSION 254
8.3.1 CORRELATION 254
CORRELATION OF INPUT-REFERRED NOISE SOURCES 256
COMPLEX INPUT IMPEDANCE 256
8.3.2 NOISE AND FEEDBACK 259
OP-AMP NOISE MODELING 259
8.3.3 SOME FINAL NOTES CONCERNING NOTATION 262
CHAPTER 9 MODELS FOR ANALOG DESIGN 269
9.1 LONG-CHANNEL MOSFETS 269
9.1.1 THE SQUARE-LAW EQUATIONS 271
PMOS SQUARE-LAW EQUATIONS 272
QUALITATIVE DISCUSSION 272
THRESHOLD VOLTAGE AND BODY EFFECT 276
QUALITATIVE DISCUSSION 276
THE TRIODE REGION 278
THE CUTOFF AND SUBTHRESHOLD REGIONS 278
9.1.2 SMALL SIGNAL MODELS 279
TRANSCONDUCTANCE 280
AC ANALYSIS 285
TRANSIENT ANALYSIS 286
BODY EFFECT TRANSCONDUCTANCE, G MB 287
OUTPUT RESISTANCE 288
MOSFET TRANSITION FREQUENCY, F T 290
GENERAL DEVICE SIZES FOR ANALOG DESIGN 291
SUBTHRESHOLD G M AND V THN 292
9.1.3 TEMPERATURE EFFECTS 293
THRESHOLD VARIATION AND TEMPERATURE 293
MOBILITY VARIATION WITH TEMPERATURE 295
DRAIN CURRENT CHANGE WITH TEMPERATURE 295
9.2 SHORT-CHANNEL MOSFETS 297
9.2.1 GENERAL DESIGN (A STARTING POINT) 297
IMAGE 10
OUTPUT RESISTANCE 298
FORWARD TRANSCONDUCTANCE 298
TRANSITION FREQUENCY 299
9.2.2 SPECIFIC DESIGN (A DISCUSSION) 300
9.3 MOSFET NOISE MODELING 302
DRAIN CURRENT NOISE MODEL 302
CHAPTER 10 MODELS FOR DIGITAL DESIGN 311
MILLER CAPACITANCE 311
10.1 THE DIGITAL MOSFET MODEL 312
EFFECTIVE SWITCHING RESISTANCE 312
SHORT-CHANNEL MOSFET EFFECTIVE SWITCHING 314
RESISTANCE
10.1.1 CAPACITIVE EFFECTS 315
10.1.2 PROCESS CHARACTERISTIC TIME CONSTANT 316
10.1.3 DELAY AND TRANSITION TIMES 317
10.1.4 GENERAL DIGITAL DESIGN 320
10.2 THE MOSFET PASS GATE 321
THE PMOS PASS GATE 322
10.2.1 DELAY THROUGH A PASS GATE 323
THE TRANSMISSION GATE (THE TG) 324
10.2.2 DELAY THROUGH SERIES-CONNECTED PGS 325
10.3 A FINAL COMMENT CONCERNING MEASUREMENTS 326
CHAPTER 11 THE INVERTER 331
11.1 DC CHARACTERISTICS 331
NOISE MARGINS 333
INVERTER SWITCHING POINT 334
IDEAL INVERTER VTC AND NOISE MARGINS 334
11.2 SWITCHING CHARACTERISTICS 337
THE RING OSCILLATOR 339
DYNAMIC POWER DISSIPATION 339
11.3 LAYOUT OF THE INVERTER 341
LATCH-UP 341
11.4 SIZING FOR LARGE CAPACITIVE LOADS 344
BUFFER TOPOLOGY 344
DISTRIBUTED DRIVERS 347
DRIVING LONG LINES 348
11.5 OTHER INVERTER CONFIGURATIONS 349
IMAGE 11
XVI
CONTENTS
NMOS-ONLY OUTPUT DRIVERS 350
INVERTERS WITH TRI-STATE OUTPUTS 351
ADDITIONAL EXAMPLES 351
CHAPTER 12 STATIC LOGIC GATES 353
12.1 DC CHARACTERISTICS OF THE NAND AND NOR GATES 353
12.1.1 DC CHARACTERISTICS OF THE NAND GATE 353
12.1.2 DC CHARACTERISTICS OF THE NOR GATE 356
A PRACTICAL NOTE CONCERNING V SP AND PASS GATES 357
12.2 LAYOUT OFTHE NAND AND NOR GATES 358
12.3 SWITCHING CHARACTERISTICS 358
PARALLEL CONNECTION OF MOSFETS 358
SERIES CONNECTION OF MOSFETS 359
12.3.1 NAND GATE 360
QUICK ESTIMATE OF DELAYS 362
12.3.2 NUMBER OF INPUTS 363
12.4 COMPLEX CMOS LOGIC GATES 364
CASCODE VOLTAGE SWITCH LOGIC 369
DIFFERENTIAL SPLIT-LEVEL LOGIC 370
TRI-STATE OUTPUTS 370
ADDITIONAL EXAMPLES 370
CHAPTER 13 CLOCKED CIRCUITS 375
13.1 THE CMOS TG 375
SERIES CONNECTION OF TGS 377
13.2 APPLICATIONS OF THE TRANSMISSION GATE 378
PATH SELECTOR 378
STATIC CIRCUITS 379
13.3 LATCHES AND FLIP-FLOPS 380
BASIC LATCHES 380
AN ARBITER 383
FLIP-FLOPS AND FLOW-THROUGH LATCHES 383
AN EDGE-TRIGGERED D-FF 386
FLIP-FLOP TIMING 388
13.4 EXAMPLES 389
CHAPTER 14 DYNAMIC LOGIC GATES 397
14.1 FUNDAMENTALS OF DYNAMIC LOGIC 397
14.1.1 CHARGE LEAKAGE 398
14.1.2 SIMULATING DYNAMIC CIRCUITS 401
IMAGE 12
14.1.3 NONOVERLAPPING CLOCK GENERATION 401
14.1.4 CMOS TG IN DYNAMIC CIRCUITS 402
14.2 CLOCKED CMOS LOGIC 403
CLOCKED CMOS LATCH 403
AN IMPORTANT NOTE 403
PE LOGIC 404
DOMINO LOGIC 405
NP LOGIC (ZIPPER LOGIC) 407
PIPELINING 407
CHAPTER 15 VLSI LAYOUT EXAMPLES 411
15.1 CHIP LAYOUT 412
REGULARITY 412
STANDARD CELL EXAMPLES 413
POWER AND GROUND CONSIDERATIONS 417
AN ADDER EXAMPLE 419
A4-TO-1 MUX/DEMUX 422
15.2 LAYOUT STEPS BY DEAN MORIARTY 422
PLANNING AND STICK DIAGRAMS 422
DEVICE PLACEMENT 424
POLISH 427
STANDARD CELLS VERSUS FULL-CUSTOM LAYOUT 427
CHAPTER 16 MEMORY CIRCUITS 433
16.1 ARRAY ARCHITECTURES 434
16.1.1 SENSING BASICS 435
NMOS SENSE AMPLIFIER (NSA) 435
THE OPEN ARRAY ARCHITECTURE 436
PMOS SENSE AMPLIFIER (PSA) 440
REFRESH OPERATION 441
16.1.2 THE FOLDED ARRAY 441
LAYOUT OF THE DRAM MEMORY BIT (MBIT) 443
16.1.3 CHIP ORGANIZATION 447
16.2 PERIPHERAL CIRCUITS 448
16.2.1 SENSE AMPLIFIER DESIGN 448
KICKBACK NOISE AND CLOCK FEEDTHROUGH 449
MEMORY 450
CURRENT DRAW 450
CONTENTION CURRENT (SWITCHING CURRENT) 450
IMAGE 13
REMOVING SENSE AMPLIFIER MEMORY 451
CREATING AN IMBALANCE AND REDUCING KICKBACK NOISE 451
INCREASING THE INPUT RANGE 454
SIMULATION EXAMPLES 454
16.2.2 ROW/COLUMN DECODERS 457
GLOBAL AND LOCAL DECODERS 458
REDUCING DECODER LAYOUT AREA 460
16.2.3 ROWDRIVERS 461
16.3 MEMORY CELLS 463
16.3.1 THE SRAM CELL 463
16.3.2 READ-ONLY MEMORY (ROM) 464
16.3.3 FLOATING GATE MEMORY 466
THE THRESHOLD VOLTAGE 467
ERASABLE PROGRAMMABLE READ-ONLY MEMORY 468
TWO IMPORTANT NOTES 468
FLASH MEMORY 469
CHAPTER 17 SENSING USING AE MODULATION 483
17.1 QUALITATIVE DISCUSSION 484
17.1.1 EXAMPLES OF DSM 484
THE COUNTER 485
CUP SIZE 486
ANOTHER EXAMPLE 486
17.1.2 USING DSM FOR SENSING IN FLASH MEMORY 487
THE BASIC IDEA 487
THE FEEDBACK SIGNAL 492
INCOMPLETE SETTLING 496
17.2 SENSING RESISTIVE MEMORY 497
THE BIT LINE VOLTAGE 497
ADDING AN OFFSET TO THE COMPARATOR 498
SCHEMATIC AND DESIGN VALUES 499
A COUPLE OF COMMENTS 502
17.3 SENSING IN CMOS IMAGERS 504
RESETTING THE PIXEL 504
THE INTENSITY LEVEL 504
SAMPLING THE REFERENCE AND INTENSITY SIGNALS 505
NOISE ISSUES 506
SUBTRACTING V R FROM V S 508
IMAGE 14
SENSING CIRCUIT MISMATCHES 517
CHAPTER 18 SPECIAL PURPOSE CMOS CIRCUITS 523
18.1 THE SCHMITT TRIGGER 523
18.1.1 DESIGN OF THE SCHMITT TRIGGER 524
SWITCHING CHARACTERISTICS 526
18.1.2 APPLICATIONS OF THE SCHMITT TRIGGER 527
18.2 MULTIVIBRATOR CIRCUITS 529
18.2.1 THE MONOSTABLE MULTIVIBRATOR 529
18.2.2 THE ASTABLE MULTIVIBRATOR 530
18.3 INPUT BUFFERS 531
18.3.1 BASIC CIRCUITS 531
SKEW IN LOGIC GATES 533
18.3.2 DIFFERENTIAL CIRCUITS 534
TRANSIENT RESPONSE 535
18.3.3 DC REFERENCE 538
18.3.4 REDUCING BUFFER INPUT RESISTANCE 541
18.4 CHARGE PUMPS (VOLTAGE GENERATORS) 542
NEGATIVE VOLTAGES 543
USING MOSFETS FOR THE CAPACITORS 544
18.4.1 INCREASING THE OUTPUT VOLTAGE 544
18.4.2 GENERATING HIGHER VOLTAGES: THE DICKSON CHARGE 544
PUMP
CLOCK DRIVER WITH A PUMPED OUTPUT VOLTAGE 546
18.4.3 EXAMPLE 546
CHAPTER 19 DIGITAL PHASE-LOCKED LOOPS 551
19.1 THE PHASE DETECTOR 553
19.1.1 THEXOR PHASE DETECTOR 553
19.1.2 THE PHASE FREQUENCY DETECTOR 557
19.2 THE VOLTAGE-CONTROLLED OSCILLATOR 561
19.2.1 THE CURRENT-STARVED VCO 561
LINEARIZING THE VCO S GAIN 564
19.2.2 SOURCE-COUPLED VCOS 565
19.3 THE LOOP FILTER 567
19.3.1 XORDPLL 568
ACTIVE PI LOOP FILTER 573
19.3.2 PFDDPLL 575
TRI-STATE OUTPUT 575
IMAGE 15
XX
CONTENTS
IMPLEMENTING THE PFD IN CMOS 576
PFD WITH A CHARGE PUMP OUTPUT 578
PRACTICAL IMPLEMENTATION OF THE CHARGE PUMP 579
DISCUSSION 581
19.4 SYSTEM CONCERNS 582
19.4.1 CLOCK RECOVERY FROM NRZ DATA 584
THE HOGGE PHASE DETECTOR 588
JITTER 591
19.5 DELAY-LOCKED LOOPS 592
DELAY ELEMENTS 595
PRACTICAL VCO AND VCDL DESIGN 596
19.6 SOME EXAMPLES 596
19.6.1 A 2 GHZ DLL 596
19.6.2 A 1 GBIT/S CLOCK-RECOVERY CIRCUIT 602
CHAPTER 20 CURRENT MIRRORS 613
20.1 THE BASIC CURRENT MIRROR 613
20.1.1 LONG-CHANNEL DESIGN 614
20.1.2 MATCHING CURRENTS IN THE MIRROR 616
THRESHOLD VOLTAGE MISMATCH 616
TRANSCONDUCTANCE PARAMETER MISMATCH 616
DRAIN-TO-SOURCE VOLTAGE AND LAMBDA 617
LAYOUT TECHNIQUES TO IMPROVE MATCHING 617
LAYOUT OF THE MIRROR WITH DIFFERENT WIDTHS 620
20.1.3 BIASING THE CURRENT MIRROR 621
USING A MOSFET-ONLY REFERENCE CIRCUIT 622
SUPPLY INDEPENDENT BIASING 624
20.1.4 SHORT-CHANNEL DESIGN 627
AN IMPORTANT NOTE 630
20.1.5 TEMPERATURE BEHAVIOR 631
RESISTOR-MOSFET REFERENCE CIRCUIT 631
MOSFET-ONLY REFERENCE CIRCUIT 633
TEMPERATURE BEHAVIOR OF THE BETA-MULTIPLIER 634
VOLTAGE REFERENCE USING THE BETA-MULTIPLIER 634
20.1.6 BIASING IN THE SUBTHRESHOLD REGION 635
20.2 CASCODING THE CURRENT MIRROR 636
20.2.1 THE SIMPLE CASCODE 636
DC OPERATION 637
IMAGE 16
CASCODE OUTPUT RESISTANCE 637
20.2.2 LOW-VOLTAGE (WIDE-SWING) CASCODE 639
AN IMPORTANT PRACTICAL NOTE 641
LAYOUT CONCERNS 642
20.2.3 WIDE-SWING, SHORT-CHANNEL DESIGN 642
20.2.4 REGULATED DRAIN CURRENT MIRROR 645
20.3 BIASING CIRCUITS 647
20.3.1 LONG-CHANNEL BIASING CIRCUITS 647
BASIC CASCODE BIASING 648
THE FOLDED-CASCODE STRUCTURE 648
20.3.2 SHORT-CHANNEL BIASING CIRCUITS 650
FLOATING CURRENT SOURCES 651
20.3.3 A FINAL COMMENT 651
CHAPTER 21 AMPLIFIERS 657
21.1 GATE-DRAIN CONNECTED LOADS 657
21.1.1 COMMON-SOURCE (CS) AMPLIFIERS 657
MILLER S THEOREM 660
FREQUENCY RESPONSE 661
THE RIGHT-HAND PLANE ZERO 662
A COMMON-SOURCE CURRENT AMPLIFIER 666
COMMON-SOURCE AMPLIFIER WITH SOURCE DEGENERATION 667
NOISE PERFORMANCE OF THE CS AMPLIFIER WITH 669
GATE-DRAIN LOAD
21.1.2 THE SOURCE FOLLOWER (COMMON-DRAIN AMPLIFIER) 670
21.1.3 COMMON GATE AMPLIFIER 671
21.2 CURRENT SOURCE LOADS 671
21.2.1 COMMON-SOURCE AMPLIFIER 671
CLASS A OPERATION 672
SMALL-SIGNAL GAIN 673
OPEN CIRCUIT GAIN 673
HIGH-IMPEDANCE AND LOW-IMPEDANCE NODES 673
FREQUENCY RESPONSE 674
POLE SPLITTING 676
POLE SPLITTING SUMMARY 679
CANCELING THE RHP ZERO 685
NOISE PERFORMANCE OF THE CS AMPLIFIER WITH CURRENT 686
SOURCE LOAD
21.2.2 THE CASCODE AMPLIFIER 686
IMAGE 17
FREQUENCY RESPONSE 687
CLASS A OPERATION 688
NOISE PERFORMANCE OF THE CASCODE AMPLIFIER 688
OPERATION AS A TRANSIMPEDANCE AMPLIFIER 688
21.2.3 THE COMMON-GATE AMPLIFIER 689
21.2.4 THE SOURCE FOLLOWER (COMMON-DRAIN AMPLIFIER) 690
BODY EFFECT AND GAIN 691
LEVEL SHIFTING 692
INPUT CAPACITANCE 693
NOISE PERFORMANCE OF THE SF AMPLIFIER 694
FREQUENCY BEHAVIOR 694
SF AS AN OUTPUT BUFFER 696
A CLASS AB OUTPUT BUFFER USING SFS 697
21.3 THE PUSH-PULL AMPLIFIER 698
21.3.1 DC OPERATION AND BIASING 699
POWER CONVERSION EFFICIENCY 699
21.3.2 SMALL-SIGNAL ANALYSIS 702
21.3.3 DISTORTION 704
MODELING DISTORTION WITH SPICE 705
CHAPTER 22 DIFFERENTIAL AMPLIFIERS 711
22.1 THE SOURCE-COUPLED PAIR 711
22.1.1 DC OPERATION 711
MAXIMUM AND MINIMUM DIFFERENTIAL INPUT VOLTAGE 712
MAXIMUM AND MINIMUM COMMON-MODE INPUT VOLTAGE 713
CURRENT MIRROR LOAD 715
BIASING FROM THE CURRENT MIRROR LOAD 717
MINIMUM POWER SUPPLY VOLTAGE 717
22.1.2 AC OPERATION 718
AC GAIN WITH A CURRENT MIRROR LOAD 719
22.1.3 COMMON-MODE REJECTION RATIO 721
INPUT-REFERRED OFFSET FROM FINITE CMRR 723
22.1.4 MATCHING CONSIDERATIONS 724
INPUT-REFERRED OFFSET WITH A CURRENT MIRROR LOAD 725
22.1.5 NOISE PERFORMANCE 726
22.1.6 SLEW-RATE LIMITATIONS 727
22.2 THE SOURCE CROSS-COUPLED PAIR 727
OPERATION OF THE DIFF-AMP 728
IMAGE 18
CONTENTS
XXUI
INPUT SIGNAL RANGE 729
22.2.1 CURRENT SOURCE LOAD 731
INPUT SIGNAL RANGE 732
22.3 CASCODE LOADS (THE TELESCOPIC DIFF-AMP) 733
22.4 WIDE-SWING DIFFERENTIAL AMPLIFIERS 736
22.4.1 CURRENT DIFFERENTIAL AMPLIFIER 737
22.4.2 CONSTANT TRANSCONDUCTANCE DIFF-AMP 738
DISCUSSION 740
CHAPTER 23 VOLTAGE REFERENCES 745
23.1 MOSFET-RESISTOR VOLTAGE REFERENCES 746
23.1.1 THE RESISTOR-MOSFET DIVIDER 746
23.1.2 THE MOSFET-ONLY VOLTAGE DIVIDER 749
23.1.3 SELF-BIASED VOLTAGE REFERENCES 750
FORCING THE SAME CURRENT THROUGH EACH SIDE OF THE 751
REFERENCE
AN ALTERNATE TOPOLOGY 756
23.2 PARASITIC DIODE-BASED REFERENCES 757
DIODE BEHAVIOR 758
THE BANDGAP ENERGY OF SILICON 759
LOWER VOLTAGE REFERENCE DESIGN 760
23.2.1 LONG-CHANNEL BGR DESIGN 761
DIODE-REFERENCED SELF-BIASING (CTAT) 761
THERMAL VOLTAGE-REFERENCED SELF-BIASING (PTAT) 762
BANDGAP REFERENCE DESIGN 765
ALTERNATIVE BGR TOPOLOGIES 766
23.2.2 SHORT-CHANNEL BGR DESIGN 768
THE ADDED AMPLIFIER 770
LOWER VOLTAGE OPERATION 770
CHAPTER 24 OPERATIONAL AMPLIFIERS I 773
24.1 THE TWO-STAGE OP-AMP 774
LOW-FREQUENCY, OPEN LOOP GAIN, A 0LDC IIA
INPUT COMMON-MODE RANGE 774
POWER DISSIPATION 775
OUTPUT SWING AND CURRENT SOURCE/SINKING CAPABILITY 775
OFFSETS 775
COMPENSATING THE OP-AMP 776
GAIN AND PHASE MARGINS 781
IMAGE 19
REMOVING THE ZERO 782
COMPENSATION FOR HIGH-SPEED OPERATION 783
SLEW-RATE LIMITATIONS 787
COMMON-MODE REJECTION RATIO (CMRR) 789
POWER SUPPLY REJECTION RATIO (PSRR) 790
INCREASING THE INPUT COMMON-MODE VOLTAGE RANGE 791
ESTIMATING BANDWIDTH IN OP-AMPS CIRCUITS 792
24.2 AN OP-AMP WITH OUTPUT BUFFER 793
COMPENSATING THE OP-AMP 794
24.3 THE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) 796
UNITY-GAIN FREQUENCY, F UN 797
INCREASING THE OTA OUTPUT RESISTANCE 798
AN IMPORTANT NOTE 799
OTA WITH AN OUTPUT BUFFER (AN OP-AMP) 800
THE FOLDED-CASCODE OTA AND OP-AMP 803
24.4 GAIN-ENHANCEMENT 808
BANDWIDTH OF THE ADDED GE AMPLIFIERS 809
COMPENSATING THE ADDED GE AMPLIFIERS 811
24.5 SOME EXAMPLES AND DISCUSSIONS 812
A VOLTAGE REGULATOR 812
BAD OUTPUT STAGE DESIGN 817
THREE-STAGE OP-AMP DESIGN 820
CHAPTER 25 DYNAMIC ANALOG CIRCUITS 829
25.1 THE MOSFET SWITCH 829
CHARGE INJECTION 830
CAPACITIVE FEEDTHROUGH 831
REDUCTION OF CHARGE INJECTION AND CLOCK FEEDTHROUGH 832
KT/C NOISE 833
25.1.1 SAMPLE-AND-HOLD CIRCUITS 834
25.2 FULLY-DIFFERENTIAL CIRCUITS 836
GAIN 836
COMMON-MODE FEEDBACK 837
COUPLED NOISE REJECTION 838
OTHER BENEFITS OF FULLY-DIFFERENTIAL OP-AMPS 838
25.2.1 A FULLY-DIFFERENTIAL SAMPLE-AND-HOLD 838
CONNECTING THE INPUTS TO THE BOTTOM (POLYL) PLATE 840
BOTTOM PLATE SAMPLING 841
IMAGE 20
SPICE SIMULATION 841
25.3 SWITCHED-CAPACITOR CIRCUITS 843
25.3.1 SWITCHED-CAPACITOR INTEGRATOR 845
PARASITIC INSENSITIVE 846
OTHER INTEGRATOR CONFIGURATIONS 846
EXACT FREQUENCY RESPONSE OF A SWITCHED-CAPACITOR 849
INTEGRATOR
CAPACITOR LAYOUT 851
OP-AMP SETTLING TIME 852
25.4 CIRCUITS 853
REDUCING OFFSET VOLTAGE OF AN OP-AMP 853
DYNAMIC COMPARATOR 854
DYNAMIC CURRENT MIRRORS 856
DYNAMIC AMPLIFIERS 858
CHAPTER 26 OPERATIONAL AMPLIFIERS II 863
26.1 BIASING FOR POWER AND SPEED 863
26.1.1 DEVICE CHARACTERISTICS 864
26.1.2 BIASING CIRCUIT 865
LAYOUT OF DIFFERENTIAL OP-AMPS 865
SELF-BIASED REFERENCE 866
26.2 BASIC CONCEPTS 867
MODELING OFFSET 867
A DIFF-AMP 867
A SINGLE BIAS INPUT DIFF-AMP 868
THE DIFF-AMP S TAIL CURRENT SOURCE 868
USING A CMFB AMPLIFIER 869
COMPENSATING THE CMFB LOOP 871
EXTENDING THE CMFB AMPLIFIER INPUT RANGE 873
DYNAMIC CMFB 874
26.3 BASIC OP-AMP DESIGN 876
THE DIFFERENTIAL AMPLIFIER 877
ADDING A SECOND STAGE (MAKING AN OP-AMP) 878
STEP RESPONSE 880
ADDING CMFB 881
CMFB AMPLIFIER 882
THE TWO-STAGE OP-AMP WITH CMFB 883
ORIGIN OF THE PROBLEM 884
IMAGE 21
SIMULATION RESULTS 886
USING MOSFETS OPERATING IN THE TRIODE REGION 887
START-UP PROBLEMS 887
LOWERING INPUT CAPACITANCE 887
MAKING THE OP-AMP MORE PRACTICAL 888
INCREASING THE OP-AMP S OPEN-LOOP GAIN 889
OFFSETS 892
OP-AMP OFFSET EFFECTS ON OUTPUTS 893
SINGLE-ENDED TO DIFFERENTIAL CONVERSION 894
CMFB SETTLING TIME 895
CMFB IN THE OUTPUT BUFFER (FIG. 26.43) OR THE 895
DIFF-AMP (FIG. 26.40)?
26.4 OP-AMP DESIGN USING SWITCHED-CAPACITOR CMFB 896
CLOCK SIGNALS 896
SWITCHED-CAPACITOR CMFB 896
THE OP-AMP S FIRST STAGE 898
THE OUTPUT BUFFER 900
AN APPLICATION OF THE OP-AMP 901
SIMULATION RESULTS 902
INCREASING THE WIDTHS OF THE DIFF-PAIR 903
A FINAL NOTE CONCERNING BIASING 903
CHAPTER 27 NONLINEAR ANALOG CIRCUITS 909
27.1 BASIC CMOS COMPARATOR DESIGN 909
PREAMPLIFICATION 910
DECISION CIRCUIT 910
OUTPUT BUFFER 913
27.1.1 CHARACTERIZING THE COMPARATOR 915
COMPARATOR DC PERFORMANCE 915
TRANSIENT RESPONSE 916
PROPAGATION DELAY 918
MINIMUM INPUT SLEW RATE 918
27.1.2 CLOCKED COMPARATORS 918
27.1.3 INPUT BUFFERS REVISITED 920
27.2 ADAPTIVE BIASING 920
27.3 ANALOG MULTIPLIERS 923
27.3.1 THE MULTIPLYING QUAD 924
SIMULATING THE OPERATION OF THE MULTIPLIER 926
IMAGE 22
27.3.2 MULTIPLIER DESIGN USING SQUARING CIRCUITS 928
CHAPTER 28 DATA CONVERTER FUNDAMENTALS 931
28.1 ANALOG VERSUS DISCRETE TIME SIGNALS 931
28.2 CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS 932
28.3 SAMPLE-AND-HOLD (S/H) CHARACTERISTICS 935
SAMPLE MODE 936
HOLD MODE 937
APERTURE ERROR 937
28.4 DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS 938
DIFFERENTIAL NONLINEARITY 941
INTEGRAL NONLINEARITY 943
OFFSET 945
GAIN ERROR 945
LATENCY 945
SIGNAL-TO-NOISE RATIO (SNR) 945
DYNAMIC RANGE 947
28.5 ANALOG-TO-DIGITAL CONVERTER (ADC) SPECIFICATIONS 947
QUANTIZATION ERROR 948
DIFFERENTIAL NONLINEARITY 950
MISSING CODES 951
INTEGRAL NONLINEARITY 951
OFFSET AND GAIN ERROR 953
ALIASING 953
SIGNAL-TO-NOISE RATIO 956
APERTURE ERROR 956
28.6 MIXED-SIGNAL LAYOUT ISSUES 957
FLOORPLANNING 958
POWER SUPPLY AND GROUND ISSUES 958
FULLY DIFFERENTIAL DESIGN 960
GUARD RINGS 960
SHIELDING 961
OTHER INTERCONNECT CONSIDERATIONS 962
CHAPTER 29 DATA CONVERTER ARCHITECTURES 965
29.1 DAC ARCHITECTURES 965
29.1.1 DIGITAL INPUT CODE 965
29.1.2 RESISTOR STRING 966
MISMATCH ERRORS RELATED TO THE RESISTOR-STRING DAC 967
IMAGE 23
INTEGRAL NONLINEARITY OF THE RESISTOR-STRING DAC 969
DIFFERENTIAL NONLINEARITY OF THE WORST-CASE RESISTOR- 970
STRING DAC
29.1.3 R-2R LADDER NETWORKS 971
29.1.4 CURRENT STEERING 973
MISMATCH ERRORS RELATED TO CURRENT-STEERING DACS 976
29.1.5 CHARGE-SCALING DACS 978
LAYOUT CONSIDERATIONS FOR A BINARY-WEIGHTED 980
CAPACITOR ARRAY
THESPLITARRAY 980
29.1.6 CYCLIC DAC 982
29.1.7 PIPELINE DAC 984
29.2 ADC ARCHITECTURES 985
29.2.1 FLASH 985
ACCURACY ISSUES FOR THE FLASH ADC 988
29.2.2 THE TWO-STEP FLASH ADC 990
ACCURACY ISSUES RELATED TO THE TWO-STEP FLASH 992
CONVERTER
ACCURACY ISSUES RELATED TO OPERATIONAL AMPLIFIERS 992
29.2.3 THE PIPELINE ADC 994
ACCURACY ISSUES RELATED TO THE PIPELINE CONVERTER 996
29.2.4 INTEGRATING ADCS 998
SINGLE-SLOPE ARCHITECTURE 998
ACCURACY ISSUES RELATED TO THE SINGLE-SLOPE ADC 1000
DUAL-SLOPE ARCHITECTURE 1000
ACCURACY ISSUES RELATED TO THE DUAL-SLOPE ADC 1002
29.2.5 THE SUCCESSIVE APPROXIMATION ADC 1003
THE CHARGE-REDISTRIBUTION SUCCESSIVE APPROXIMATION 1005 ADC
29.2.6 THE OVERSAMPLING ADC 1007
DIFFERENCES IN NYQUIST RATE AND OVERSAMPIED ADCS 1007
THE FIRST-ORDER AS MODULATOR 1008
THE HIGHER ORDER AE MODULATORS 1010
INDEX 1023
ABOUT THE AUTHOR 1039
|
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IMAGE 1
CMOS
CIRCUIT DESIGN, LAYOUT, AND SIMULATION REVISED SECOND EDITION
R. JACOB BAKER
IEEE PRESS SERIES ON MICROELECTRONIC SYSTEMS STUART K. TEWKSBURY AND JOE
E. BREWER, SERIES EDITORS
IEEE SOLID-STATE CIRCUITS SOCIETY, SPONSOR
IEEE PRESS
I C E N T E N N I AL
1 I C E N T E N N I AL
WILEY-INTERSCIENCE
A JOHN WILEY & SONS, INC., PUBLICATION
IMAGE 2
CONTENTS
PREFACE XXIX
CHAPTER 1 INTRODUCTION TO CMOS DESIGN 1
1.1 THE CMOS IC DESIGN PROCESS 1
1.1.1 FABRICATION 3
LAYOUT AND CROSS-SECTIONAL VIEWS 4
1.2 CMOS BACKGROUND 6
THE CMOS ACRONYM 6
CMOS INVERTER 7
THE FIRST CMOS CIRCUITS 7
ANALOG DESIGN IN CMOS 8
1.3 AN INTRODUCTION TO SPICE 8
GENERATING A NETLIST FILE 8
OPERATING POINT 9
TRANSFER FUNCTION ANALYSIS 10
THE VOLTAGE-CONTROLLED VOLTAGE SOURCE 11
AN IDEAL OP-AMP 12
THE SUBCIRCUIT 13
DC ANALYSIS 13
PLOTTING IV CURVES 14
DUAL LOOP DC ANALYSIS 15
TRANSIENT ANALYSIS 15
VII
IMAGE 3
THE SIN SOURCE 16
AN RC CIRCUIT EXAMPLE 17
ANOTHER RC CIRCUIT EXAMPLE 18
ACANALYSIS 19
DECADES AND OCTAVES 20
DECIBELS 20
PULSE STATEMENT 21
FINITE PULSE RISE TIME 21
STEP RESPONSE 22
DELAY AND RISE TIME IN RC CIRCUITS 22
PIECE-WISE LINEAR (PWL) SOURCE 23
SIMULATING SWITCHES 24
INITIAL CONDITIONS ON A CAPACITOR 24
INITIAL CONDITIONS IN AN INDUCTOR 25
Q OF AN LC TANK 25
FREQUENCY RESPONSE OF AN IDEAL INTEGRATOR 26
UNITY-GAIN FREQUENCY 26
TIME-DOMAIN BEHAVIOR OF THE INTEGRATOR 27
CONVERGENCE 28
SOME COMMON MISTAKES AND HELPFUI TECHNIQUES 29
CHAPTER 2 THE WELL 31
THE SUBSTRATE (THE UNPROCESSED WAFER) 31
A PARASITIC DIODE 31
USING THE N-WELL AS A RESISTOR 32
2.1 PATTERNING 32
2.1.1 PATTERNING THE N-WELL 35
2.2 LAYING OUT THE N-WELL 36
2.2.1 DESIGN RULES FOR THE N-WELL 36
2.3 RESISTANCE CALCULATION 37
LAYOUT OF CORNERS 38
2.3.1 THE N-WELL RESISTOR 38
2.4 THE N-WELL/SUBSTRATE DIODE 39
2.4.1 A BRIEF INTRODUCTION TO PN JUNCTION PHYSICS 39
CARRIER CONCENTRATIONS 40
FERMI ENERGY LEVEL 42
2.4.2 DEPLETION LAYER CAPACITANCE 43
2.4.3 STORAGE OR DIFFUSION CAPACITANCE 45
IMAGE 4
2.4.4 SPICE MODELING 47
2.5 THE RC DELAY THROUGH THE N-WELL 49
RC CIRCUIT REVIEW 50
DISTRIBUTED RC DELAY 50
DISTRIBUTED RC RISE TIME 52
2.6 TWIN WELL PROCESSES 52
DESIGN RULES FOR THE WELL 53
SEM VIEWS OF WELLS 55
CHAPTER 3 THE METAL LAYERS 59
3.1 THE BONDING PAED 59
3.1.1 LAYING OUT THE PAED I 60
CAPACITANCE OF METAL-TO-SUBSTRATE 60
PASSIVATION 62
AN IMPORTANT NOTE 62
3.2 DESIGN AND LAYOUT USING THE METAL LAYERS 63
3.2.1 METALL AND VIA1 63
AN EXAMPLE LAYOUT 63
3.2.2 PARASITICS ASSOCIATED WITH THE METAL LAYERS 64
INTRINSIC PROPAGATION DELAY 65
3.2.3 CURRENT-CARRYING LIMITATIONS 68
3.2.4 DESIGN RULES FOR THE METAL LAYERS 69
LAYOUT OF TWO SHAPES OR A SINGLE SHAPE 69
A LAYOUT TRICK FOR THE METAL LAYERS 69
3.2.5 CONTACT RESISTANCE 70
3.3 CROSSTALK AND GROUND BOUNCE 71
3.3.1 CROSSTALK 71
3.3.2 GROUND BOUNCE 72
DC PROBLEMS 72
AC PROBLEMS 72
A FINAL COMMENT 74
3.4 LAYOUT EXAMPLES 75
3.4.1 LAYING OUT THE PAED II 75
3.4.2 LAYING OUT METAL TEST STRUCTURES 78
SEM VIEW OF METAL 79
CHAPTER 4 THE ACTIVE AND POLY LAYERS 83
4.1 LAYOUT USING THE ACTIVE AND POLY LAYERS 83
THE ACTIVE LAYER 83
IMAGE 5
X
CONTENTS
THE P- AND N-SELECT LAYERS 84
THE POLY LAYER 86
SELF-ALIGNED GATE 86
THE POLY WIRE 88
SILICIDE BLOCK 89
4.1.1 PROCESS FLOW 89
DAMASCENE PROCESS STEPS 90
4.2 CONNECTING WIRES TO POLY AND ACTIVE 92
CONNECTING THE P-SUBSTRATE TO GROUND 93
LAYOUT OF AN N-WELL RESISTOR 94
LAYOUT OF AN NMOS DEVICE 95
LAYOUT OF A PMOS DEVICE 96
A COMMENT CONCERNING MOSFET SYMBOLS 96
STANDARD CELL FRAME 97
DESIGN RULES 98
4.3 ELECTROSTATIC DISCHARGE (ESD) PROTECTION 100
LAYOUT OF THE DIODES 100
CHAPTER 5 RESISTORS, CAPACITORS, MOSFETS 105
5.1 RESISTORS 105
TEMPERATURE COEFFICIENT (TEMP CO) 105
POLARITY OF THE TEMP CO 106
VOLTAGE COEFFICIENT 107
USING UNIT ELEMENTS 109
GUARD RINGS 110
INTERDIGITATED LAYOUT 110
COMMON-CENTROID LAYOUT 111
DUMMY ELEMENTS 113
5.2 CAPACITORS 113
LAYOUT OF THE POLY-POLY CAPACITOR 114
PARASITICS 115
TEMPERATURE COEFFICIENT (TEMP CO) 116
VOLTAGE COEFFICIENT 116
5.3 MOSFETS 116
LATERAL DIFFUSION 116
OXIDE ENCROACHMENT 116
SOURCE/DRAIN DEPLETION CAPACITANCE 117
SOURCE/DRAIN PARASITIC RESISTANCE 118
IMAGE 6
LAYOUT OF LONG-LENGTH MOSFETS 120
LAYOUT OF LARGE-WIDTH MOSFETS 121
A QUALITATIVE DESCRIPTION OF MOSFET CAPACITANCES 123
5.4 LAYOUT EXAMPLES 125
METAL CAPACITORS 125
POLYSILICON RESISTORS 127
CHAPTER 6 MOSFET OPERATION 131
6.1 MOSFET CAPACITANCE OVERVIEW/REVIEW 132
CASE I: ACCUMULATION 132
CASE II: DEPLETION 133
CASE III: STRONG INVERSION 133
SUMMARY 135
6.2 THE THRESHOLD VOLTAGE 135
CONTACT POTENTIALS 137
THRESHOLD VOLTAGE ADJUST 140
6.3 IV CHARACTERISTICS OF MOSFETS 140
6.3.1 MOSFET OPERATION IN THE TRIODE REGION 141
6.3.2 THE SATURATION REGION 143
CGS CALCULATION IN THE SATURATION REGION 145
6.4 SPICE MODELING OF THE MOSFET 145
LEVEL 1 MODEL PARAMETERS RELATED TO V THN 145
LONG-CHANNEL MOSFET MODELS 146
LEVEL 1 MODEL PARAMETERS RELATED TO 146
TRANSCONDUCTANCE
SPICE MODELING OF THE SOURCE AND DRAIN IMPLANTS 147
SUMMARY 147
6.4.1 SOME SPICE SIMULATION EXAMPLES 148
THRESHOLD VOLTAGE AND BODY EFFECT 148
6.4.2 THE SUBTHRESHOLD CURRENT 149
6.5 SHORT-CHANNEL MOSFETS 151
LIGHTLY DOPED DRAIN (LDD) 151
6.5.1 MOSFET SCALING 152
6.5.2 SHORT-CHANNEL EFFECTS 153
HOTCARRIERS 153
OXIDE BREAKDOWN 154
DRAIN-INDUCED BARRIER LOWERING 154
SUBSTRATE CURRENT-INDUCED BODY EFFECT 154
IMAGE 7
GATE TUNNEL CURRENT
6.5.3 SPICE MODELS FOR OUR SHORT-CHANNEL CMOS PROCESS
BSIM4 MODEL LISTING (NMOS)
BSIM4 MODEL LISTING (PMOS)
SIMULATION RESULTS
C H A P T ER 7 C M OS FABRICATION BY JEFF JESSING
7. 1 CMOS UNIT PROCESSES
7.1.1 WAFER MANUFACTURE
METALLURGICAL GRADE SILICON (MGS)
ELECTRONIC GRADE SILICON (EGS)
CZOCHRALSKI (CZ) GROWTH AND WAFER FORMATION
7.1.2 THERMAL OXIDATION
7.1.3 DOPING PROCESSES
ION IMPLANTATION
SOLID STATE DIFFUSION
7.1.4 PHOTOLITHOGRAPHY
RESOLUTION
DEPTH OF FOCUS
ALIGNING MASKS
7.1.5 THIN FILM REMOVAL
THIN FILM ETCHING
WET ETCHING
DRY ETCHING
CHEMICAL MECHANICAL POLISHING
7.1.6 THIN FILM DEPOSITION
PHYSICAL VAPOR DEPOSITION (PVD)
CHEMICAL VAPOR DEPOSITON (CVD)
7.2 CMOS PROCESS INTEGRATION
FEOL
BEOL
CMOS PROCESS DESCRIPTION
7.2.1 FRONTEND-OF-THE-LINE INTEGRATION
SHALLOW TRENCH ISOLATION MODULE
TWIN TUB MODULE
GATE MODULE
SOURCE/DRAIN MODULE
154
154
154
156
157
161
161 161
162
162
162
163
165
165
166
167
168
168
170
170
170
171
171
173
173
175
176
177
177
177
178
180
181
187
190
193
IMAGE 8
7.2.2 BACKEND-OF-THE-LINE INTEGRATION 199
SELF-ALIGNED SILICIDE (SALICIDE) MODULE 199
PRE-METAL DIELECTRIC 200
CONTACT MODULE 202
METALLIZATION 1 203
INTRA-METAL DIELECTRIC 1 DEPOSITION 205
VIA 1 MODULE 205
METALLIZATION 2 207
ADDITIONAL METAL/DIELETRIC LAYERS 208
FINAL PASSIVATION 208
7.3 BACKEND PROCESSES 209
WAFER PROBE 209
DIE SEPARATION 211
PACKAGING 211
FINAL TEST AND BURN-IN 211
7.4 SUMMARY 211
CHAPTER 8 ELECTRICAL NOISE: AN OVERVIEW 213
8.1 SIGNALS 213
8.1.1 POWER AND ENERGY 213
COMMENTS 215
8.1.2 POWER SPECTRAL DENSITY 215
SPECTRUM ANALYZERS 216
8.2 CIRCUIT NOISE 219
8.2.1 CAICULATING AND MODELING CIRCUIT NOISE 219
INPUT-REFERRED NOISE I 220
NOISE EQUIVALENT BANDWIDTH 220
INPUT-REFERRED NOISE IN CASCADED AMPLIFIERS 223
CAICULATING V ONOISERMS OM A SPECTRUM: A SUMMARY 224
8.2.2 THERMAL NOISE 225
8.2.3 SIGNAL-TO-NOISE RATIO 230
INPUT-REFERRED NOISE II 231
NOISE FIGURE 233
AN IMPORTANT LIMITATION OF THE NOISE FIGURE 233
OPTIMUM SOURCE RESISTANCE 236
SIMULATING NOISELESS RESISTORS 236
NOISE TEMPERATURE 239
AVERAGING WHITE NOISE 240
IMAGE 9
XIV
CONTENTS
8.2.4 SHOT NOISE 242
8.2.5 FLICKER NOISE 244
8.2.6 OTHER NOISE SOURCES 252
BURST (POPCORN) NOISE 252
EXCESS NOISE (FLICKER NOISE) 253
AVALANCHE NOISE 253
8.3 DISCUSSION 254
8.3.1 CORRELATION 254
CORRELATION OF INPUT-REFERRED NOISE SOURCES 256
COMPLEX INPUT IMPEDANCE 256
8.3.2 NOISE AND FEEDBACK 259
OP-AMP NOISE MODELING 259
8.3.3 SOME FINAL NOTES CONCERNING NOTATION 262
CHAPTER 9 MODELS FOR ANALOG DESIGN 269
9.1 LONG-CHANNEL MOSFETS 269
9.1.1 THE SQUARE-LAW EQUATIONS 271
PMOS SQUARE-LAW EQUATIONS 272
QUALITATIVE DISCUSSION 272
THRESHOLD VOLTAGE AND BODY EFFECT 276
QUALITATIVE DISCUSSION 276
THE TRIODE REGION 278
THE CUTOFF AND SUBTHRESHOLD REGIONS 278
9.1.2 SMALL SIGNAL MODELS 279
TRANSCONDUCTANCE 280
AC ANALYSIS 285
TRANSIENT ANALYSIS 286
BODY EFFECT TRANSCONDUCTANCE, G MB 287
OUTPUT RESISTANCE 288
MOSFET TRANSITION FREQUENCY, F T 290
GENERAL DEVICE SIZES FOR ANALOG DESIGN 291
SUBTHRESHOLD G M AND V THN 292
9.1.3 TEMPERATURE EFFECTS 293
THRESHOLD VARIATION AND TEMPERATURE 293
MOBILITY VARIATION WITH TEMPERATURE 295
DRAIN CURRENT CHANGE WITH TEMPERATURE 295
9.2 SHORT-CHANNEL MOSFETS 297
9.2.1 GENERAL DESIGN (A STARTING POINT) 297
IMAGE 10
OUTPUT RESISTANCE 298
FORWARD TRANSCONDUCTANCE 298
TRANSITION FREQUENCY 299
9.2.2 SPECIFIC DESIGN (A DISCUSSION) 300
9.3 MOSFET NOISE MODELING 302
DRAIN CURRENT NOISE MODEL 302
CHAPTER 10 MODELS FOR DIGITAL DESIGN 311
MILLER CAPACITANCE 311
10.1 THE DIGITAL MOSFET MODEL 312
EFFECTIVE SWITCHING RESISTANCE 312
SHORT-CHANNEL MOSFET EFFECTIVE SWITCHING 314
RESISTANCE
10.1.1 CAPACITIVE EFFECTS 315
10.1.2 PROCESS CHARACTERISTIC TIME CONSTANT 316
10.1.3 DELAY AND TRANSITION TIMES 317
10.1.4 GENERAL DIGITAL DESIGN 320
10.2 THE MOSFET PASS GATE 321
THE PMOS PASS GATE 322
10.2.1 DELAY THROUGH A PASS GATE 323
THE TRANSMISSION GATE (THE TG) 324
10.2.2 DELAY THROUGH SERIES-CONNECTED PGS 325
10.3 A FINAL COMMENT CONCERNING MEASUREMENTS 326
CHAPTER 11 THE INVERTER 331
11.1 DC CHARACTERISTICS 331
NOISE MARGINS 333
INVERTER SWITCHING POINT 334
IDEAL INVERTER VTC AND NOISE MARGINS 334
11.2 SWITCHING CHARACTERISTICS 337
THE RING OSCILLATOR 339
DYNAMIC POWER DISSIPATION 339
11.3 LAYOUT OF THE INVERTER 341
LATCH-UP 341
11.4 SIZING FOR LARGE CAPACITIVE LOADS 344
BUFFER TOPOLOGY 344
DISTRIBUTED DRIVERS 347
DRIVING LONG LINES 348
11.5 OTHER INVERTER CONFIGURATIONS 349
IMAGE 11
XVI
CONTENTS
NMOS-ONLY OUTPUT DRIVERS 350
INVERTERS WITH TRI-STATE OUTPUTS 351
ADDITIONAL EXAMPLES 351
CHAPTER 12 STATIC LOGIC GATES 353
12.1 DC CHARACTERISTICS OF THE NAND AND NOR GATES 353
12.1.1 DC CHARACTERISTICS OF THE NAND GATE 353
12.1.2 DC CHARACTERISTICS OF THE NOR GATE 356
A PRACTICAL NOTE CONCERNING V SP AND PASS GATES 357
12.2 LAYOUT OFTHE NAND AND NOR GATES 358
12.3 SWITCHING CHARACTERISTICS 358
PARALLEL CONNECTION OF MOSFETS 358
SERIES CONNECTION OF MOSFETS 359
12.3.1 NAND GATE 360
QUICK ESTIMATE OF DELAYS 362
12.3.2 NUMBER OF INPUTS 363
12.4 COMPLEX CMOS LOGIC GATES 364
CASCODE VOLTAGE SWITCH LOGIC 369
DIFFERENTIAL SPLIT-LEVEL LOGIC 370
TRI-STATE OUTPUTS 370
ADDITIONAL EXAMPLES 370
CHAPTER 13 CLOCKED CIRCUITS 375
13.1 THE CMOS TG 375
SERIES CONNECTION OF TGS 377
13.2 APPLICATIONS OF THE TRANSMISSION GATE 378
PATH SELECTOR 378
STATIC CIRCUITS 379
13.3 LATCHES AND FLIP-FLOPS 380
BASIC LATCHES 380
AN ARBITER 383
FLIP-FLOPS AND FLOW-THROUGH LATCHES 383
AN EDGE-TRIGGERED D-FF 386
FLIP-FLOP TIMING 388
13.4 EXAMPLES 389
CHAPTER 14 DYNAMIC LOGIC GATES 397
14.1 FUNDAMENTALS OF DYNAMIC LOGIC 397
14.1.1 CHARGE LEAKAGE 398
14.1.2 SIMULATING DYNAMIC CIRCUITS 401
IMAGE 12
14.1.3 NONOVERLAPPING CLOCK GENERATION 401
14.1.4 CMOS TG IN DYNAMIC CIRCUITS 402
14.2 CLOCKED CMOS LOGIC 403
CLOCKED CMOS LATCH 403
AN IMPORTANT NOTE 403
PE LOGIC 404
DOMINO LOGIC 405
NP LOGIC (ZIPPER LOGIC) 407
PIPELINING 407
CHAPTER 15 VLSI LAYOUT EXAMPLES 411
15.1 CHIP LAYOUT 412
REGULARITY 412
STANDARD CELL EXAMPLES 413
POWER AND GROUND CONSIDERATIONS 417
AN ADDER EXAMPLE 419
A4-TO-1 MUX/DEMUX 422
15.2 LAYOUT STEPS BY DEAN MORIARTY 422
PLANNING AND STICK DIAGRAMS 422
DEVICE PLACEMENT 424
POLISH 427
STANDARD CELLS VERSUS FULL-CUSTOM LAYOUT 427
CHAPTER 16 MEMORY CIRCUITS 433
16.1 ARRAY ARCHITECTURES 434
16.1.1 SENSING BASICS 435
NMOS SENSE AMPLIFIER (NSA) 435
THE OPEN ARRAY ARCHITECTURE 436
PMOS SENSE AMPLIFIER (PSA) 440
REFRESH OPERATION 441
16.1.2 THE FOLDED ARRAY 441
LAYOUT OF THE DRAM MEMORY BIT (MBIT) 443
16.1.3 CHIP ORGANIZATION 447
16.2 PERIPHERAL CIRCUITS 448
16.2.1 SENSE AMPLIFIER DESIGN 448
KICKBACK NOISE AND CLOCK FEEDTHROUGH 449
MEMORY 450
CURRENT DRAW 450
CONTENTION CURRENT (SWITCHING CURRENT) 450
IMAGE 13
REMOVING SENSE AMPLIFIER MEMORY 451
CREATING AN IMBALANCE AND REDUCING KICKBACK NOISE 451
INCREASING THE INPUT RANGE 454
SIMULATION EXAMPLES 454
16.2.2 ROW/COLUMN DECODERS 457
GLOBAL AND LOCAL DECODERS 458
REDUCING DECODER LAYOUT AREA 460
16.2.3 ROWDRIVERS 461
16.3 MEMORY CELLS 463
16.3.1 THE SRAM CELL 463
16.3.2 READ-ONLY MEMORY (ROM) 464
16.3.3 FLOATING GATE MEMORY 466
THE THRESHOLD VOLTAGE 467
ERASABLE PROGRAMMABLE READ-ONLY MEMORY 468
TWO IMPORTANT NOTES 468
FLASH MEMORY 469
CHAPTER 17 SENSING USING AE MODULATION 483
17.1 QUALITATIVE DISCUSSION 484
17.1.1 EXAMPLES OF DSM 484
THE COUNTER 485
CUP SIZE 486
ANOTHER EXAMPLE 486
17.1.2 USING DSM FOR SENSING IN FLASH MEMORY 487
THE BASIC IDEA 487
THE FEEDBACK SIGNAL 492
INCOMPLETE SETTLING 496
17.2 SENSING RESISTIVE MEMORY 497
THE BIT LINE VOLTAGE 497
ADDING AN OFFSET TO THE COMPARATOR 498
SCHEMATIC AND DESIGN VALUES 499
A COUPLE OF COMMENTS 502
17.3 SENSING IN CMOS IMAGERS 504
RESETTING THE PIXEL 504
THE INTENSITY LEVEL 504
SAMPLING THE REFERENCE AND INTENSITY SIGNALS 505
NOISE ISSUES 506
SUBTRACTING V R FROM V S 508
IMAGE 14
SENSING CIRCUIT MISMATCHES 517
CHAPTER 18 SPECIAL PURPOSE CMOS CIRCUITS 523
18.1 THE SCHMITT TRIGGER 523
18.1.1 DESIGN OF THE SCHMITT TRIGGER 524
SWITCHING CHARACTERISTICS 526
18.1.2 APPLICATIONS OF THE SCHMITT TRIGGER 527
18.2 MULTIVIBRATOR CIRCUITS 529
18.2.1 THE MONOSTABLE MULTIVIBRATOR 529
18.2.2 THE ASTABLE MULTIVIBRATOR 530
18.3 INPUT BUFFERS 531
18.3.1 BASIC CIRCUITS 531
SKEW IN LOGIC GATES 533
18.3.2 DIFFERENTIAL CIRCUITS 534
TRANSIENT RESPONSE 535
18.3.3 DC REFERENCE 538
18.3.4 REDUCING BUFFER INPUT RESISTANCE 541
18.4 CHARGE PUMPS (VOLTAGE GENERATORS) 542
NEGATIVE VOLTAGES 543
USING MOSFETS FOR THE CAPACITORS 544
18.4.1 INCREASING THE OUTPUT VOLTAGE 544
18.4.2 GENERATING HIGHER VOLTAGES: THE DICKSON CHARGE 544
PUMP
CLOCK DRIVER WITH A PUMPED OUTPUT VOLTAGE 546
18.4.3 EXAMPLE 546
CHAPTER 19 DIGITAL PHASE-LOCKED LOOPS 551
19.1 THE PHASE DETECTOR 553
19.1.1 THEXOR PHASE DETECTOR 553
19.1.2 THE PHASE FREQUENCY DETECTOR 557
19.2 THE VOLTAGE-CONTROLLED OSCILLATOR 561
19.2.1 THE CURRENT-STARVED VCO 561
LINEARIZING THE VCO'S GAIN 564
19.2.2 SOURCE-COUPLED VCOS 565
19.3 THE LOOP FILTER 567
19.3.1 XORDPLL 568
ACTIVE PI LOOP FILTER 573
19.3.2 PFDDPLL 575
TRI-STATE OUTPUT 575
IMAGE 15
XX
CONTENTS
IMPLEMENTING THE PFD IN CMOS 576
PFD WITH A CHARGE PUMP OUTPUT 578
PRACTICAL IMPLEMENTATION OF THE CHARGE PUMP 579
DISCUSSION 581
19.4 SYSTEM CONCERNS 582
19.4.1 CLOCK RECOVERY FROM NRZ DATA 584
THE HOGGE PHASE DETECTOR 588
JITTER 591
19.5 DELAY-LOCKED LOOPS 592
DELAY ELEMENTS 595
PRACTICAL VCO AND VCDL DESIGN 596
19.6 SOME EXAMPLES 596
19.6.1 A 2 GHZ DLL 596
19.6.2 A 1 GBIT/S CLOCK-RECOVERY CIRCUIT 602
CHAPTER 20 CURRENT MIRRORS 613
20.1 THE BASIC CURRENT MIRROR 613
20.1.1 LONG-CHANNEL DESIGN 614
20.1.2 MATCHING CURRENTS IN THE MIRROR 616
THRESHOLD VOLTAGE MISMATCH 616
TRANSCONDUCTANCE PARAMETER MISMATCH 616
DRAIN-TO-SOURCE VOLTAGE AND LAMBDA 617
LAYOUT TECHNIQUES TO IMPROVE MATCHING 617
LAYOUT OF THE MIRROR WITH DIFFERENT WIDTHS 620
20.1.3 BIASING THE CURRENT MIRROR 621
USING A MOSFET-ONLY REFERENCE CIRCUIT 622
SUPPLY INDEPENDENT BIASING 624
20.1.4 SHORT-CHANNEL DESIGN 627
AN IMPORTANT NOTE 630
20.1.5 TEMPERATURE BEHAVIOR 631
RESISTOR-MOSFET REFERENCE CIRCUIT 631
MOSFET-ONLY REFERENCE CIRCUIT 633
TEMPERATURE BEHAVIOR OF THE BETA-MULTIPLIER 634
VOLTAGE REFERENCE USING THE BETA-MULTIPLIER 634
20.1.6 BIASING IN THE SUBTHRESHOLD REGION 635
20.2 CASCODING THE CURRENT MIRROR 636
20.2.1 THE SIMPLE CASCODE 636
DC OPERATION 637
IMAGE 16
CASCODE OUTPUT RESISTANCE 637
20.2.2 LOW-VOLTAGE (WIDE-SWING) CASCODE 639
AN IMPORTANT PRACTICAL NOTE 641
LAYOUT CONCERNS 642
20.2.3 WIDE-SWING, SHORT-CHANNEL DESIGN 642
20.2.4 REGULATED DRAIN CURRENT MIRROR 645
20.3 BIASING CIRCUITS 647
20.3.1 LONG-CHANNEL BIASING CIRCUITS 647
BASIC CASCODE BIASING 648
THE FOLDED-CASCODE STRUCTURE 648
20.3.2 SHORT-CHANNEL BIASING CIRCUITS 650
FLOATING CURRENT SOURCES 651
20.3.3 A FINAL COMMENT 651
CHAPTER 21 AMPLIFIERS 657
21.1 GATE-DRAIN CONNECTED LOADS 657
21.1.1 COMMON-SOURCE (CS) AMPLIFIERS 657
MILLER'S THEOREM 660
FREQUENCY RESPONSE 661
THE RIGHT-HAND PLANE ZERO 662
A COMMON-SOURCE CURRENT AMPLIFIER 666
COMMON-SOURCE AMPLIFIER WITH SOURCE DEGENERATION 667
NOISE PERFORMANCE OF THE CS AMPLIFIER WITH 669
GATE-DRAIN LOAD
21.1.2 THE SOURCE FOLLOWER (COMMON-DRAIN AMPLIFIER) 670
21.1.3 COMMON GATE AMPLIFIER 671
21.2 CURRENT SOURCE LOADS 671
21.2.1 COMMON-SOURCE AMPLIFIER 671
CLASS A OPERATION 672
SMALL-SIGNAL GAIN 673
OPEN CIRCUIT GAIN 673
HIGH-IMPEDANCE AND LOW-IMPEDANCE NODES 673
FREQUENCY RESPONSE 674
POLE SPLITTING 676
POLE SPLITTING SUMMARY 679
CANCELING THE RHP ZERO 685
NOISE PERFORMANCE OF THE CS AMPLIFIER WITH CURRENT 686
SOURCE LOAD
21.2.2 THE CASCODE AMPLIFIER 686
IMAGE 17
FREQUENCY RESPONSE 687
CLASS A OPERATION 688
NOISE PERFORMANCE OF THE CASCODE AMPLIFIER 688
OPERATION AS A TRANSIMPEDANCE AMPLIFIER 688
21.2.3 THE COMMON-GATE AMPLIFIER 689
21.2.4 THE SOURCE FOLLOWER (COMMON-DRAIN AMPLIFIER) 690
BODY EFFECT AND GAIN 691
LEVEL SHIFTING 692
INPUT CAPACITANCE 693
NOISE PERFORMANCE OF THE SF AMPLIFIER 694
FREQUENCY BEHAVIOR 694
SF AS AN OUTPUT BUFFER 696
A CLASS AB OUTPUT BUFFER USING SFS 697
21.3 THE PUSH-PULL AMPLIFIER 698
21.3.1 DC OPERATION AND BIASING 699
POWER CONVERSION EFFICIENCY 699
21.3.2 SMALL-SIGNAL ANALYSIS 702
21.3.3 DISTORTION 704
MODELING DISTORTION WITH SPICE 705
CHAPTER 22 DIFFERENTIAL AMPLIFIERS 711
22.1 THE SOURCE-COUPLED PAIR 711
22.1.1 DC OPERATION 711
MAXIMUM AND MINIMUM DIFFERENTIAL INPUT VOLTAGE 712
MAXIMUM AND MINIMUM COMMON-MODE INPUT VOLTAGE 713
CURRENT MIRROR LOAD 715
BIASING FROM THE CURRENT MIRROR LOAD 717
MINIMUM POWER SUPPLY VOLTAGE 717
22.1.2 AC OPERATION 718
AC GAIN WITH A CURRENT MIRROR LOAD 719
22.1.3 COMMON-MODE REJECTION RATIO 721
INPUT-REFERRED OFFSET FROM FINITE CMRR 723
22.1.4 MATCHING CONSIDERATIONS 724
INPUT-REFERRED OFFSET WITH A CURRENT MIRROR LOAD 725
22.1.5 NOISE PERFORMANCE 726
22.1.6 SLEW-RATE LIMITATIONS 727
22.2 THE SOURCE CROSS-COUPLED PAIR 727
OPERATION OF THE DIFF-AMP 728
IMAGE 18
CONTENTS
XXUI
INPUT SIGNAL RANGE 729
22.2.1 CURRENT SOURCE LOAD 731
INPUT SIGNAL RANGE 732
22.3 CASCODE LOADS (THE TELESCOPIC DIFF-AMP) 733
22.4 WIDE-SWING DIFFERENTIAL AMPLIFIERS 736
22.4.1 CURRENT DIFFERENTIAL AMPLIFIER 737
22.4.2 CONSTANT TRANSCONDUCTANCE DIFF-AMP 738
DISCUSSION 740
CHAPTER 23 VOLTAGE REFERENCES 745
23.1 MOSFET-RESISTOR VOLTAGE REFERENCES 746
23.1.1 THE RESISTOR-MOSFET DIVIDER 746
23.1.2 THE MOSFET-ONLY VOLTAGE DIVIDER 749
23.1.3 SELF-BIASED VOLTAGE REFERENCES 750
FORCING THE SAME CURRENT THROUGH EACH SIDE OF THE 751
REFERENCE
AN ALTERNATE TOPOLOGY 756
23.2 PARASITIC DIODE-BASED REFERENCES 757
DIODE BEHAVIOR 758
THE BANDGAP ENERGY OF SILICON 759
LOWER VOLTAGE REFERENCE DESIGN 760
23.2.1 LONG-CHANNEL BGR DESIGN 761
DIODE-REFERENCED SELF-BIASING (CTAT) 761
THERMAL VOLTAGE-REFERENCED SELF-BIASING (PTAT) 762
BANDGAP REFERENCE DESIGN 765
ALTERNATIVE BGR TOPOLOGIES 766
23.2.2 SHORT-CHANNEL BGR DESIGN 768
THE ADDED AMPLIFIER 770
LOWER VOLTAGE OPERATION 770
CHAPTER 24 OPERATIONAL AMPLIFIERS I 773
24.1 THE TWO-STAGE OP-AMP 774
LOW-FREQUENCY, OPEN LOOP GAIN, A 0LDC IIA
INPUT COMMON-MODE RANGE 774
POWER DISSIPATION 775
OUTPUT SWING AND CURRENT SOURCE/SINKING CAPABILITY 775
OFFSETS 775
COMPENSATING THE OP-AMP 776
GAIN AND PHASE MARGINS 781
IMAGE 19
REMOVING THE ZERO 782
COMPENSATION FOR HIGH-SPEED OPERATION 783
SLEW-RATE LIMITATIONS 787
COMMON-MODE REJECTION RATIO (CMRR) 789
POWER SUPPLY REJECTION RATIO (PSRR) 790
INCREASING THE INPUT COMMON-MODE VOLTAGE RANGE 791
ESTIMATING BANDWIDTH IN OP-AMPS CIRCUITS 792
24.2 AN OP-AMP WITH OUTPUT BUFFER 793
COMPENSATING THE OP-AMP 794
24.3 THE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) 796
UNITY-GAIN FREQUENCY, F UN 797
INCREASING THE OTA OUTPUT RESISTANCE 798
AN IMPORTANT NOTE 799
OTA WITH AN OUTPUT BUFFER (AN OP-AMP) 800
THE FOLDED-CASCODE OTA AND OP-AMP 803
24.4 GAIN-ENHANCEMENT 808
BANDWIDTH OF THE ADDED GE AMPLIFIERS 809
COMPENSATING THE ADDED GE AMPLIFIERS 811
24.5 SOME EXAMPLES AND DISCUSSIONS 812
A VOLTAGE REGULATOR 812
BAD OUTPUT STAGE DESIGN 817
THREE-STAGE OP-AMP DESIGN 820
CHAPTER 25 DYNAMIC ANALOG CIRCUITS 829
25.1 THE MOSFET SWITCH 829
CHARGE INJECTION 830
CAPACITIVE FEEDTHROUGH 831
REDUCTION OF CHARGE INJECTION AND CLOCK FEEDTHROUGH 832
KT/C NOISE 833
25.1.1 SAMPLE-AND-HOLD CIRCUITS 834
25.2 FULLY-DIFFERENTIAL CIRCUITS 836
GAIN 836
COMMON-MODE FEEDBACK 837
COUPLED NOISE REJECTION 838
OTHER BENEFITS OF FULLY-DIFFERENTIAL OP-AMPS 838
25.2.1 A FULLY-DIFFERENTIAL SAMPLE-AND-HOLD 838
CONNECTING THE INPUTS TO THE BOTTOM (POLYL) PLATE 840
BOTTOM PLATE SAMPLING 841
IMAGE 20
SPICE SIMULATION 841
25.3 SWITCHED-CAPACITOR CIRCUITS 843
25.3.1 SWITCHED-CAPACITOR INTEGRATOR 845
PARASITIC INSENSITIVE 846
OTHER INTEGRATOR CONFIGURATIONS 846
EXACT FREQUENCY RESPONSE OF A SWITCHED-CAPACITOR 849
INTEGRATOR
CAPACITOR LAYOUT 851
OP-AMP SETTLING TIME 852
25.4 CIRCUITS 853
REDUCING OFFSET VOLTAGE OF AN OP-AMP 853
DYNAMIC COMPARATOR 854
DYNAMIC CURRENT MIRRORS 856
DYNAMIC AMPLIFIERS 858
CHAPTER 26 OPERATIONAL AMPLIFIERS II 863
26.1 BIASING FOR POWER AND SPEED 863
26.1.1 DEVICE CHARACTERISTICS 864
26.1.2 BIASING CIRCUIT 865
LAYOUT OF DIFFERENTIAL OP-AMPS 865
SELF-BIASED REFERENCE 866
26.2 BASIC CONCEPTS 867
MODELING OFFSET 867
A DIFF-AMP 867
A SINGLE BIAS INPUT DIFF-AMP 868
THE DIFF-AMP'S TAIL CURRENT SOURCE 868
USING A CMFB AMPLIFIER 869
COMPENSATING THE CMFB LOOP 871
EXTENDING THE CMFB AMPLIFIER INPUT RANGE 873
DYNAMIC CMFB 874
26.3 BASIC OP-AMP DESIGN 876
THE DIFFERENTIAL AMPLIFIER 877
ADDING A SECOND STAGE (MAKING AN OP-AMP) 878
STEP RESPONSE 880
ADDING CMFB 881
CMFB AMPLIFIER 882
THE TWO-STAGE OP-AMP WITH CMFB 883
ORIGIN OF THE PROBLEM 884
IMAGE 21
SIMULATION RESULTS 886
USING MOSFETS OPERATING IN THE TRIODE REGION 887
START-UP PROBLEMS 887
LOWERING INPUT CAPACITANCE 887
MAKING THE OP-AMP MORE PRACTICAL 888
INCREASING THE OP-AMP'S OPEN-LOOP GAIN 889
OFFSETS 892
OP-AMP OFFSET EFFECTS ON OUTPUTS 893
SINGLE-ENDED TO DIFFERENTIAL CONVERSION 894
CMFB SETTLING TIME 895
CMFB IN THE OUTPUT BUFFER (FIG. 26.43) OR THE 895
DIFF-AMP (FIG. 26.40)?
26.4 OP-AMP DESIGN USING SWITCHED-CAPACITOR CMFB 896
CLOCK SIGNALS 896
SWITCHED-CAPACITOR CMFB 896
THE OP-AMP'S FIRST STAGE 898
THE OUTPUT BUFFER 900
AN APPLICATION OF THE OP-AMP 901
SIMULATION RESULTS 902
INCREASING THE WIDTHS OF THE DIFF-PAIR 903
A FINAL NOTE CONCERNING BIASING 903
CHAPTER 27 NONLINEAR ANALOG CIRCUITS 909
27.1 BASIC CMOS COMPARATOR DESIGN 909
PREAMPLIFICATION 910
DECISION CIRCUIT 910
OUTPUT BUFFER 913
27.1.1 CHARACTERIZING THE COMPARATOR 915
COMPARATOR DC PERFORMANCE 915
TRANSIENT RESPONSE 916
PROPAGATION DELAY 918
MINIMUM INPUT SLEW RATE 918
27.1.2 CLOCKED COMPARATORS 918
27.1.3 INPUT BUFFERS REVISITED 920
27.2 ADAPTIVE BIASING 920
27.3 ANALOG MULTIPLIERS 923
27.3.1 THE MULTIPLYING QUAD 924
SIMULATING THE OPERATION OF THE MULTIPLIER 926
IMAGE 22
27.3.2 MULTIPLIER DESIGN USING SQUARING CIRCUITS 928
CHAPTER 28 DATA CONVERTER FUNDAMENTALS 931
28.1 ANALOG VERSUS DISCRETE TIME SIGNALS 931
28.2 CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS 932
28.3 SAMPLE-AND-HOLD (S/H) CHARACTERISTICS 935
SAMPLE MODE 936
HOLD MODE 937
APERTURE ERROR 937
28.4 DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS 938
DIFFERENTIAL NONLINEARITY 941
INTEGRAL NONLINEARITY 943
OFFSET 945
GAIN ERROR 945
LATENCY 945
SIGNAL-TO-NOISE RATIO (SNR) 945
DYNAMIC RANGE 947
28.5 ANALOG-TO-DIGITAL CONVERTER (ADC) SPECIFICATIONS 947
QUANTIZATION ERROR 948
DIFFERENTIAL NONLINEARITY 950
MISSING CODES 951
INTEGRAL NONLINEARITY 951
OFFSET AND GAIN ERROR 953
ALIASING 953
SIGNAL-TO-NOISE RATIO 956
APERTURE ERROR 956
28.6 MIXED-SIGNAL LAYOUT ISSUES 957
FLOORPLANNING 958
POWER SUPPLY AND GROUND ISSUES 958
FULLY DIFFERENTIAL DESIGN 960
GUARD RINGS 960
SHIELDING 961
OTHER INTERCONNECT CONSIDERATIONS 962
CHAPTER 29 DATA CONVERTER ARCHITECTURES 965
29.1 DAC ARCHITECTURES 965
29.1.1 DIGITAL INPUT CODE 965
29.1.2 RESISTOR STRING 966
MISMATCH ERRORS RELATED TO THE RESISTOR-STRING DAC 967
IMAGE 23
INTEGRAL NONLINEARITY OF THE RESISTOR-STRING DAC 969
DIFFERENTIAL NONLINEARITY OF THE WORST-CASE RESISTOR- 970
STRING DAC
29.1.3 R-2R LADDER NETWORKS 971
29.1.4 CURRENT STEERING 973
MISMATCH ERRORS RELATED TO CURRENT-STEERING DACS 976
29.1.5 CHARGE-SCALING DACS 978
LAYOUT CONSIDERATIONS FOR A BINARY-WEIGHTED 980
CAPACITOR ARRAY
THESPLITARRAY 980
29.1.6 CYCLIC DAC 982
29.1.7 PIPELINE DAC 984
29.2 ADC ARCHITECTURES 985
29.2.1 FLASH 985
ACCURACY ISSUES FOR THE FLASH ADC 988
29.2.2 THE TWO-STEP FLASH ADC 990
ACCURACY ISSUES RELATED TO THE TWO-STEP FLASH 992
CONVERTER
ACCURACY ISSUES RELATED TO OPERATIONAL AMPLIFIERS 992
29.2.3 THE PIPELINE ADC 994
ACCURACY ISSUES RELATED TO THE PIPELINE CONVERTER 996
29.2.4 INTEGRATING ADCS 998
SINGLE-SLOPE ARCHITECTURE 998
ACCURACY ISSUES RELATED TO THE SINGLE-SLOPE ADC 1000
DUAL-SLOPE ARCHITECTURE 1000
ACCURACY ISSUES RELATED TO THE DUAL-SLOPE ADC 1002
29.2.5 THE SUCCESSIVE APPROXIMATION ADC 1003
THE CHARGE-REDISTRIBUTION SUCCESSIVE APPROXIMATION 1005 ADC
29.2.6 THE OVERSAMPLING ADC 1007
DIFFERENCES IN NYQUIST RATE AND OVERSAMPIED ADCS 1007
THE FIRST-ORDER AS MODULATOR 1008
THE HIGHER ORDER AE MODULATORS 1010
INDEX 1023
ABOUT THE AUTHOR 1039 |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Baker, Russel Jacob 1964- |
| author_GND | (DE-588)138111715 |
| author_facet | Baker, Russel Jacob 1964- |
| author_role | aut |
| author_sort | Baker, Russel Jacob 1964- |
| author_variant | r j b rj rjb |
| building | Verbundindex |
| bvnumber | BV023245801 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.99.M44 |
| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| classification_tum | ELT 272f |
| ctrlnum | (OCoLC)181928338 (DE-599)GBV550663274 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | rev. 2. ed. |
| format | Book |
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| genre | (DE-588)4173536-5 Patentschrift gnd-content |
| genre_facet | Patentschrift |
| id | DE-604.BV023245801 |
| illustrated | Illustrated |
| index_date | 2024-07-02T20:25:43Z |
| indexdate | 2024-07-09T21:14:00Z |
| institution | BVB |
| isbn | 0470229411 9780470229415 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016431259 |
| oclc_num | 181928338 |
| open_access_boolean | 1 |
| owner | DE-1043 DE-703 DE-91 DE-BY-TUM DE-634 DE-859 DE-83 DE-M347 |
| owner_facet | DE-1043 DE-703 DE-91 DE-BY-TUM DE-634 DE-859 DE-83 DE-M347 |
| physical | XXXI, 1038 S. Ill., graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | IEEE Press [u.a.] |
| record_format | marc |
| series2 | IEEE Press series on microelectronic systems |
| spelling | Baker, Russel Jacob 1964- Verfasser (DE-588)138111715 aut CMOS circuit design, layout and simulation R. Jacob Baker rev. 2. ed. Piscaaway, NJ [u.a.] IEEE Press [u.a.] 2008 XXXI, 1038 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier IEEE Press series on microelectronic systems Includes bibliographical references and index Entegre devreler - Tasarım ve yapım Metal oksit yarı iletken alan-etki transistörleri Metal oksit yarı iletkenleri, Tümleyici - Tasarım ve yapım Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf MOS-FET (DE-588)4207266-9 gnd rswk-swf Simulation (DE-588)4055072-2 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf (DE-588)4173536-5 Patentschrift gnd-content CMOS-Schaltung (DE-588)4148111-2 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s Entwurf (DE-588)4121208-3 s 1\p DE-604 CMOS (DE-588)4010319-5 s 2\p DE-604 Simulation (DE-588)4055072-2 s 3\p DE-604 MOS-FET (DE-588)4207266-9 s 4\p DE-604 http://catdir.loc.gov/catdir/enhancements/fy0827/2008270753-d.html Beschreibung für Leser http://www.gbv.de/dms/ilmenau/toc/550663274.PDF kostenfrei Inhaltsverzeichnis GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016431259&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Baker, Russel Jacob 1964- CMOS circuit design, layout and simulation Entegre devreler - Tasarım ve yapım Metal oksit yarı iletken alan-etki transistörleri Metal oksit yarı iletkenleri, Tümleyici - Tasarım ve yapım Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Integrierte Schaltung (DE-588)4027242-4 gnd MOS-FET (DE-588)4207266-9 gnd Simulation (DE-588)4055072-2 gnd Entwurf (DE-588)4121208-3 gnd CMOS (DE-588)4010319-5 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4148111-2 (DE-588)4027242-4 (DE-588)4207266-9 (DE-588)4055072-2 (DE-588)4121208-3 (DE-588)4010319-5 (DE-588)4173536-5 |
| title | CMOS circuit design, layout and simulation |
| title_auth | CMOS circuit design, layout and simulation |
| title_exact_search | CMOS circuit design, layout and simulation |
| title_exact_search_txtP | CMOS circuit design, layout and simulation |
| title_full | CMOS circuit design, layout and simulation R. Jacob Baker |
| title_fullStr | CMOS circuit design, layout and simulation R. Jacob Baker |
| title_full_unstemmed | CMOS circuit design, layout and simulation R. Jacob Baker |
| title_short | CMOS |
| title_sort | cmos circuit design layout and simulation |
| title_sub | circuit design, layout and simulation |
| topic | Entegre devreler - Tasarım ve yapım Metal oksit yarı iletken alan-etki transistörleri Metal oksit yarı iletkenleri, Tümleyici - Tasarım ve yapım Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd CMOS-Schaltung (DE-588)4148111-2 gnd Integrierte Schaltung (DE-588)4027242-4 gnd MOS-FET (DE-588)4207266-9 gnd Simulation (DE-588)4055072-2 gnd Entwurf (DE-588)4121208-3 gnd CMOS (DE-588)4010319-5 gnd |
| topic_facet | Entegre devreler - Tasarım ve yapım Metal oksit yarı iletken alan-etki transistörleri Metal oksit yarı iletkenleri, Tümleyici - Tasarım ve yapım Integrated circuits Design and construction Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Design and construction Schaltungsentwurf CMOS-Schaltung Integrierte Schaltung MOS-FET Simulation Entwurf CMOS Patentschrift |
| url | http://catdir.loc.gov/catdir/enhancements/fy0827/2008270753-d.html http://www.gbv.de/dms/ilmenau/toc/550663274.PDF http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016431259&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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