VLSI circuit design methodology demystified: a conceptual taxonomy
This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency.. - This book was written to arm engineers qualified and knowle...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Hoboken, NJ
Wiley
2008
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Zusammenfassung: | This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency.. - This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems. |
| Beschreibung: | XVII, 202 S. Ill., graph. Darst. |
| ISBN: | 0470127422 9780470127421 |
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| 520 | 3 | |a This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency.. - This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems. | |
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Datensatz im Suchindex
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| adam_text | VLSI CIRCUIT DESIGN METHODOLOGY DEMYSTIFIED A CONCEPTUAL TAXONOMY LIMING
XIU IEEE PRESS BICENTENNIAL 1 8 O 7 WILEY 2 O O 7 11CENTENNIAL
WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS
FOREWORD XI RICHARD TEMPLETON FOREWORD XIII HANS STORK PREFACE XV
ACKNOWLEDGMENTS XVII CHAPTER 1 THE BIG PICTURE 1 1. WHAT ISA CHIP? 1 2.
WHAT ARE THE REQUIREMENTS OF A SUCCESSFUL CHIP DESIGN? 3 3. WHAT ARE THE
CHALLENGES IN TODAY S VERY DEEP SUBMICRON 4 (VDSM), MULTIMILLION GATE
DESIGNS? 4. WHAT MAJOR PROCESS TECHNOLOGIES ARE USED IN TODAY S DESIGN 5
ENVIRONMENT? 5. WHAT ARE THE GOALS OF NEW CHIP DESIGN? 8 6. WHAT ARE THE
MAJOR APPROACHES OF TODAY S VERY LARGE SCALE 9 INTEGRATION (VLSI)
CIRCUIT DESIGN PRACTICES? 7. WHAT IS STANDARD CELL-BASED,
APPLICATION-SPECIFIC INTEGRATED 11 CIRCUIT (ASIC) DESIGN METHODOLOGY? 8.
WHAT IS THE SYSTEM-ON-CHIP (SOC) APPROACH? 12 9. WHAT ARE THE DRIVING
FORCES BEHIND THE SOC TREND? 15 10. WHAT ARE THE MAJOR TASKS IN
DEVELOPING A SOC CHIP FROM 15 CONCEPT TO SILICON? 11. WHAT ARE THE MAJOR
COSTS OF DEVELOPING A CHIP? 16 CHAPTER 2 THE BASICS OF THE CMOS PROCESS
17 AND DEVICES 12. WHAT ARE THE MAJOR PROCESS STEPS IN BUILDING MOSFET
17 TRANSISTORS? VII VIII CONTENTS 13. WHAT ARE THE TWO TYPES OF MOSFET
TRANSISTORS? 19 14. WHAT ARE BASE LAYERS AND METAL LAYERS? 20 15. WHAT
ARE WAFERS AND DIES? 24 16. WHAT IS SEMICONDUCTOR LITHOGRAPHY? 28 17.
WHAT IS A PACKAGE? 33 CHAPTER 3 THE CHALLENGES IN VLSI CIRCUIT DESIGN 41
18. WHAT IS THE ROLE OF FUNCTIONAL VERIFICATION IN THE IC 41 DESIGN
PROCESS? 19. WHAT ARE SOME OF THE DESIGN INTEGRITY ISSUES? 44 20. WHAT
IS DESIGN FOR TESTABILITY? 46 21. WHY IS REDUCING THE CHIP S POWER
CONSUMPTION SO IMPORTANT? 48 22. WHAT ARE SOME OF THE CHALLENGES IN CHIP
PACKAGING? 49 23. WHAT ARE THE ADVANTAGES OF DESIGN REUSE? 50 24. WHAT
IS HARDWARE/SOFTWARE CO-DESIGN? 51 25. WHY IS THE CLOCK SO IMPORTANT? 54
26. WHAT IS THE LEAKAGE CURRENT PROBLEM? 57 27. WHAT IS DESIGN FOR
MANUFACTURABILITY? 60 28. WHAT IS CHIP RELIABILITY? 62 29. WHAT IS
ANALOG INTEGRATION IN THE DIGITAL ENVIRONMENT? 65 30. WHAT IS THE ROLE
OFEDATOOLS IN IC DESIGN? 67 31. WHAT IS THE ROLE OF THE EMBEDDED
PROCESSOR IN THE SOC 69 ENVIRONMENT? CHAPTER 4 CELL-BASED ASIC DESIGN
METHODOLOGY 73 32. WHAT ARE THE MAJOR TASKS AND PERSONNEL REQUIRED IN A
CHIP 73 DESIGN PROJECT? 33. WHAT ARE THE MAJOR STEPS IN ASIC CHIP
CONSTRUCTION? 74 34. WHAT IS THE ASIC DESIGN FLOW? 75 35. WHAT ARE THE
TWO MAJOR ASPECTS OF ASIC DESIGN FLOW? 77 36. WHAT ARE THE
CHARACTERISTICS OF GOOD DESIGN FLOW? 80 37. WHAT IS THE ROLE OF MARKET
RESEARCH IN AN ASIC PROJECT? 81 38. WHAT IS THE OPTIMAL SOLUTION OF AN
ASIC PROJECT? 82 39. WHAT IS SYSTEM-LEVEL STUDY OF A PROJECT? 84 40.
WHAT ARE THE APPROACHES FOR VERIFYING DESIGN AT THE 85 SYSTEM LEVEL? 41.
WHAT IS REGISTER-TRANSFER-LEVEL (RTL) SYSTEM-LEVEL DESCRIPTION? 86 42.
WHAT ARE METHODS OF VERIFYING DESIGN AT THE REGISTER-TRANSFER- 87 LEVEL?
43. WHAT IS A TEST BENCH? 88 44. WHAT IS CODE COVERAGE? 89 CONTENTS IX
45. WHAT IS FUNCTIONAL COVERAGE? 89 46. WHAT IS BUG RATE CONVERGENCE? 90
47. WHAT IS DESIGN PLANNING? 91 48. WHAT ARE HARD MACRO AND SOFT MACRO?
92 49. WHAT IS HARDWARE DESCRIPTION LANGUAGE (HDL)? 92 50. WHAT IS
REGISTER-TRANSFER-LEVEL (RTL) DESCRIPTION OF HARDWARE? 93 51. WHAT IS
STANDARD CELL? WHAT ARE THE DIFFERENCES AMONG STANDARD 94 CELL,
GATE-ARRAY, AND SEA-OF-GATE APPROACHES? 52. WHAT IS AN ASIC LIBRARY? 103
53. WHAT IS LOGIC SYNTHESIS? 105 54. WHAT ARE THE OPTIMIZATION TARGETS
OF LOGIC SYNTHESIS? 106 55. WHAT IS SCHEMATIC OR NETLIST? 107 56. WHAT
IS THE GATE COUNT OF A DESIGN? 111 57. WHAT IS THE PURPOSE OF TEST
INSERTION DURING LOGIC SYNTHESIS? 111 58. WHAT IS THE MOST COMMONLY USED
MODEL IN VLSI CIRCUIT TESTING? 112 59. WHAT ARE CONTROLLABILITY AND
OBSERVABILITY IN A DIGITAL CIRCUIT? 114 60. WHAT IS A TESTABLE CIRCUIT?
115 61. WHAT IS THE AIM OF SCAN INSERTION? 116 62. WHAT IS FAULT
COVERAGE? WHAT IS DEFECT PART PER MILLION (DPPM)? 117 63. WHY IS DESIGN
FOR TESTABILITY IMPORTANT FOR A PRODUCT S 119 FINANCIAL SUCCESS? 64.
WHAT IS CHIP POWER USAGE ANALYSIS? 120 65. WHAT ARE THE MAJOR COMPONENTS
OF CMOS POWER CONSUMPTION? 121 66. WHAT IS POWER OPTIMIZATION? 123 67.
WHAT IS VLSI PHYSICAL DESIGN? 123 68. WHAT ARE THE PROBLEMS THAT MAKE
VLSI PHYSICAL DESIGN SO 124 CHALLENGING? 69. WHAT IS FLOORPLANNING? 128
70. WHAT IS THE PLACEMENT PROCESS? 131 71. WHAT IS THE ROUTING PROCESS?
133 72. WHAT IS A POWER NETWORK? 135 73. WHAT IS CLOCK DISTRIBUTION? 139
74. WHAT ARE THE KEY REQUIREMENTS FOR CONSTRUCTING A CLOCK TREE? 143 75.
WHAT IS THE DIFFERENCE BETWEEN TIME SKEW AND LENGTH SKEW IN A 145 CLOCK
TREE? 76. WHAT IS SCAN CHAIN? 149 77. WHAT IS SCAN CHAIN REORDERING? 151
78. WHAT IS PARASITIC EXTRACTION? 152 79. WHAT IS DELAY CALCULATION? 155
80. WHAT IS BACK ANNOTATION? 156 81. WHAT KIND OF SIGNAL INTEGRITY
PROBLEMS DO PLACE AND ROUTE 156 X CONTENTS TOOLS HANDLE? 82. WHAT IS
CROSS-TALK DELAY? 157 83. WHAT IS CROSS-TALK NOISE? 158 84. WHAT IS IR
DROP? 159 85. WHAT ARE THE MAJOR NETLIST FORMATS FOR DESIGN
REPRESENTATION? 162 86. WHAT IS GATE-LEVEL LOGIC VERIFICATION BEFORE
TAPEOUT? 162 87. WHAT IS EQUIVALENCE CHECK? 163 88. WHAT IS TIMING
VERIFICATION? 164 89. WHAT IS DESIGN CONSTRAINT? 165 90. WHAT IS STATIC
TIMING ANALYSIS (STA)? 165 91. WHAT IS SIMULATION APPROACH ON TIMING
VERIFICATION? 169 92. WHAT IS THE LOGICAL-EFFORT-BASED TIMING CLOSURE
APPROACH? 173 93. WHAT IS PHYSICAL VERIFICATION? 178 94. WHAT ARE DESIGN
RULE CHECK (DRC), DESIGN VERIFICATION (DV), 179 AND GEOMETRY
VERIFICATION (GV)? 95. WHAT IS SCHEMATIC VERIFICATION (SV) OR LAYOUT
VERSUS 181 SCHEMATIC (LVS)? 96. WHAT IS AUTOMATIC TEST PATTERN
GENERATION (ATPG)? 182 97. WHAT IS TAPEOUT? 184 98. WHATISYIELD? 184 99.
WHAT ARE THE QUALITIES OF A GOOD IC IMPLEMENTATION DESIGNER? 187
CONCLUSION ACRONYMS BIBLIOGRAPHY 189 191 195 INDEX 199
|
| adam_txt |
VLSI CIRCUIT DESIGN METHODOLOGY DEMYSTIFIED A CONCEPTUAL TAXONOMY LIMING
XIU IEEE PRESS BICENTENNIAL 1 8 O 7 WILEY 2 O O 7 11CENTENNIAL
WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS
FOREWORD XI RICHARD TEMPLETON FOREWORD XIII HANS STORK PREFACE XV
ACKNOWLEDGMENTS XVII CHAPTER 1 THE BIG PICTURE 1 1. WHAT ISA CHIP? 1 2.
WHAT ARE THE REQUIREMENTS OF A SUCCESSFUL CHIP DESIGN? 3 3. WHAT ARE THE
CHALLENGES IN TODAY'S VERY DEEP SUBMICRON 4 (VDSM), MULTIMILLION GATE
DESIGNS? 4. WHAT MAJOR PROCESS TECHNOLOGIES ARE USED IN TODAY'S DESIGN 5
ENVIRONMENT? 5. WHAT ARE THE GOALS OF NEW CHIP DESIGN? 8 6. WHAT ARE THE
MAJOR APPROACHES OF TODAY'S VERY LARGE SCALE 9 INTEGRATION (VLSI)
CIRCUIT DESIGN PRACTICES? 7. WHAT IS STANDARD CELL-BASED,
APPLICATION-SPECIFIC INTEGRATED 11 CIRCUIT (ASIC) DESIGN METHODOLOGY? 8.
WHAT IS THE SYSTEM-ON-CHIP (SOC) APPROACH? 12 9. WHAT ARE THE DRIVING
FORCES BEHIND THE SOC TREND? 15 10. WHAT ARE THE MAJOR TASKS IN
DEVELOPING A SOC CHIP FROM 15 CONCEPT TO SILICON? 11. WHAT ARE THE MAJOR
COSTS OF DEVELOPING A CHIP? 16 CHAPTER 2 THE BASICS OF THE CMOS PROCESS
17 AND DEVICES 12. WHAT ARE THE MAJOR PROCESS STEPS IN BUILDING MOSFET
17 TRANSISTORS? VII VIII CONTENTS 13. WHAT ARE THE TWO TYPES OF MOSFET
TRANSISTORS? 19 14. WHAT ARE BASE LAYERS AND METAL LAYERS? 20 15. WHAT
ARE WAFERS AND DIES? 24 16. WHAT IS SEMICONDUCTOR LITHOGRAPHY? 28 17.
WHAT IS A PACKAGE? 33 CHAPTER 3 THE CHALLENGES IN VLSI CIRCUIT DESIGN 41
18. WHAT IS THE ROLE OF FUNCTIONAL VERIFICATION IN THE IC 41 DESIGN
PROCESS? 19. WHAT ARE SOME OF THE DESIGN INTEGRITY ISSUES? 44 20. WHAT
IS DESIGN FOR TESTABILITY? 46 21. WHY IS REDUCING THE CHIP'S POWER
CONSUMPTION SO IMPORTANT? 48 22. WHAT ARE SOME OF THE CHALLENGES IN CHIP
PACKAGING? 49 23. WHAT ARE THE ADVANTAGES OF DESIGN REUSE? 50 24. WHAT
IS HARDWARE/SOFTWARE CO-DESIGN? 51 25. WHY IS THE CLOCK SO IMPORTANT? 54
26. WHAT IS THE LEAKAGE CURRENT PROBLEM? 57 27. WHAT IS DESIGN FOR
MANUFACTURABILITY? 60 28. WHAT IS CHIP RELIABILITY? 62 29. WHAT IS
ANALOG INTEGRATION IN THE DIGITAL ENVIRONMENT? 65 30. WHAT IS THE ROLE
OFEDATOOLS IN IC DESIGN? 67 31. WHAT IS THE ROLE OF THE EMBEDDED
PROCESSOR IN THE SOC 69 ENVIRONMENT? CHAPTER 4 CELL-BASED ASIC DESIGN
METHODOLOGY 73 32. WHAT ARE THE MAJOR TASKS AND PERSONNEL REQUIRED IN A
CHIP 73 DESIGN PROJECT? 33. WHAT ARE THE MAJOR STEPS IN ASIC CHIP
CONSTRUCTION? 74 34. WHAT IS THE ASIC DESIGN FLOW? 75 35. WHAT ARE THE
TWO MAJOR ASPECTS OF ASIC DESIGN FLOW? 77 36. WHAT ARE THE
CHARACTERISTICS OF GOOD DESIGN FLOW? 80 37. WHAT IS THE ROLE OF MARKET
RESEARCH IN AN ASIC PROJECT? 81 38. WHAT IS THE OPTIMAL SOLUTION OF AN
ASIC PROJECT? 82 39. WHAT IS SYSTEM-LEVEL STUDY OF A PROJECT? 84 40.
WHAT ARE THE APPROACHES FOR VERIFYING DESIGN AT THE 85 SYSTEM LEVEL? 41.
WHAT IS REGISTER-TRANSFER-LEVEL (RTL) SYSTEM-LEVEL DESCRIPTION? 86 42.
WHAT ARE METHODS OF VERIFYING DESIGN AT THE REGISTER-TRANSFER- 87 LEVEL?
43. WHAT IS A TEST BENCH? 88 44. WHAT IS CODE COVERAGE? 89 CONTENTS IX
45. WHAT IS FUNCTIONAL COVERAGE? 89 46. WHAT IS BUG RATE CONVERGENCE? 90
47. WHAT IS DESIGN PLANNING? 91 48. WHAT ARE HARD MACRO AND SOFT MACRO?
92 49. WHAT IS HARDWARE DESCRIPTION LANGUAGE (HDL)? 92 50. WHAT IS
REGISTER-TRANSFER-LEVEL (RTL) DESCRIPTION OF HARDWARE? 93 51. WHAT IS
STANDARD CELL? WHAT ARE THE DIFFERENCES AMONG STANDARD 94 CELL,
GATE-ARRAY, AND SEA-OF-GATE APPROACHES? 52. WHAT IS AN ASIC LIBRARY? 103
53. WHAT IS LOGIC SYNTHESIS? 105 54. WHAT ARE THE OPTIMIZATION TARGETS
OF LOGIC SYNTHESIS? 106 55. WHAT IS SCHEMATIC OR NETLIST? 107 56. WHAT
IS THE GATE COUNT OF A DESIGN? 111 57. WHAT IS THE PURPOSE OF TEST
INSERTION DURING LOGIC SYNTHESIS? 111 58. WHAT IS THE MOST COMMONLY USED
MODEL IN VLSI CIRCUIT TESTING? 112 59. WHAT ARE CONTROLLABILITY AND
OBSERVABILITY IN A DIGITAL CIRCUIT? 114 60. WHAT IS A TESTABLE CIRCUIT?
115 61. WHAT IS THE AIM OF SCAN INSERTION? 116 62. WHAT IS FAULT
COVERAGE? WHAT IS DEFECT PART PER MILLION (DPPM)? 117 63. WHY IS DESIGN
FOR TESTABILITY IMPORTANT FOR A PRODUCT'S 119 FINANCIAL SUCCESS? 64.
WHAT IS CHIP POWER USAGE ANALYSIS? 120 65. WHAT ARE THE MAJOR COMPONENTS
OF CMOS POWER CONSUMPTION? 121 66. WHAT IS POWER OPTIMIZATION? 123 67.
WHAT IS VLSI PHYSICAL DESIGN? 123 68. WHAT ARE THE PROBLEMS THAT MAKE
VLSI PHYSICAL DESIGN SO 124 CHALLENGING? 69. WHAT IS FLOORPLANNING? 128
70. WHAT IS THE PLACEMENT PROCESS? 131 71. WHAT IS THE ROUTING PROCESS?
133 72. WHAT IS A POWER NETWORK? 135 73. WHAT IS CLOCK DISTRIBUTION? 139
74. WHAT ARE THE KEY REQUIREMENTS FOR CONSTRUCTING A CLOCK TREE? 143 75.
WHAT IS THE DIFFERENCE BETWEEN TIME SKEW AND LENGTH SKEW IN A 145 CLOCK
TREE? 76. WHAT IS SCAN CHAIN? 149 77. WHAT IS SCAN CHAIN REORDERING? 151
78. WHAT IS PARASITIC EXTRACTION? 152 79. WHAT IS DELAY CALCULATION? 155
80. WHAT IS BACK ANNOTATION? 156 81. WHAT KIND OF SIGNAL INTEGRITY
PROBLEMS DO PLACE AND ROUTE 156 X CONTENTS TOOLS HANDLE? 82. WHAT IS
CROSS-TALK DELAY? 157 83. WHAT IS CROSS-TALK NOISE? 158 84. WHAT IS IR
DROP? 159 85. WHAT ARE THE MAJOR NETLIST FORMATS FOR DESIGN
REPRESENTATION? 162 86. WHAT IS GATE-LEVEL LOGIC VERIFICATION BEFORE
TAPEOUT? 162 87. WHAT IS EQUIVALENCE CHECK? 163 88. WHAT IS TIMING
VERIFICATION? 164 89. WHAT IS DESIGN CONSTRAINT? 165 90. WHAT IS STATIC
TIMING ANALYSIS (STA)? 165 91. WHAT IS SIMULATION APPROACH ON TIMING
VERIFICATION? 169 92. WHAT IS THE LOGICAL-EFFORT-BASED TIMING CLOSURE
APPROACH? 173 93. WHAT IS PHYSICAL VERIFICATION? 178 94. WHAT ARE DESIGN
RULE CHECK (DRC), DESIGN VERIFICATION (DV), 179 AND GEOMETRY
VERIFICATION (GV)? 95. WHAT IS SCHEMATIC VERIFICATION (SV) OR LAYOUT
VERSUS 181 SCHEMATIC (LVS)? 96. WHAT IS AUTOMATIC TEST PATTERN
GENERATION (ATPG)? 182 97. WHAT IS TAPEOUT? 184 98. WHATISYIELD? 184 99.
WHAT ARE THE QUALITIES OF A GOOD IC IMPLEMENTATION DESIGNER? 187
CONCLUSION ACRONYMS BIBLIOGRAPHY 189 191 195 INDEX 199 |
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| illustrated | Illustrated |
| index_date | 2024-07-02T20:16:45Z |
| indexdate | 2024-07-09T21:13:27Z |
| institution | BVB |
| isbn | 0470127422 9780470127421 |
| language | English |
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| owner | DE-703 DE-1043 DE-83 |
| owner_facet | DE-703 DE-1043 DE-83 |
| physical | XVII, 202 S. Ill., graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Wiley |
| record_format | marc |
| spelling | Xiu, Liming Verfasser aut VLSI circuit design methodology demystified a conceptual taxonomy Liming Xiu Hoboken, NJ Wiley 2008 XVII, 202 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency.. - This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems. Integrated circuits Design Integrated circuits Very large scale integration VLSI (DE-588)4117388-0 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf (DE-588)4173536-5 Patentschrift gnd-content VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016408701&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Xiu, Liming VLSI circuit design methodology demystified a conceptual taxonomy Integrated circuits Design Integrated circuits Very large scale integration VLSI (DE-588)4117388-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4179389-4 (DE-588)4173536-5 |
| title | VLSI circuit design methodology demystified a conceptual taxonomy |
| title_auth | VLSI circuit design methodology demystified a conceptual taxonomy |
| title_exact_search | VLSI circuit design methodology demystified a conceptual taxonomy |
| title_exact_search_txtP | VLSI circuit design methodology demystified a conceptual taxonomy |
| title_full | VLSI circuit design methodology demystified a conceptual taxonomy Liming Xiu |
| title_fullStr | VLSI circuit design methodology demystified a conceptual taxonomy Liming Xiu |
| title_full_unstemmed | VLSI circuit design methodology demystified a conceptual taxonomy Liming Xiu |
| title_short | VLSI circuit design methodology demystified |
| title_sort | vlsi circuit design methodology demystified a conceptual taxonomy |
| title_sub | a conceptual taxonomy |
| topic | Integrated circuits Design Integrated circuits Very large scale integration VLSI (DE-588)4117388-0 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Integrated circuits Design Integrated circuits Very large scale integration VLSI Schaltungsentwurf Patentschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016408701&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT xiuliming vlsicircuitdesignmethodologydemystifiedaconceptualtaxonomy |