Integrated system-level modeling of network-on-chip enabled multi-processor platforms:
Gespeichert in:
| Format: | Abschlussarbeit Elektronisch E-Book |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Dordrecht
Springer
2006
|
| Schlagworte: | |
| Online-Zugang: | BTU01 FHR01 Volltext |
| Beschreibung: | 1 Online-Ressource (XIV, 199 S.) graph. Darst. |
| ISBN: | 9781402048258 9781402048265 |
| DOI: | 10.1007/1-4020-4826-2 |
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| id | DE-604.BV023160494 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T19:54:59Z |
| indexdate | 2024-07-09T21:11:44Z |
| institution | BVB |
| isbn | 9781402048258 9781402048265 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016332519 |
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| physical | 1 Online-Ressource (XIV, 199 S.) graph. Darst. |
| psigel | ZDB-2-ENG ebook |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Springer |
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| spelling | Integrated system-level modeling of network-on-chip enabled multi-processor platforms Tim Kogel ; Rainer Leupers ; Heinrich Meyr Dordrecht Springer 2006 1 Online-Ressource (XIV, 199 S.) graph. Darst. txt rdacontent c rdamedia cr rdacarrier Dissertation Technsiche Hochschule Aachen 2005 (DE-588)4113937-9 Hochschulschrift gnd-content Kogel, Tim Sonstige oth Leupers, Rainer Sonstige oth Meyr, Heinrich Sonstige oth https://doi.org/10.1007/1-4020-4826-2 Verlag Volltext |
| spellingShingle | Integrated system-level modeling of network-on-chip enabled multi-processor platforms |
| subject_GND | (DE-588)4113937-9 |
| title | Integrated system-level modeling of network-on-chip enabled multi-processor platforms |
| title_auth | Integrated system-level modeling of network-on-chip enabled multi-processor platforms |
| title_exact_search | Integrated system-level modeling of network-on-chip enabled multi-processor platforms |
| title_exact_search_txtP | Integrated system-level modeling of network-on-chip enabled multi-processor platforms |
| title_full | Integrated system-level modeling of network-on-chip enabled multi-processor platforms Tim Kogel ; Rainer Leupers ; Heinrich Meyr |
| title_fullStr | Integrated system-level modeling of network-on-chip enabled multi-processor platforms Tim Kogel ; Rainer Leupers ; Heinrich Meyr |
| title_full_unstemmed | Integrated system-level modeling of network-on-chip enabled multi-processor platforms Tim Kogel ; Rainer Leupers ; Heinrich Meyr |
| title_short | Integrated system-level modeling of network-on-chip enabled multi-processor platforms |
| title_sort | integrated system level modeling of network on chip enabled multi processor platforms |
| topic_facet | Hochschulschrift |
| url | https://doi.org/10.1007/1-4020-4826-2 |
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