Statistical analysis and optimization for VLSI: timing and power
Gespeichert in:
| Format: | Elektronisch E-Book |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Springer
2005
|
| Schriftenreihe: | Series on integrated circuits and systems
|
| Schlagworte: | |
| Online-Zugang: | BTU01 FHR01 Volltext |
| Beschreibung: | 1 Online-Ressource |
| ISBN: | 0387257381 0387265287 9780387257389 9780387265285 |
| DOI: | 10.1007/b137645 |
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| id | DE-604.BV023117324 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T19:50:26Z |
| indexdate | 2024-07-09T21:11:25Z |
| institution | BVB |
| isbn | 0387257381 0387265287 9780387257389 9780387265285 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016319831 |
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| physical | 1 Online-Ressource |
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| publishDate | 2005 |
| publishDateSearch | 2005 |
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| publisher | Springer |
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| series2 | Series on integrated circuits and systems |
| spelling | Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw New York, NY Springer 2005 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Series on integrated circuits and systems VLSI (DE-588)4117388-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s CAD (DE-588)4069794-0 s 1\p DE-604 Srivastava, Ashish Sonstige oth Sylvester, Dennis Sonstige oth Blaauw, David Sonstige oth https://doi.org/10.1007/b137645 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Statistical analysis and optimization for VLSI timing and power VLSI (DE-588)4117388-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4312536-0 (DE-588)4069794-0 |
| title | Statistical analysis and optimization for VLSI timing and power |
| title_auth | Statistical analysis and optimization for VLSI timing and power |
| title_exact_search | Statistical analysis and optimization for VLSI timing and power |
| title_exact_search_txtP | Statistical analysis and optimization for VLSI timing and power |
| title_full | Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw |
| title_fullStr | Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw |
| title_full_unstemmed | Statistical analysis and optimization for VLSI timing and power Ashish Srivastava ; Dennis Sylvester ; David Blaauw |
| title_short | Statistical analysis and optimization for VLSI |
| title_sort | statistical analysis and optimization for vlsi timing and power |
| title_sub | timing and power |
| topic | VLSI (DE-588)4117388-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | VLSI Entwurfsautomation CAD |
| url | https://doi.org/10.1007/b137645 |
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