Optimized ASIP synthesis from architecture description language models:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Abschlussarbeit Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Dordrecht
Springer
2007
|
| Schlagworte: | |
| Online-Zugang: | BTU01 FHR01 Volltext |
| Beschreibung: | 1 Online-Ressource |
| ISBN: | 1402056850 9781402056857 9781402056864 |
| DOI: | 10.1007/978-1-4020-5686-4 |
Internformat
MARC
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Datensatz im Suchindex
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| adam_txt | |
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| author | Schliebusch, Oliver Meyr, Heinrich Leupers, Rainer |
| author_facet | Schliebusch, Oliver Meyr, Heinrich Leupers, Rainer |
| author_role | aut aut aut |
| author_sort | Schliebusch, Oliver |
| author_variant | o s os h m hm r l rl |
| building | Verbundindex |
| bvnumber | BV023096015 |
| classification_rvk | ZN 4904 |
| collection | ZDB-2-ENG ebook |
| ctrlnum | (OCoLC)611758427 (DE-599)BVBBV023096015 |
| dewey-full | 621.395 004.165 |
| dewey-hundreds | 600 - Technology (Applied sciences) 000 - Computer science, information, general works |
| dewey-ones | 621 - Applied physics 004 - Computer science |
| dewey-raw | 621.395 004.165 |
| dewey-search | 621.395 004.165 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations 000 - Computer science, information, general works |
| discipline | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4020-5686-4 |
| format | Thesis Electronic eBook |
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| illustrated | Not Illustrated |
| index_date | 2024-07-02T19:43:05Z |
| indexdate | 2024-07-09T21:10:55Z |
| institution | BVB |
| isbn | 1402056850 9781402056857 9781402056864 |
| language | English |
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| spelling | Schliebusch, Oliver Verfasser aut Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers Dordrecht Springer 2007 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Dissertation Technische Hochschule Aachen 2006 Anwendungsspezifischer Prozessor (DE-588)7582430-9 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 gnd rswk-swf LISA Programmiersprache (DE-588)4795068-7 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Logiksynthese (DE-588)4348178-4 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content System-on-Chip (DE-588)4740357-3 s Anwendungsspezifischer Prozessor (DE-588)7582430-9 s Logiksynthese (DE-588)4348178-4 s Hardwarebeschreibungssprache (DE-588)4159102-1 s LISA Programmiersprache (DE-588)4795068-7 s DE-604 Meyr, Heinrich Verfasser aut Leupers, Rainer Verfasser aut https://doi.org/10.1007/978-1-4020-5686-4 Verlag Volltext |
| spellingShingle | Schliebusch, Oliver Meyr, Heinrich Leupers, Rainer Optimized ASIP synthesis from architecture description language models Anwendungsspezifischer Prozessor (DE-588)7582430-9 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd LISA Programmiersprache (DE-588)4795068-7 gnd System-on-Chip (DE-588)4740357-3 gnd Logiksynthese (DE-588)4348178-4 gnd |
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| title | Optimized ASIP synthesis from architecture description language models |
| title_auth | Optimized ASIP synthesis from architecture description language models |
| title_exact_search | Optimized ASIP synthesis from architecture description language models |
| title_exact_search_txtP | Optimized ASIP synthesis from architecture description language models |
| title_full | Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers |
| title_fullStr | Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers |
| title_full_unstemmed | Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers |
| title_short | Optimized ASIP synthesis from architecture description language models |
| title_sort | optimized asip synthesis from architecture description language models |
| topic | Anwendungsspezifischer Prozessor (DE-588)7582430-9 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd LISA Programmiersprache (DE-588)4795068-7 gnd System-on-Chip (DE-588)4740357-3 gnd Logiksynthese (DE-588)4348178-4 gnd |
| topic_facet | Anwendungsspezifischer Prozessor Hardwarebeschreibungssprache LISA Programmiersprache System-on-Chip Logiksynthese Hochschulschrift |
| url | https://doi.org/10.1007/978-1-4020-5686-4 |
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