Digital electronics and design with VHDL:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam [u.a.]
Elsevier, Morgan Kaufmann
2008
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXI, 693 S. Ill., graph. Darst. |
| ISBN: | 0123742706 9780123742704 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV023076945 | ||
| 003 | DE-604 | ||
| 005 | 20120418 | ||
| 007 | t | ||
| 008 | 080114s2008 ad|| j||| 00||| eng d | ||
| 010 | |a 007032518 | ||
| 020 | |a 0123742706 |c pbk. : £39.99 |9 0-12-374270-6 | ||
| 020 | |a 9780123742704 |c pbk. : £39.99 |9 978-0-12-374270-4 | ||
| 035 | |a (OCoLC)164570635 | ||
| 035 | |a (DE-599)GBV539590754 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-703 |a DE-1050 |a DE-634 |a DE-83 | ||
| 050 | 0 | |a TK7885.7 | |
| 082 | 0 | |a 621.39/2 |2 22 | |
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 084 | |a ZN 5620 |0 (DE-625)157469: |2 rvk | ||
| 100 | 1 | |a Pedroni, Volnei A. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Digital electronics and design with VHDL |c Volnei A. Pedroni |
| 264 | 1 | |a Amsterdam [u.a.] |b Elsevier, Morgan Kaufmann |c 2008 | |
| 300 | |a XXI, 693 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | |a Digital integrated circuits / Design and construction / Data processing | |
| 650 | 4 | |a Circuits intégrés numériques - Conception et construction - Informatique | |
| 650 | 4 | |a VHDL (Langage de description de matériel informatique) | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Digital integrated circuits |x Design and construction |x Data processing | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitalschaltung |0 (DE-588)4012295-5 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4173536-5 |a Patentschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Digitalschaltung |0 (DE-588)4012295-5 |D s |
| 689 | 0 | 1 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 856 | 4 | 2 | |m Digitalisierung UB Bayreuth |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016280024&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-016280024 | ||
Datensatz im Suchindex
| _version_ | 1804137322790256640 |
|---|---|
| adam_text | Contents
Preface
xix
1
Introduction
1
1.1
Historical
Notes
1
1.2
Analog
versus Digital
4
1.3
Bits,
Bytes, and Words
5
1.4
Digital Circuits
6
1.5
Combinational
Circuits versus
Sequential
Circuits
10
1.6
Integrated
Circuits
10
1.7
Printed
Circuit
Boards
11
1.8
Logic Values versus
Physical
Values
13
1.9
Nonprogrammable,
Programmable, and Hardware Programmable
15
1.10
Binary Waveforms
15
1.11
DC, AC, and Transient Responses
16
1.12
Programmable Logic Devices
18
1.13
Circuit Synthesis and Simulation with VHDL
19
1.14
Circuit Simulation with SPICE
19
1.15
Gate-Level versus Transistor-Level Analysis
20
2
Binary Representations
21
2.1
Binary Code
21
2.2
Octal and Hexadecimal Codes
24
2.3
Gray Code
24
2.4
BCD Code
25
2.5
Codes for Negative Numbers
26
2.5.1
Sign-Magnitude Code
26
2.5.2
One s Complement Code
26
vii
viii Contents
2.5.3
Binary
Addition 27
2.5.4
Two s Complement Code
28
2.6 Floating-Point
Representation
30
2.6.1
IEEE
754
Standard
30
2.6.2 Floating-Point
versus Integer
33
2.7
ASCnCode
35
2.7.1
ASCnCode
35
2.7.2
Extended
АЅСП
Code
36
2.8
Unicode
36
2.8.1
Unicode Characters
36
2.8.2
UTF-8 Encoding
36
2.8.3
UTF-16 Encoding
38
2.8.4
UTF-32 Encoding
39
2.9
Exercises
40
3
Binary Arithmetic
47
3.1
Unsigned Addition
47
3.2
Signed Addition and Subtraction
49
3.3
Shift Operations
52
3.4
Unsigned Multiplication
54
3.5
Signed Multiplication
56
3.6
Unsigned Division
57
3.7
Signed Division
58
3.8 Floating-Point
Addition and Subtraction
59
3.9 Floating-Point
Multiplication
61
3.10 Floating-Point
Division
62
3.11
Exercises
63
4
Introduction to Digital Circuits
69
4.1
Introduction to
MOS
Transistors
69
4.2
Inverter and CMOS Logic
71
4.2.1
Inverter
71
4.2.2
CMOS Logic
72
4.2.3
Power Consumption
73
4.2.4
Power-Delay Product
74
4.2.5
Logic Voltages
75
4.2.6
Timing Diagrams for Combinational Circuits
75
4.3
AND and
NAND
Gates
77
4.4
OR and NOR Gates
79
4.5
XOR and XNOR Gates
81
4.6
Modulo-2 Adder
83
4.7
Buffer
84
4.8
Tri-State Buffer
85
Contents
¡χ
4.9
Open-Drain Buffer
86
4.10 D-Type Flip-Flop 87
4.11
Shift Register
89
4.12
Counters
91
4.13
Pseudo-Random Sequence Generator
93
4.14
Exercises
94
5
Boolean Algebra
103
5.1
Boolean Algebra
103
5.2
Truth Tables
108
5.3
Minterms and SOP Equations
108
5.4
Maxterms and
POS
Equations
110
5.5
Standard Circuits for SOP and
POS
Equations
112
5.6
Karnaugh Maps
117
5.7
Large Karnaugh Maps
120
5.8
Other Function-Simplification Techniques
121
5.8.1
The Quine-McCluskey Algorithm
121
5.8.2
Other Simplification Algorithms
123
5.9
Propagation Delay and Glitches
123
5.10
Exercises
125
6
Line Codes
133
6.1
The Use of Line Codes
133
6.2
Parameters and Types of Line Codes
135
6.3
Unipolar Codes
137
6.4
Polar Codes
138
6.5
Bipolar Codes
139
6.6
Biphase/Manchester Codes
139
6.7
MLT Codes
140
6.8
mB/nB Codes
140
6.9
РАМ
Codes
143
6.10
Exercises
148
7
Error-Detecting/Correcfing Codes
153
7.1
Codes for Error Detection and Error Correction
153
7.2
Single Parity Check
(SPC)
Codes
154
7.3
Cyclic Redundancy Check
(CRC)
Codes
155
7.4
Hamming Codes
156
7.5
Reed-Solomon (RS) Codes
159
7.6
Interleaving
161
7.7
Convolutional Codes
163
χ
Contente
7.8
Viterbi Decoder
167
7.9
Turbo
Codes
170
7.10
Low Density Parity Check (LDPC) Codes
171
7.11
Exercises
174
8
Bipolar Transistor
181
8.1
Semiconductors
181
8.2
The Bipolar Junction Transistor
183
8.3
I-V Characteristics
184
8.4
DC Response
185
8.5
Transient Response
189
8.6
AC Response
191
8.7
Modern BJTs
192
8.7.1
Polysilicon-Emitter BJT
192
8.7.2
Heterojunction Bipolar Transistor
193
8.8
Exercises
194
9
MOS
Transistor
197
9.1
Semiconductors
197
9.2
The Field-Effect Transistor (MOSFET)
198
9.2.1
MOSFET Construction
198
9.2.2
MOSFET Operation
200
9.3
I-V Characteristics
201
9.4
DC Response
202
9.5
CMOS Inverter
205
9.6
Transient Response
207
9.7
AC Response
209
9.8
Modern MOSFETs
210
9.8.1
Strained Si-SiGe MOSFETs
210
9.8.2
SOI MOSFETs
211
9.8.3
BiCMOS Technologies
211
9.9
Exercises
212
10
Logic Families and I/Os
219
10.1
BJT-Based Logic Families
219
10.2
Diode-Transistor Logic
220
10.3
Transistor-Transistor Logic
(TTL)
221
10.3.1
TTL
Circuit
221
10.3.2
Temperature Ranges
222
10.3.3
TTL
Versions
223
10.3.4
Fan-In and Fan-Out
224
10.3.5
Supply Voltage, Signal Voltages, and
Noise Margin
224
Contents xi
10.4 Emitter-Coupled Logic 225
10.5 MOS-Based Logic
Families
226
10.6 CMOS Logic 227
10.6.1
CMOS Circuits
227
10.6.2
НС
and HCT
CMOS Families
227
10.6.3 CMOS-TTL Interface 228
10.6.4
Fan-In and Fan-Out
229
10.6.5
Supply Voltage,
Signal
Voltages, and Noise Margin
229
10.6.6
Low-Voltage CMOS
229
10.6.7
Power Consumption
230
10.6.8
Power-Delay Product
230
10.7
Other Static
MOS
Architectures
230
10.7.1
Pseudo-nMOS Logic
230
10.7.2
Transmission-Gate Logic
231
10.7.3
BiCMOS Logic
232
10.8
Dynamic
MOS
Architectures
232
10.8.1
Dynamic Logic
232
10.8.2
Domino Logic
233
10.8.3
Clocked-CMOS (C2MOS) Logic
234
10.9
Modern I/O Standards
235
10.9.1
TTL
and LVTTL Standards
236
10.9.2
CMOS and LVCMOS Standards
237
10.9.3
SSTL Standards
240
10.9.4
HSTL Standards
244
10.9.5
LVDS Standard
244
10.9.6
LVDS Example: PCI Express Bus
246
10.10
Exercises
248
11
Combinational Logic Circuits
257
11.1
Combinational versus Sequential Logic
257
11.2
Logical versus Arithmetic Circuits
258
11.3
Fundamental Logic Gates
258
11.4
Compound Gates
259
11.4.1
SOP-Based CMOS Circuit
260
11.4.2
POS-Based CMOS Circuit
260
11.5
Encoders and Decoders
262
11.5.1
Address Decoder
262
11.5.2
Address Decoder with Enable
264
11.5.3
Large Address Decoders
264
11.5.4
Timing Diagrams
265
11.5.5
Address Encoder
266
11.6
Multiplexer
268
11.6.1
Basic Multiplexers
269
11.6.2
Large Multiplexers
270
11.6.3
Timing Diagrams
271
xii Contents
11.7
Parity
Detector
272
11.8
Priority Encoder
272
11.9
Binary Sorter
274
11.10
Shifters
275
11.11
Nonoverlapping
Clock Generators
277
11.12
Short-Pulse Generators
278
11.13 Schmitt
Triggers
279
11.14
Memories
280
11.15
Exercises
281
11.16
Exercises with VHDL
287
11.17
Exercises with SPICE
287
12
Combinational Arithmetic Circuits
289
12.1
Arithmetic versus Logic Circuits
289
12.2
Basic Adders
290
12.2.1
Full-Adder Unit
290
12.2.2
Carry-Ripple Adder
291
12.3
Fast Adders
293
12.3.1
Generate, Propagate, and Kill Signals
293
12.3.2
Approaches for Fast Adders
294
12.3.3
Manchester Carry-Chain Adder
295
12.3.4
Carry-Skip Adder
296
12.3.5
Carry-Select Adder
297
12.3.6
Carry-Lookahead Adder
297
12.4
Bit-Serial Adder
300
12.5
Signed Adders/Subtracters
301
12.5.1
Signed versus Unsigned Adders
301
12.5.2
Subtracters
301
12.6
Incrementer,
Décrémenter,
and Two s Complementer
303
12.6.1
Incrementer
303
12.6.2
Décrémenter
303
12.6.3
Two s Complementer
303
12.7
Comparators
304
12.8
Arithmetic-Logic Unit
306
12.9
Multipliers
307
12.9.1
Parallel Unsigned Multiplier
308
12.9.2
Parallel Signed Multiplier
309
12.9.3
Parallel-Serial Unsigned Multiplier
309
12.9.4
ALU-Based Unsigned and Signed Multipliers
311
12.10
Dividers
312
12.11
Exercises
312
12.12
Exercises with VHDL
317
12.13
Exercises with SPICE
317
Contents xiii
13 Registers 319
13.1
Sequential
versus
Combinational Logic
319
13.2
SR
Latch
320
13.3
D
Latch
320
13.3.1
DL
Operation
320
13.3.2
Time-Related Parameters
322
13.3.3
DL
Circuits
323
13.3.4
Static Multiplexer-Based DLs
324
13.3.5
Static RAM-Type DLs
326
13.3.6
Static Current-Mode DLs
327
13.3.7
Dynamic DLs
327
13.4
DFlip-Flop
329
13.4.1
DFF Operation
329
13.4.2
Time-Related Parameters
330
13.4.3
DFF Construction Approaches
331
13.4.4
DFF Circuits
332
13.5
Master-Slave
D
Flip-Flops 332
13.5.1
Classical Master-Slave DFFs
332
13.5.2
Clock Skew and Slow Clock Transitions
334
13.5.3
Special Master-Slave DFFs
335
13.6
Pulse-Based
D
Flip-Flops 338
13.6.1
Short-Pulse Generators
338
13.6.2
Pulse-Based DFFs
339
13.7
Dual-Edge
D
Flip-Flops 342
13.8
Statistically Low-Power
D
Flip-Flops 343
13.9
D
Flip-Flop
Control
Ports 344
13.9.1 DFF
with Reset and Preset
344
13.9.2
DFF with Enable
345
13.9.3
DFF with Clear
345
13.10
Τ
Flip-Flop 345
13.11
Exercises
347
13.12
Exercises with SPICE
352
14
Sequential Circuits
353
14.1
Shift Registers
353
14.2
Synchronous Counters
355
14.3
Asynchronous Counters
368
14.4
Signal Generators
371
14.5
Frequency Dividers
374
14.6
PLL
and Prescalers
377
14.6.1
Basic
PLL
378
14.6.2
Prescaler
379
14.6.3
Programmable
PLL
381
xiv Contents
14.7
Pseudo-Random Sequence Generators
381
14.8
Scramblers and Descramblers
383
14.8.1
Additive Scrambler-Descrambler
383
14.8.2
Multiplicative Scrambler-Descrambler
384
14.9
Exercises
386
14.10
Exercises with VHDL
395
14.11
Exercises with SPICE
395
15
Finite State Machines
397
15.1
Finite State Machine Model
397
15.2
Design of Finite State Machines
399
15.3
System Resolution and Glitches
410
15.4
Design of Large Finite State Machines
411
15.5
Design of Finite State Machines with Complex
Combinational Logic
414
15.6
Multi-Machine Designs
417
15.7
Generic Signal Generator Design Technique
419
15.8
Design of Symmetric-Phase Frequency Dividers
421
15.9
Finite State Machine Encoding Styles
423
15.10
Exercises
426
15.11
Exercises with VHDL
432
16
Volatile Memories
433
16.1
Memory Types
433
16.2
Static Random Access Memory (SRAM)
434
16.3
Dual and Quad Data Rate (DDR, QDR) SRAMs
438
16.4
Dynamic Random Access Memory (DRAM)
439
16.5
Synchronous DRAM (SDRAM)
442
16.6
Dual Data Rate (DDR, DDR2, DDR3)
SDRAMs 444
16.7
Content-Addressable Memory (CAM) for Cache Memories
446
16.8
Exercises
447
17
Nonvolatile Memories
451
17.1
Memory Types
451
17.2
Mask-Programmed ROM (MP-ROM)
452
17.3
Опе-Гіте
-Programmable
ROM (OTP-ROM)
453
17.4
Electrically Programmable ROM
(EPROM)
453
17.5
Electrically Erasable Programmable ROM
(EEPROM)
455
17.6
Flash Memory
456
17.7
Next-Generation Nonvolatile Memories
461
17.7.1
Ferroelectric RAM
(FRAM)
462
Contents xv
17.7.2 Magnetoresistive RAM (MRAM) 463
17.7.3
Phase-Change RAM (PRAM)
464
17.8
Exercises
465
18
Programmable
Logic Devices 467
18.1
The Concept of Programmable
Logic Devices 467
18.2 SPLDs 468
18.2.1 PAL Devices 468
18.2.2
PLA
Devices 470
18.2.3
GAL
Devices 471
18.3 CPLDs 471
18.3.1
Architecture
471
18.3.2 Xilinx CPLDs 475
18.3.3
Altera
CPLDs 477
18.4 FPGAs 478
18.4.1 FPGA Technology 478
18.4.2 FPGA
Architecture
479
18.4.3 Virtex CLB
and Slice
480
18.4.4 Stratix LAB and ALM 481
18.4.5 RAM Blocks 481
18.4.6 DSP Blocks 482
18.4.7
Clock
Management 483
18.4.8 I/O Standards 485
18.4.9
Additional
Features 485
18.4.10
Summary and Comparison
485
18.5
Exercises
486
19 VHDL
Summary
491
19.1
About VHDL
492
19.2 Code
Structure
492
19.3 Fundamental VHDL
Packages
495
19.4
Predefined Data Types
496
19.5 User
Defined Data Types
498
19.6 Operators 498
19.7 Attributes 500
19.8
Concurrent
versus
Sequential Code
501
19.9
Concurrent Code (WHEN, GENERATE)
502
19.10
Sequential Code (IF, CASE, LOOP, WAIT)
503
19.11
Objects (CONSTANT, SIGNAL, VARIABLE)
506
19.12
Packages
509
19.13
Components
510
19.14
Functions
513
xvi Contents
19.15
Procedures
514
19.16 VHDL Template
for FSMs
516
19.17
Exercises
520
20 VHDL
Design of Combinational Logic Circuits
523
20.1
Generic Address Decoder
523
20.2
BCD-to-SSD Conversion Function
525
20.3
Generic Multiplexer
527
20.4
Generic Priority Encoder
529
20.5
Design of ROM Memory
530
20.6
Design of Synchronous RAM Memories
532
20.7
Exercises
536
21
VHDL Design of Combinational Arithmetic Circuits
539
21.1
Carry-Ripple Adder
539
21.2
Carry-Lookahead Adder
540
21.3
Signed and Unsigned Adders/Subtracters
543
21.4
Signed and Unsigned Multipliers/Dividers
545
21.5 ALU 547
21.6
Exercises
550
22
VHDL Design of Sequential Circuits
553
22.1
Shift Register with Load
553
22.2
Switch Debouncer
556
22.3
Timer
558
22.4
Fibonacci Series Generator
561
22.5
Frequency Meters
562
22.6
Neural Networks
565
22.7
Exercises
571
23
VHDL Design of State Machines
573
23.1
String Detector
573
23.2
Universal Signal Generator
575
23.3
Car Alarm
578
23.4
LCD Driver
588
23.5
Exercises
597
24
Simulation with VHDL Testbenches
601
24.1
Synthesis versus Simulation
601
24.2
Testbenen
Types
602
24.3
Stimulus Generation
603
Contents xvii
24.4
Testing
the Stimuli
605
24.5
Testbench Template
607
24.6
Writing Type I Testbenches
607
24.7
Writing Type
Π
Testbenches
612
24.8
Writing Type
Ш
Testbenches
615
24.9
Writing Type IV Testbenches
615
24.10
Exercises
618
25
Simulation with SPICE
621
25.1
About SPICE
621
25.2
Types of Analysis
622
25.3
Basic Structure of SPICE Code
623
25.4
Declarations of Electronic Devices
625
25.5
Declarations of Independent DC Sources
630
25.6
Declarations of Independent AC Sources
631
25.7
Declarations of Dependent Sources
635
25.8
SPICE Inputs and Outputs
636
25.9
DC Response Examples
638
25.10
Transient Response Examples
641
25.11
AC Response Example
644
25.12
Monte Carlo Analysis
645
25.13
Subcircuits
648
25.14
Exercises Involving Combinational Logic Circuits
650
25.15
Exercises Involving Combinational Arithmetic Circuits
652
25.16
Exercises Involving Registers
654
25.17
Exercises Involving Sequential Circuits
655
APPENDIX A ModelSim Tutorial
657
APPENDIX
В
PSpice Tutorial
667
References
673
Index
679
|
| adam_txt |
Contents
Preface
xix
1
Introduction
1
1.1
Historical
Notes
1
1.2
Analog
versus Digital
4
1.3
Bits,
Bytes, and Words
5
1.4
Digital Circuits
6
1.5
Combinational
Circuits versus
Sequential
Circuits
10
1.6
Integrated
Circuits
10
1.7
Printed
Circuit
Boards
11
1.8
Logic Values versus
Physical
Values
13
1.9
Nonprogrammable,
Programmable, and Hardware Programmable
15
1.10
Binary Waveforms
15
1.11
DC, AC, and Transient Responses
16
1.12
Programmable Logic Devices
18
1.13
Circuit Synthesis and Simulation with VHDL
19
1.14
Circuit Simulation with SPICE
19
1.15
Gate-Level versus Transistor-Level Analysis
20
2
Binary Representations
21
2.1
Binary Code
21
2.2
Octal and Hexadecimal Codes
24
2.3
Gray Code
24
2.4
BCD Code
25
2.5
Codes for Negative Numbers
26
2.5.1
Sign-Magnitude Code
26
2.5.2
One's Complement Code
26
vii
viii Contents
2.5.3
Binary
Addition 27
2.5.4
Two's Complement Code
28
2.6 Floating-Point
Representation
30
2.6.1
IEEE
754
Standard
30
2.6.2 Floating-Point
versus Integer
33
2.7
ASCnCode
35
2.7.1
ASCnCode
35
2.7.2
Extended
АЅСП
Code
36
2.8
Unicode
36
2.8.1
Unicode Characters
36
2.8.2
UTF-8 Encoding
36
2.8.3
UTF-16 Encoding
38
2.8.4
UTF-32 Encoding
39
2.9
Exercises
40
3
Binary Arithmetic
47
3.1
Unsigned Addition
47
3.2
Signed Addition and Subtraction
49
3.3
Shift Operations
52
3.4
Unsigned Multiplication
54
3.5
Signed Multiplication
56
3.6
Unsigned Division
57
3.7
Signed Division
58
3.8 Floating-Point
Addition and Subtraction
59
3.9 Floating-Point
Multiplication
61
3.10 Floating-Point
Division
62
3.11
Exercises
63
4
Introduction to Digital Circuits
69
4.1
Introduction to
MOS
Transistors
69
4.2
Inverter and CMOS Logic
71
4.2.1
Inverter
71
4.2.2
CMOS Logic
72
4.2.3
Power Consumption
73
4.2.4
Power-Delay Product
74
4.2.5
Logic Voltages
75
4.2.6
Timing Diagrams for Combinational Circuits
75
4.3
AND and
NAND
Gates
77
4.4
OR and NOR Gates
79
4.5
XOR and XNOR Gates
81
4.6
Modulo-2 Adder
83
4.7
Buffer
84
4.8
Tri-State Buffer
85
Contents
¡χ
4.9
Open-Drain Buffer
86
4.10 D-Type Flip-Flop 87
4.11
Shift Register
89
4.12
Counters
91
4.13
Pseudo-Random Sequence Generator
93
4.14
Exercises
94
5
Boolean Algebra
103
5.1
Boolean Algebra
103
5.2
Truth Tables
108
5.3
Minterms and SOP Equations
108
5.4
Maxterms and
POS
Equations
110
5.5
Standard Circuits for SOP and
POS
Equations
112
5.6
Karnaugh Maps
117
5.7
Large Karnaugh Maps
120
5.8
Other Function-Simplification Techniques
121
5.8.1
The Quine-McCluskey Algorithm
121
5.8.2
Other Simplification Algorithms
123
5.9
Propagation Delay and Glitches
123
5.10
Exercises
125
6
Line Codes
133
6.1
The Use of Line Codes
133
6.2
Parameters and Types of Line Codes
135
6.3
Unipolar Codes
137
6.4
Polar Codes
138
6.5
Bipolar Codes
139
6.6
Biphase/Manchester Codes
139
6.7
MLT Codes
140
6.8
mB/nB Codes
140
6.9
РАМ
Codes
143
6.10
Exercises
148
7
Error-Detecting/Correcfing Codes
153
7.1
Codes for Error Detection and Error Correction
153
7.2
Single Parity Check
(SPC)
Codes
154
7.3
Cyclic Redundancy Check
(CRC)
Codes
155
7.4
Hamming Codes
156
7.5
Reed-Solomon (RS) Codes
159
7.6
Interleaving
161
7.7
Convolutional Codes
163
χ
Contente
7.8
Viterbi Decoder
167
7.9
Turbo
Codes
170
7.10
Low Density Parity Check (LDPC) Codes
171
7.11
Exercises
174
8
Bipolar Transistor
181
8.1
Semiconductors
181
8.2
The Bipolar Junction Transistor
183
8.3
I-V Characteristics
184
8.4
DC Response
185
8.5
Transient Response
189
8.6
AC Response
191
8.7
Modern BJTs
192
8.7.1
Polysilicon-Emitter BJT
192
8.7.2
Heterojunction Bipolar Transistor
193
8.8
Exercises
194
9
MOS
Transistor
197
9.1
Semiconductors
197
9.2
The Field-Effect Transistor (MOSFET)
198
9.2.1
MOSFET Construction
198
9.2.2
MOSFET Operation
200
9.3
I-V Characteristics
201
9.4
DC Response
202
9.5
CMOS Inverter
205
9.6
Transient Response
207
9.7
AC Response
209
9.8
Modern MOSFETs
210
9.8.1
Strained Si-SiGe MOSFETs
210
9.8.2
SOI MOSFETs
211
9.8.3
BiCMOS Technologies
211
9.9
Exercises
212
10
Logic Families and I/Os
219
10.1
BJT-Based Logic Families
219
10.2
Diode-Transistor Logic
220
10.3
Transistor-Transistor Logic
(TTL)
221
10.3.1
TTL
Circuit
221
10.3.2
Temperature Ranges
222
10.3.3
TTL
Versions
223
10.3.4
Fan-In and Fan-Out
224
10.3.5
Supply Voltage, Signal Voltages, and
Noise Margin
224
Contents xi
10.4 Emitter-Coupled Logic 225
10.5 MOS-Based Logic
Families
226
10.6 CMOS Logic 227
10.6.1
CMOS Circuits
227
10.6.2
НС
and HCT
CMOS Families
227
10.6.3 CMOS-TTL Interface 228
10.6.4
Fan-In and Fan-Out
229
10.6.5
Supply Voltage,
Signal
Voltages, and Noise Margin
229
10.6.6
Low-Voltage CMOS
229
10.6.7
Power Consumption
230
10.6.8
Power-Delay Product
230
10.7
Other Static
MOS
Architectures
230
10.7.1
Pseudo-nMOS Logic
230
10.7.2
Transmission-Gate Logic
231
10.7.3
BiCMOS Logic
232
10.8
Dynamic
MOS
Architectures
232
10.8.1
Dynamic Logic
232
10.8.2
Domino Logic
233
10.8.3
Clocked-CMOS (C2MOS) Logic
234
10.9
Modern I/O Standards
235
10.9.1
TTL
and LVTTL Standards
236
10.9.2
CMOS and LVCMOS Standards
237
10.9.3
SSTL Standards
240
10.9.4
HSTL Standards
244
10.9.5
LVDS Standard
244
10.9.6
LVDS Example: PCI Express Bus
246
10.10
Exercises
248
11
Combinational Logic Circuits
257
11.1
Combinational versus Sequential Logic
257
11.2
Logical versus Arithmetic Circuits
258
11.3
Fundamental Logic Gates
258
11.4
Compound Gates
259
11.4.1
SOP-Based CMOS Circuit
260
11.4.2
POS-Based CMOS Circuit
260
11.5
Encoders and Decoders
262
11.5.1
Address Decoder
262
11.5.2
Address Decoder with Enable
264
11.5.3
Large Address Decoders
264
11.5.4
Timing Diagrams
265
11.5.5
Address Encoder
266
11.6
Multiplexer
268
11.6.1
Basic Multiplexers
269
11.6.2
Large Multiplexers
270
11.6.3
Timing Diagrams
271
xii Contents
11.7
Parity
Detector
272
11.8
Priority Encoder
272
11.9
Binary Sorter
274
11.10
Shifters
275
11.11
Nonoverlapping
Clock Generators
277
11.12
Short-Pulse Generators
278
11.13 Schmitt
Triggers
279
11.14
Memories
280
11.15
Exercises
281
11.16
Exercises with VHDL
287
11.17
Exercises with SPICE
287
12
Combinational Arithmetic Circuits
289
12.1
Arithmetic versus Logic Circuits
289
12.2
Basic Adders
290
12.2.1
Full-Adder Unit
290
12.2.2
Carry-Ripple Adder
291
12.3
Fast Adders
293
12.3.1
Generate, Propagate, and Kill Signals
293
12.3.2
Approaches for Fast Adders
294
12.3.3
Manchester Carry-Chain Adder
295
12.3.4
Carry-Skip Adder
296
12.3.5
Carry-Select Adder
297
12.3.6
Carry-Lookahead Adder
297
12.4
Bit-Serial Adder
300
12.5
Signed Adders/Subtracters
301
12.5.1
Signed versus Unsigned Adders
301
12.5.2
Subtracters
301
12.6
Incrementer,
Décrémenter,
and Two's Complementer
303
12.6.1
Incrementer
303
12.6.2
Décrémenter
303
12.6.3
Two's Complementer
303
12.7
Comparators
304
12.8
Arithmetic-Logic Unit
306
12.9
Multipliers
307
12.9.1
Parallel Unsigned Multiplier
308
12.9.2
Parallel Signed Multiplier
309
12.9.3
Parallel-Serial Unsigned Multiplier
309
12.9.4
ALU-Based Unsigned and Signed Multipliers
311
12.10
Dividers
312
12.11
Exercises
312
12.12
Exercises with VHDL
317
12.13
Exercises with SPICE
317
Contents xiii
13 Registers 319
13.1
Sequential
versus
Combinational Logic
319
13.2
SR
Latch
320
13.3
D
Latch
320
13.3.1
DL
Operation
320
13.3.2
Time-Related Parameters
322
13.3.3
DL
Circuits
323
13.3.4
Static Multiplexer-Based DLs
324
13.3.5
Static RAM-Type DLs
326
13.3.6
Static Current-Mode DLs
327
13.3.7
Dynamic DLs
327
13.4
DFlip-Flop
329
13.4.1
DFF Operation
329
13.4.2
Time-Related Parameters
330
13.4.3
DFF Construction Approaches
331
13.4.4
DFF Circuits
332
13.5
Master-Slave
D
Flip-Flops 332
13.5.1
Classical Master-Slave DFFs
332
13.5.2
Clock Skew and Slow Clock Transitions
334
13.5.3
Special Master-Slave DFFs
335
13.6
Pulse-Based
D
Flip-Flops 338
13.6.1
Short-Pulse Generators
338
13.6.2
Pulse-Based DFFs
339
13.7
Dual-Edge
D
Flip-Flops 342
13.8
Statistically Low-Power
D
Flip-Flops 343
13.9
D
Flip-Flop
Control
Ports 344
13.9.1 DFF
with Reset and Preset
344
13.9.2
DFF with Enable
345
13.9.3
DFF with Clear
345
13.10
Τ
Flip-Flop 345
13.11
Exercises
347
13.12
Exercises with SPICE
352
14
Sequential Circuits
353
14.1
Shift Registers
353
14.2
Synchronous Counters
355
14.3
Asynchronous Counters
368
14.4
Signal Generators
371
14.5
Frequency Dividers
374
14.6
PLL
and Prescalers
377
14.6.1
Basic
PLL
378
14.6.2
Prescaler
379
14.6.3
Programmable
PLL
381
xiv Contents
14.7
Pseudo-Random Sequence Generators
381
14.8
Scramblers and Descramblers
383
14.8.1
Additive Scrambler-Descrambler
383
14.8.2
Multiplicative Scrambler-Descrambler
384
14.9
Exercises
386
14.10
Exercises with VHDL
395
14.11
Exercises with SPICE
395
15
Finite State Machines
397
15.1
Finite State Machine Model
397
15.2
Design of Finite State Machines
399
15.3
System Resolution and Glitches
410
15.4
Design of Large Finite State Machines
411
15.5
Design of Finite State Machines with Complex
Combinational Logic
414
15.6
Multi-Machine Designs
417
15.7
Generic Signal Generator Design Technique
419
15.8
Design of Symmetric-Phase Frequency Dividers
421
15.9
Finite State Machine Encoding Styles
423
15.10
Exercises
426
15.11
Exercises with VHDL
432
16
Volatile Memories
433
16.1
Memory Types
433
16.2
Static Random Access Memory (SRAM)
434
16.3
Dual and Quad Data Rate (DDR, QDR) SRAMs
438
16.4
Dynamic Random Access Memory (DRAM)
439
16.5
Synchronous DRAM (SDRAM)
442
16.6
Dual Data Rate (DDR, DDR2, DDR3)
SDRAMs 444
16.7
Content-Addressable Memory (CAM) for Cache Memories
446
16.8
Exercises
447
17
Nonvolatile Memories
451
17.1
Memory Types
451
17.2
Mask-Programmed ROM (MP-ROM)
452
17.3
Опе-Гіте
-Programmable
ROM (OTP-ROM)
453
17.4
Electrically Programmable ROM
(EPROM)
453
17.5
Electrically Erasable Programmable ROM
(EEPROM)
455
17.6
Flash Memory
456
17.7
Next-Generation Nonvolatile Memories
461
17.7.1
Ferroelectric RAM
(FRAM)
462
Contents xv
17.7.2 Magnetoresistive RAM (MRAM) 463
17.7.3
Phase-Change RAM (PRAM)
464
17.8
Exercises
465
18
Programmable
Logic Devices 467
18.1
The Concept of Programmable
Logic Devices 467
18.2 SPLDs 468
18.2.1 PAL Devices 468
18.2.2
PLA
Devices 470
18.2.3
GAL
Devices 471
18.3 CPLDs 471
18.3.1
Architecture
471
18.3.2 Xilinx CPLDs 475
18.3.3
Altera
CPLDs 477
18.4 FPGAs 478
18.4.1 FPGA Technology 478
18.4.2 FPGA
Architecture
479
18.4.3 Virtex CLB
and Slice
480
18.4.4 Stratix LAB and ALM 481
18.4.5 RAM Blocks 481
18.4.6 DSP Blocks 482
18.4.7
Clock
Management 483
18.4.8 I/O Standards 485
18.4.9
Additional
Features 485
18.4.10
Summary and Comparison
485
18.5
Exercises
486
19 VHDL
Summary
491
19.1
About VHDL
492
19.2 Code
Structure
492
19.3 Fundamental VHDL
Packages
495
19.4
Predefined Data Types
496
19.5 User
Defined Data Types
498
19.6 Operators 498
19.7 Attributes 500
19.8
Concurrent
versus
Sequential Code
501
19.9
Concurrent Code (WHEN, GENERATE)
502
19.10
Sequential Code (IF, CASE, LOOP, WAIT)
503
19.11
Objects (CONSTANT, SIGNAL, VARIABLE)
506
19.12
Packages
509
19.13
Components
510
19.14
Functions
513
xvi Contents
19.15
Procedures
514
19.16 VHDL Template
for FSMs
516
19.17
Exercises
520
20 VHDL
Design of Combinational Logic Circuits
523
20.1
Generic Address Decoder
523
20.2
BCD-to-SSD Conversion Function
525
20.3
Generic Multiplexer
527
20.4
Generic Priority Encoder
529
20.5
Design of ROM Memory
530
20.6
Design of Synchronous RAM Memories
532
20.7
Exercises
536
21
VHDL Design of Combinational Arithmetic Circuits
539
21.1
Carry-Ripple Adder
539
21.2
Carry-Lookahead Adder
540
21.3
Signed and Unsigned Adders/Subtracters
543
21.4
Signed and Unsigned Multipliers/Dividers
545
21.5 ALU 547
21.6
Exercises
550
22
VHDL Design of Sequential Circuits
553
22.1
Shift Register with Load
553
22.2
Switch Debouncer
556
22.3
Timer
558
22.4
Fibonacci Series Generator
561
22.5
Frequency Meters
562
22.6
Neural Networks
565
22.7
Exercises
571
23
VHDL Design of State Machines
573
23.1
String Detector
573
23.2
"Universal" Signal Generator
575
23.3
Car Alarm
578
23.4
LCD Driver
588
23.5
Exercises
597
24
Simulation with VHDL Testbenches
601
24.1
Synthesis versus Simulation
601
24.2
Testbenen
Types
602
24.3
Stimulus Generation
603
Contents xvii
24.4
Testing
the Stimuli
605
24.5
Testbench Template
607
24.6
Writing Type I Testbenches
607
24.7
Writing Type
Π
Testbenches
612
24.8
Writing Type
Ш
Testbenches
615
24.9
Writing Type IV Testbenches
615
24.10
Exercises
618
25
Simulation with SPICE
621
25.1
About SPICE
621
25.2
Types of Analysis
622
25.3
Basic Structure of SPICE Code
623
25.4
Declarations of Electronic Devices
625
25.5
Declarations of Independent DC Sources
630
25.6
Declarations of Independent AC Sources
631
25.7
Declarations of Dependent Sources
635
25.8
SPICE Inputs and Outputs
636
25.9
DC Response Examples
638
25.10
Transient Response Examples
641
25.11
AC Response Example
644
25.12
Monte Carlo Analysis
645
25.13
Subcircuits
648
25.14
Exercises Involving Combinational Logic Circuits
650
25.15
Exercises Involving Combinational Arithmetic Circuits
652
25.16
Exercises Involving Registers
654
25.17
Exercises Involving Sequential Circuits
655
APPENDIX A ModelSim Tutorial
657
APPENDIX
В
PSpice Tutorial
667
References
673
Index
679 |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Pedroni, Volnei A. |
| author_facet | Pedroni, Volnei A. |
| author_role | aut |
| author_sort | Pedroni, Volnei A. |
| author_variant | v a p va vap |
| building | Verbundindex |
| bvnumber | BV023076945 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 ZN 4904 ZN 5620 |
| ctrlnum | (OCoLC)164570635 (DE-599)GBV539590754 |
| dewey-full | 621.39/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| genre | (DE-588)4173536-5 Patentschrift gnd-content |
| genre_facet | Patentschrift |
| id | DE-604.BV023076945 |
| illustrated | Illustrated |
| index_date | 2024-07-02T19:35:30Z |
| indexdate | 2024-07-09T21:10:27Z |
| institution | BVB |
| isbn | 0123742706 9780123742704 |
| language | English |
| lccn | 007032518 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016280024 |
| oclc_num | 164570635 |
| open_access_boolean | |
| owner | DE-703 DE-1050 DE-634 DE-83 |
| owner_facet | DE-703 DE-1050 DE-634 DE-83 |
| physical | XXI, 693 S. Ill., graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Elsevier, Morgan Kaufmann |
| record_format | marc |
| spelling | Pedroni, Volnei A. Verfasser aut Digital electronics and design with VHDL Volnei A. Pedroni Amsterdam [u.a.] Elsevier, Morgan Kaufmann 2008 XXI, 693 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier VHDL (Computer hardware description language) Digital integrated circuits / Design and construction / Data processing Circuits intégrés numériques - Conception et construction - Informatique VHDL (Langage de description de matériel informatique) Datenverarbeitung Digital integrated circuits Design and construction Data processing VHDL (DE-588)4254792-1 gnd rswk-swf Digitalschaltung (DE-588)4012295-5 gnd rswk-swf (DE-588)4173536-5 Patentschrift gnd-content Digitalschaltung (DE-588)4012295-5 s VHDL (DE-588)4254792-1 s DE-604 Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016280024&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Pedroni, Volnei A. Digital electronics and design with VHDL VHDL (Computer hardware description language) Digital integrated circuits / Design and construction / Data processing Circuits intégrés numériques - Conception et construction - Informatique VHDL (Langage de description de matériel informatique) Datenverarbeitung Digital integrated circuits Design and construction Data processing VHDL (DE-588)4254792-1 gnd Digitalschaltung (DE-588)4012295-5 gnd |
| subject_GND | (DE-588)4254792-1 (DE-588)4012295-5 (DE-588)4173536-5 |
| title | Digital electronics and design with VHDL |
| title_auth | Digital electronics and design with VHDL |
| title_exact_search | Digital electronics and design with VHDL |
| title_exact_search_txtP | Digital electronics and design with VHDL |
| title_full | Digital electronics and design with VHDL Volnei A. Pedroni |
| title_fullStr | Digital electronics and design with VHDL Volnei A. Pedroni |
| title_full_unstemmed | Digital electronics and design with VHDL Volnei A. Pedroni |
| title_short | Digital electronics and design with VHDL |
| title_sort | digital electronics and design with vhdl |
| topic | VHDL (Computer hardware description language) Digital integrated circuits / Design and construction / Data processing Circuits intégrés numériques - Conception et construction - Informatique VHDL (Langage de description de matériel informatique) Datenverarbeitung Digital integrated circuits Design and construction Data processing VHDL (DE-588)4254792-1 gnd Digitalschaltung (DE-588)4012295-5 gnd |
| topic_facet | VHDL (Computer hardware description language) Digital integrated circuits / Design and construction / Data processing Circuits intégrés numériques - Conception et construction - Informatique VHDL (Langage de description de matériel informatique) Datenverarbeitung Digital integrated circuits Design and construction Data processing VHDL Digitalschaltung Patentschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016280024&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT pedronivolneia digitalelectronicsanddesignwithvhdl |