Transactional memory:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
[San Rafael, Calif.]
Morgan & Claypool Publishers
2007
|
| Ausgabe: | 1. ed. |
| Schriftenreihe: | Synthesis lectures on computer architecture
2 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIII, 211 S. |
| ISBN: | 9781598291247 |
Internformat
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| 245 | 1 | 0 | |a Transactional memory |c James R. Larus ; Ravi Rajwar |
| 250 | |a 1. ed. | ||
| 264 | 1 | |a [San Rafael, Calif.] |b Morgan & Claypool Publishers |c 2007 | |
| 300 | |a XIII, 211 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Synthesis lectures on computer architecture |v 2 | |
| 650 | 4 | |a Parallel programming (Computer science) | |
| 650 | 4 | |a Synchronization | |
| 650 | 4 | |a Threads (Computer programs) | |
| 650 | 4 | |a Transaction systems (Computer systems) | |
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Datensatz im Suchindex
| _version_ | 1804137251859333120 |
|---|---|
| adam_text | Contents
1.
introduction
........
,
.........................................................1
1.1
Motivation
..............................................................1
1.1.1
Single-Chip Parallel Computers
....................................1
1.1.2
Difficulty of Parallel Programming
.................................2
1.1.3
Parallel Programming Abstractions
.................................3
1.2
Database Systems and Transactions
........................................5
1.2.1
What Is a Transaction?
............................................6
1.3
Transactional Memory
....................................................7
1.3.1
Differences
.......................................................9
1.4
This Book
...............................................................9
2.
Programming Transactional Memory
..........................................14
2.1
Basic Transactional Constructs
...........................................15
2.1.1
Atomic Block
...................................................16
2.1.2
Semantics
.......................................................19
Database Correctness Criteria
.................................19
Operational Semantics
........................................20
Non-Transactional Accesses
....................................20
Linearizability
................................................23
2.1.3
Declarations
.....................................................23
2.1.4
Retry
...........................................................24
2.1.5
OrElse
..........................................................25
2.2
Transaction Design Space
................................................26
2.2.1
Weak and Strong Isolation
........................................26
2.2.2
Nested Transactions
..............................................28
2.2.3
Exceptions
......................................................31
2.3
Transactional Memory System Taxonomy
.................................32
2.3.1
Transaction Granularity
..........................................32
2.3.2
Direct and Deferred Update
......................................33
2.3.3
Concurrency Control
.............................................35
2.3.4
Early and Late Conflict Detection
.................................37
2.3.5
Detecting and Tolerating Conflicts
................................39
CONTENTS
2.3.6 Contention Management.........................................43
2.4 Programming and
Execution
Environment................................44
2.4.1
Communication
.................................................44
2.4.2 System
Abstractions
.............................................45
2.4.3
Existing
Programming
Languages.................................
46
2.4.4 Libraries........................................................47
2.4.5 Svnchronization Primitives.......................................47
2.4.6
Debugging
......................................................47
2.4.7 Performance Isolation............................................48
2.4.8 HTM Implementation...........................................48
$. Software Transactional Memory..............................................53
3.1
Introduction
............................................................53
3.1.1
Chapter Overview
...............................................53
3.2
A Few Words on Language
..............................................54
3.3
STM Precursors
........................................................55
3.3.1
Lomet, LDRS
77................................................55
Implementation
..............................................58
3.3.2
Shavit, Touitou, PODC
1995.....................................58
Implementation
..............................................59
3.3.3
Other Precursors
.................................................63
3.4
Deferred-Update STM Systems
..........................................64
3.4.1
Herlihy, Luchangco, Moir, and Scherer, PODC
2003...............64
Implementation
..............................................65
Detailed Implementation
......................................67
3.4.2
Harris and
Fraser, OOPSLA
2003................................72
Implementation
..............................................73
Detailed Implementation
......................................78
3.4.3
Fraser, Ph.D
.....................................................86
Implementation
..............................................86
3.4.4
Scherer and Scott, PODC
05.....................................87
Policies
......................................................87
3.4.5
Guerraoui, Herlihy, and Pochon, DISC
05.........................88
Implementation
..............................................89
3.4.6
Marathe,
Scherer, and Scott, DISC
05.............................90
Implementation
..............................................90
3.4.7
Ananian and Rinard, SCOOL
05.................................93
CONTENTS
Ł
Implementation
..............................................94
3.4.8
Marathe,
Spear, Heriot, Acharya,
Eisenstat, Scherer,
Scott, TRANSACT
06...........................................95
Implementation
..............................................96
3.4.9
Dice and Shavit, TRANSACT
06.................................98
Implementation
..............................................98
3.5
Direct-Update STM
Systems
...........................................101
3.5.1
Manassiev, Mihailescu, Amza,
РРоРРОб
..........................101
3.5.2
Saha, Adl-Tabatabai, Hudson, Minh,
Hertzberg,
РРоРРОб.........
103
Implementation
.............................................104
3.5.3
Adl-Tabatabai, Lewis, Menon, Murphy, Saha,
Shpeisman, PLDI06
............................................106
3.5.4
Harris,
Plesko,
Shinnar,
Tarditi, PLDI06
.........................108
Detailed Implementation
.....................................108
Compiler Optimizations
.....................................114
Run-time Optimizations
.....................................115
3.5.5
McCloskey, Zhou, Gay, Brewer, POPL06
.........................115
3.5.6
Hicks, Foster, Pratikakis, TRANSACT
06........................116
3.6
Language-Oriented STM Systems
.......................................117
3.6.1
Harris, CSJP04
.................................................118
3.6.2
Pizlo, Procházka, Jagannathan, Vítek, CJSP04
.....................120
3.6.3
Harris, Marlow, Peyton Jones, Herlihy, PPoPP
05.................121
Haskell STM Extensions
.....................................122
Implementation
.............................................124
3.6.4 Ringenburg,
Grossman, ICFP
05................................124
Language Extensions
........................................125
Implementation
.............................................126
4.
Hardware-Supported Transactional Memory
.................................131
4.1
Introduction
...........................................................131
4.1.1
Chapter Overview
..............................................131
4.2
A Few Words on Hardware
.............................................132
4.2.1
Memory Consistency Models
....................................132
4.2.2
Caches and Cache Coherence
....................................133
4.2.3
Speculative Execution and Modem Processors
....................135
4.2.4
Baseline Hardware Framework
...................................136
4.3
Precursors
.............................................................137
CONTENTS
4.3.1
Chang
and Mergen,
ACM
TOCS
1988..........................137
Overview
...................................................137
Implementation
.............................................138
4.3.2
Knight, LFP
198...............................................140
Overview
...................................................140
Programming Interface
.......................................141
Implementation
.............................................141
4.3.3
Jensen, Hagensen, and Broughton, UCRL
1987...................144
Overview
...................................................144
Programming Interface
.......................................144
Implementation
.............................................145
4.3.4
Stone
et al.,
IEEE Concurrency
1993.............................148
Overview
...................................................148
Programming Interface
.......................................149
Implementation
.............................................150
4.3.5
Herlihy and Moss,
ISCA
1993...................................152
Overview
...................................................152
Programming Interface
.......................................153
Implementation
.............................................155
4.3.6
Rajwar and Goodman, MICRO
2001............................157
Overview
...................................................157
Programming Interface
.......................................158
Implementation
.............................................159
4.3.7
Rajwar and Goodman, ASPLOS
2002............................161
Overview
...................................................161
Programming Interface
.......................................162
Implementation
.............................................162
4.4
Bounded/Large HTMs
.................................................164
4.4.1
Hammond
et al.,
ISCA
2004....................................165
Overview
...................................................165
Programming Interface
.......................................166
Implementation
.............................................166
4.4.2
Ananian
et
al./LTM, HPCA
2005...............................168
Overview
...................................................168
Programming Interface
.......................................168
Implementation
.............................................168
4.4.3
Moore
et al., HPCA
2006.......................................170
CONTENTS
Overview
...................................................170
Programming Environment and Interface
......................171
Implementation
.............................................171
4.4.4
Ceze
et al.,
ISCA
2006..........................................173
Overview
...................................................173
Implementation
.............................................174
4.5
Unbounded HTMs
....................................................177
4.5.1
Ananian
et
al./UTM, HPCA
2005...............................177
Overview
...................................................177
Programming Interface
.......................................178
Implementation
.............................................178
4.5.2
Rajwar, Herlihy, and
Lai, ISCA
2005.............................180
Overview
...................................................180
Programming Interface
.......................................181
Implementation
.............................................182
4.5.3
Zilles and Baugh, TRANSACT
2006............................184
Overview
...................................................184
Programming Interface
.......................................185
.
Implementation
.............................................186
4.6
Hybrid HTM-STMs/Hardware-Accelerated STMs
......................188
4.6.1
Lie, MIT ME Thesis
2004......................................188
Overview
...................................................188
Programming Interface
.......................................188
Implementation
.............................................189
4.6.2
Kumar
et al., PPoPP
2006.......................................189
Overview
...................................................189
Programming Interface
.......................................190
Implementation
.............................................190
4.6.3
Shriraman
et al.,
TRANSACT
2006.............................193
Overview
...................................................193
Programming Interface
.......................................193
Implementation
.............................................195
4.7
HTM Semantics
.......................................................196
4.7.1
Moss and Hosking,
SCP
2006...................................196
Overview
...................................................196
Semantic Description
........................................196
Implementation Sketch
......................................197
ii
CONTENTS
4.7.2
McDonald et
al, ISCA
2006....................................198
Overview
...................................................198
Programming Interface
.......................................199
Implementation
.............................................200
5.
Conclusions
........>.......................................................206
|
| adam_txt |
Contents
1.
introduction
.
,
.1
1.1
Motivation
.1
1.1.1
Single-Chip Parallel Computers
.1
1.1.2
Difficulty of Parallel Programming
.2
1.1.3
Parallel Programming Abstractions
.3
1.2
Database Systems and Transactions
.5
1.2.1
What Is a Transaction?
.6
1.3
Transactional Memory
.7
1.3.1
Differences
.9
1.4
This Book
.9
2.
Programming Transactional Memory
.14
2.1
Basic Transactional Constructs
.15
2.1.1
Atomic Block
.16
2.1.2
Semantics
.19
Database Correctness Criteria
.19
Operational Semantics
.20
Non-Transactional Accesses
.20
Linearizability
.23
2.1.3
Declarations
.23
2.1.4
Retry
.24
2.1.5
OrElse
.25
2.2
Transaction Design Space
.26
2.2.1
Weak and Strong Isolation
.26
2.2.2
Nested Transactions
.28
2.2.3
Exceptions
.31
2.3
Transactional Memory System Taxonomy
.32
2.3.1
Transaction Granularity
.32
2.3.2
Direct and Deferred Update
.33
2.3.3
Concurrency Control
.35
2.3.4
Early and Late Conflict Detection
.37
2.3.5
Detecting and Tolerating Conflicts
.39
CONTENTS
2.3.6 Contention Management.43
2.4 Programming and
Execution
Environment.44
2.4.1
Communication
.44
2.4.2 System
Abstractions
.45
2.4.3
Existing
Programming
Languages.
46
2.4.4 Libraries.47
2.4.5 Svnchronization Primitives.47
2.4.6
Debugging
.47
2.4.7 Performance Isolation.48
2.4.8 HTM Implementation.48
$. Software Transactional Memory.53
3.1
Introduction
.53
3.1.1
Chapter Overview
.53
3.2
A Few Words on Language
.54
3.3
STM Precursors
.55
3.3.1
Lomet, LDRS
77.55
Implementation
.58
3.3.2
Shavit, Touitou, PODC
1995.58
Implementation
.59
3.3.3
Other Precursors
.63
3.4
Deferred-Update STM Systems
.64
3.4.1
Herlihy, Luchangco, Moir, and Scherer, PODC
2003.64
Implementation
.65
Detailed Implementation
.67
3.4.2
Harris and
Fraser, OOPSLA
2003.72
Implementation
.73
Detailed Implementation
.78
3.4.3
Fraser, Ph.D
.86
Implementation
.86
3.4.4
Scherer and Scott, PODC
05.87
Policies
.87
3.4.5
Guerraoui, Herlihy, and Pochon, DISC
05.88
Implementation
.89
3.4.6
Marathe,
Scherer, and Scott, DISC
05.90
Implementation
.90
3.4.7
Ananian and Rinard, SCOOL
05.93
CONTENTS
Ł
Implementation
.94
3.4.8
Marathe,
Spear, Heriot, Acharya,
Eisenstat, Scherer,
Scott, TRANSACT
06.95
Implementation
.96
3.4.9
Dice and Shavit, TRANSACT
06.98
Implementation
.98
3.5
Direct-Update STM
Systems
.101
3.5.1
Manassiev, Mihailescu, Amza,
РРоРРОб
.101
3.5.2
Saha, Adl-Tabatabai, Hudson, Minh,
Hertzberg,
РРоРРОб.
103
Implementation
.104
3.5.3
Adl-Tabatabai, Lewis, Menon, Murphy, Saha,
Shpeisman, PLDI06
.106
3.5.4
Harris,
Plesko,
Shinnar,
Tarditi, PLDI06
.108
Detailed Implementation
.108
Compiler Optimizations
.114
Run-time Optimizations
.115
3.5.5
McCloskey, Zhou, Gay, Brewer, POPL06
.115
3.5.6
Hicks, Foster, Pratikakis, TRANSACT
06.116
3.6
Language-Oriented STM Systems
.117
3.6.1
Harris, CSJP04
.118
3.6.2
Pizlo, Procházka, Jagannathan, Vítek, CJSP04
.120
3.6.3
Harris, Marlow, Peyton Jones, Herlihy, PPoPP
05.121
Haskell STM Extensions
.122
Implementation
.124
3.6.4 Ringenburg,
Grossman, ICFP
05.124
Language Extensions
.125
Implementation
.126
4.
Hardware-Supported Transactional Memory
.131
4.1
Introduction
.131
4.1.1
Chapter Overview
.131
4.2
A Few Words on Hardware
.132
4.2.1
Memory Consistency Models
.132
4.2.2
Caches and Cache Coherence
.133
4.2.3
Speculative Execution and Modem Processors
.135
4.2.4
Baseline Hardware Framework
.136
4.3
Precursors
.137
CONTENTS
4.3.1
Chang
and Mergen,
ACM
TOCS
1988.137
Overview
.137
Implementation
.138
4.3.2
Knight, LFP
198.140
Overview
.140
Programming Interface
.141
Implementation
.141
4.3.3
Jensen, Hagensen, and Broughton, UCRL
1987.144
Overview
.144
Programming Interface
.144
Implementation
.145
4.3.4
Stone
et al.,
IEEE Concurrency
1993.148
Overview
.148
Programming Interface
.149
Implementation
.150
4.3.5
Herlihy and Moss,
ISCA
1993.152
Overview
.152
Programming Interface
.153
Implementation
.155
4.3.6
Rajwar and Goodman, MICRO
2001.157
Overview
.157
Programming Interface
.158
Implementation
.159
4.3.7
Rajwar and Goodman, ASPLOS
2002.161
Overview
.161
Programming Interface
.162
Implementation
.162
4.4
Bounded/Large HTMs
.164
4.4.1
Hammond
et al.,
ISCA
2004.165
Overview
.165
Programming Interface
.166
Implementation
.166
4.4.2
Ananian
et
al./LTM, HPCA
2005.168
Overview
.168
Programming Interface
.168
Implementation
.168
4.4.3
Moore
et al., HPCA
2006.170
CONTENTS
Overview
.170
Programming Environment and Interface
.171
Implementation
.171
4.4.4
Ceze
et al.,
ISCA
2006.173
Overview
.173
Implementation
.174
4.5
Unbounded HTMs
.177
4.5.1
Ananian
et
al./UTM, HPCA
2005.177
Overview
.177
Programming Interface
.178
Implementation
.178
4.5.2
Rajwar, Herlihy, and
Lai, ISCA
2005.180
Overview
.180
Programming Interface
.181
Implementation
.182
4.5.3
Zilles and Baugh, TRANSACT
2006.184
Overview
.184
Programming Interface
.185
.
Implementation
.186
4.6
Hybrid HTM-STMs/Hardware-Accelerated STMs
.188
4.6.1
Lie, MIT ME Thesis
2004.188
Overview
.188
Programming Interface
.188
Implementation
.189
4.6.2
Kumar
et al., PPoPP
2006.189
Overview
.189
Programming Interface
.190
Implementation
.190
4.6.3
Shriraman
et al.,
TRANSACT
2006.193
Overview
.193
Programming Interface
.193
Implementation
.195
4.7
HTM Semantics
.196
4.7.1
Moss and Hosking,
SCP
2006.196
Overview
.196
Semantic Description
.196
Implementation Sketch
.197
ii
CONTENTS
4.7.2
McDonald et
al, ISCA
2006.198
Overview
.198
Programming Interface
.199
Implementation
.200
5.
Conclusions
.>.206 |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Larus, James R. Rajwar, Ravi |
| author_facet | Larus, James R. Rajwar, Ravi |
| author_role | aut aut |
| author_sort | Larus, James R. |
| author_variant | j r l jr jrl r r rr |
| building | Verbundindex |
| bvnumber | BV023028516 |
| callnumber-first | Q - Science |
| callnumber-label | QA76 |
| callnumber-raw | QA76.545 |
| callnumber-search | QA76.545 |
| callnumber-sort | QA 276.545 |
| callnumber-subject | QA - Mathematics |
| classification_rvk | ST 175 |
| ctrlnum | (OCoLC)85771303 (DE-599)BVBBV023028516 |
| dewey-full | 510 |
| dewey-hundreds | 500 - Natural sciences and mathematics |
| dewey-ones | 510 - Mathematics |
| dewey-raw | 510 |
| dewey-search | 510 |
| dewey-sort | 3510 |
| dewey-tens | 510 - Mathematics |
| discipline | Informatik Mathematik |
| discipline_str_mv | Informatik Mathematik |
| edition | 1. ed. |
| format | Book |
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| id | DE-604.BV023028516 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T19:16:04Z |
| indexdate | 2024-07-09T21:09:20Z |
| institution | BVB |
| isbn | 9781598291247 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016232447 |
| oclc_num | 85771303 |
| open_access_boolean | |
| owner | DE-384 DE-473 DE-BY-UBG DE-29T |
| owner_facet | DE-384 DE-473 DE-BY-UBG DE-29T |
| physical | XIII, 211 S. |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | Morgan & Claypool Publishers |
| record_format | marc |
| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture |
| spelling | Larus, James R. Verfasser aut Transactional memory James R. Larus ; Ravi Rajwar 1. ed. [San Rafael, Calif.] Morgan & Claypool Publishers 2007 XIII, 211 S. txt rdacontent n rdamedia nc rdacarrier Synthesis lectures on computer architecture 2 Parallel programming (Computer science) Synchronization Threads (Computer programs) Transaction systems (Computer systems) Robustheit (DE-588)4126481-2 gnd rswk-swf Transaktionssystem (DE-588)4195506-7 gnd rswk-swf Gemeinsamer Speicher (DE-588)4294156-8 gnd rswk-swf Transaktionssystem (DE-588)4195506-7 s Gemeinsamer Speicher (DE-588)4294156-8 s Robustheit (DE-588)4126481-2 s DE-604 Rajwar, Ravi Verfasser aut Synthesis lectures on computer architecture 2 (DE-604)BV023068349 2 Digitalisierung UB Augsburg application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016232447&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Larus, James R. Rajwar, Ravi Transactional memory Synthesis lectures on computer architecture Parallel programming (Computer science) Synchronization Threads (Computer programs) Transaction systems (Computer systems) Robustheit (DE-588)4126481-2 gnd Transaktionssystem (DE-588)4195506-7 gnd Gemeinsamer Speicher (DE-588)4294156-8 gnd |
| subject_GND | (DE-588)4126481-2 (DE-588)4195506-7 (DE-588)4294156-8 |
| title | Transactional memory |
| title_auth | Transactional memory |
| title_exact_search | Transactional memory |
| title_exact_search_txtP | Transactional memory |
| title_full | Transactional memory James R. Larus ; Ravi Rajwar |
| title_fullStr | Transactional memory James R. Larus ; Ravi Rajwar |
| title_full_unstemmed | Transactional memory James R. Larus ; Ravi Rajwar |
| title_short | Transactional memory |
| title_sort | transactional memory |
| topic | Parallel programming (Computer science) Synchronization Threads (Computer programs) Transaction systems (Computer systems) Robustheit (DE-588)4126481-2 gnd Transaktionssystem (DE-588)4195506-7 gnd Gemeinsamer Speicher (DE-588)4294156-8 gnd |
| topic_facet | Parallel programming (Computer science) Synchronization Threads (Computer programs) Transaction systems (Computer systems) Robustheit Transaktionssystem Gemeinsamer Speicher |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016232447&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV023068349 |
| work_keys_str_mv | AT larusjamesr transactionalmemory AT rajwarravi transactionalmemory |