Verilog for digital design:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Hoboken, NJ
Wiley
2007
|
| Schlagworte: | |
| Beschreibung: | XVI, 173 S. graph. Darst. |
| ISBN: | 9780470052624 |
Internformat
MARC
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|---|---|---|---|
| 001 | BV022965979 | ||
| 003 | DE-604 | ||
| 005 | 20110927 | ||
| 007 | t | ||
| 008 | 071115s2007 d||| |||| 00||| eng d | ||
| 020 | |a 9780470052624 |9 978-0-470-05262-4 | ||
| 035 | |a (OCoLC)164375002 | ||
| 035 | |a (DE-599)BVBBV022965979 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-703 |a DE-83 | ||
| 050 | 0 | |a TK7885.7 | |
| 082 | 0 | |a 621.392 |2 22 | |
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
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| 100 | 1 | |a Vahid, Frank |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Verilog for digital design |c Frank Vahid ; Roman Lysecky |
| 264 | 1 | |a Hoboken, NJ |b Wiley |c 2007 | |
| 300 | |a XVI, 173 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Lysecky, Roman |e Verfasser |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-016170295 | ||
Datensatz im Suchindex
| _version_ | 1804137215218941952 |
|---|---|
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| any_adam_object | |
| any_adam_object_boolean | |
| author | Vahid, Frank Lysecky, Roman |
| author_facet | Vahid, Frank Lysecky, Roman |
| author_role | aut aut |
| author_sort | Vahid, Frank |
| author_variant | f v fv r l rl |
| building | Verbundindex |
| bvnumber | BV022965979 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 ZN 4904 |
| ctrlnum | (OCoLC)164375002 (DE-599)BVBBV022965979 |
| dewey-full | 621.392 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.392 |
| dewey-search | 621.392 |
| dewey-sort | 3621.392 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV022965979 |
| illustrated | Illustrated |
| index_date | 2024-07-02T19:06:39Z |
| indexdate | 2024-07-09T21:08:45Z |
| institution | BVB |
| isbn | 9780470052624 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016170295 |
| oclc_num | 164375002 |
| open_access_boolean | |
| owner | DE-703 DE-83 |
| owner_facet | DE-703 DE-83 |
| physical | XVI, 173 S. graph. Darst. |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | Wiley |
| record_format | marc |
| spelling | Vahid, Frank Verfasser aut Verilog for digital design Frank Vahid ; Roman Lysecky Hoboken, NJ Wiley 2007 XVI, 173 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier VHDL (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 Lysecky, Roman Verfasser aut |
| spellingShingle | Vahid, Frank Lysecky, Roman Verilog for digital design VHDL (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Verilog for digital design |
| title_auth | Verilog for digital design |
| title_exact_search | Verilog for digital design |
| title_exact_search_txtP | Verilog for digital design |
| title_full | Verilog for digital design Frank Vahid ; Roman Lysecky |
| title_fullStr | Verilog for digital design Frank Vahid ; Roman Lysecky |
| title_full_unstemmed | Verilog for digital design Frank Vahid ; Roman Lysecky |
| title_short | Verilog for digital design |
| title_sort | verilog for digital design |
| topic | VHDL (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| topic_facet | VHDL (Computer hardware description language) VERILOG |
| work_keys_str_mv | AT vahidfrank verilogfordigitaldesign AT lyseckyroman verilogfordigitaldesign |