Analog circuit design techniques at 0.5V:
Gespeichert in:
| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Springer
2007
|
| Schriftenreihe: | Analog circuits and signal processing series
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XI, 156 S. Ill., graph. Darst. |
| ISBN: | 9780387699530 0387699538 |
Internformat
MARC
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| 245 | 1 | 0 | |a Analog circuit design techniques at 0.5V |c Shouri Chatterjee ... |
| 264 | 1 | |a New York, NY |b Springer |c 2007 | |
| 300 | |a XI, 156 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 490 | 0 | |a Analog circuits and signal processing series | |
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Datensatz im Suchindex
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| adam_text | SHOURI CHATTERJEE KONG PANG PUN NEBOJSA STANIC YANNIS TSIVIDIS PETER
KINGET ANALOG CIRCUIT DESIGN TECHNIQUES AT 0.5V SPRINGER CONTENTS 1
INTRODUCTION 1 1.1 LOW-VOLTAGE ANALOG CIRCUIT DESIGN CHALLENGES 4 1.2
OPPORTUNITIES AT LOW VOLTAGES 9 1.3 ORGANIZATION OF THE BOOK 14 2 FULLY
DIFFERENTIAL OPERATIONAL TRANSCONDUCTANCE AMPLINERS (OTAS) . 17 2.1
BODY-INPUT OTA 19 2.2 GATE-INPUT OTA 23 2.3 ON-CHIP BIASING CIRCUITS FOR
THE GATE-INPUT OTA 29 2.3.1 ERROR AMPLIFIER 30 2.3.2 GENERATING A FIXED
LEVEL SHIFT 31 2.3.3 SETTING THE OTA OUTPUT DC COMMON-MODE VOLTAGE 32
2.3.4 GAIN ENHANCEMENT 33 2.3.5 START-UP 35 2.4 CHARACTERIZATION RESULTS
FOR THE BODY-INPUT AND GATE-INPUT OTAS ... 35 2.4.1 BODY-INPUT OTA
MEASUREMENTS 35 2.4.2 GATE-INPUT OTA MEASUREMENTS 36 2.5 DISCUSSION ON
THE TWO OTA DESIGN TECHNIQUES 39 2.6 DESIGN METHODOLOGY FOR LOW VT
DEVICES, WITHOUT BODY ACCESS 41 2.6.1 FULLY DIFFERENTIAL OTA 41 2.6.2
BIAS CIRCUITS 45 2.7 SUMMARY 45 3 WEAK INVERSION MOS VARACTORS FOR
TUNABLE INTEGRATORS 49 3.1 BRIEF THEORETICAL OVERVIEW 50 3.2 DEVICE
MEASUREMENTS AND MODELING 50 3.2.1 CLOSED-FORM MODEL 52 3.2.2 CHANNEL
SEGMENTATION 54 3.2.3 COMPARISON BETWEEN MEASURED RESULTS AND
SIMULATIONS 56 3.3 CIRCUIT APPLICATIONS 56 3.3.1 DISCRETE PROTOTYPE
USING THE VARACTOR 56 X CONTENTS 3.3.2 APPLICATION OF THE VARACTOR IN AN
INTEGRATED SETTING 56 3.4 SUMMARY 60 4 A 0.5 V 5TH-ORDER LOW-PASS
ELLIPTIC FILTER 61 4.1 FILTER TOPOLOGY 61 4.2 ON-CHIP PLL-BASED
AUTOMATIC FREQUENCY TUNING LOOP 62 4.3 LAYOUT AND PROTOTYPE CHIP 65 4.4
CHARACTERIZATION RESULTS 66 4.4.1 TEST SET-UP 66 4.4.2 FREQUENCY
RESPONSE 66 4.4.3 NOISE 67 4.4.4 DISTORTION AND CHARACTERIZATION OVER
TUNING RAENGE 67 4.4.5 PERFORMANCE AT DIFFERENT POWER SUPPLY VOLTAGES 69
4.4.6 PERFORMANCE OVER DIFFERENT CHIPS 69 4.4.7 PERFORMANCE OVER
TEMPERATURE 71 4.5 SUMMARY 71 5 A 0.5 V TRACK-AND-HOLD (T/H) CIRCUIT 77
5.1 INTRODUCTION 77 5.2 T/H OPERATION AT ULTRA-LOW VOLTAGES 77 5.3
FULLY-DIFFERENTIAL 0.5 V T/H CIRCUIT 79 5.3.1 CHARGE INJECTION AND
SAMPLING TIMES 80 5.3.2 FULLY-DIFFERENTIAL IMPLEMENTATION 81 5.3.3
COMMON-MODE REJECTION 81 5.3.4 INTEGRATED NOISE 83 5.3.5 TRACK-AND-HOLD
TEST STRATEGY 86 5.4 DESIGN DETAILS AND MEASUREMENT RESULTS 86 5.4.1
GATE-INPUT OTA 86 5.4.2 SWITCHES 87 5.4.3 CLOCK GENERATION 87 5.4.4
PROTOTYPE CHIP 90 5.4.5 SIMULATED PERFORMANCE 91 5.4.6 MEASURED
PERFORMANCE 91 5.5 CONCLUSION 92 6 A 0.5 V CONTINUOUS-TIME SA MODULATOR
97 6.1 INTRODUCTION 97 6.2 RETURN-TO-OPEN DAC 98 6.2.1 SIMILAR DAC
CONCEPTS 99 6.2.2 NOISE IMPROVEMENTS BY RTO DAC 102 6.2.3 RETURN TO ZERO
URNING 103 6.3 SPLIT RTO DAC MODULATOR ARCHITECTURE 103 6.3.1 MODULATOR
CLOCKING 104 6.3.2 MODULATOR DESIGN 105 6.3.3 VALUES OF R AND C 106
CONTENTS XI 6.4 BUILDING BLOCK CIRCUITS FOR 0.5 V SUPPLY 108 6.4.1 RTO
DAC CIRCUIT 108 6.4.2 COMPARATOR 110 6.4.3 OPERATIONAL TRANSCONDUCTANCE
AMPLIFIERS 110 6.4.4 CLOCK GENERATION CIRCUIT 112 6.5 EXPERIMENTAL
RESULTS 112 6.6 CONCLUSIONS 120 7 0.5 V RECEIVER FRONT-END CIRCUITS 121
7.1 INTRODUCTION 121 7.2 RF RECEIVER SYSTEM-LEVEL CONSIDERATIONS 121 7.3
LOW-NOISE AMPLIFIERS 122 7.3.1 BASIC PROPERTIES AND STANDARD TOPOLOGIES
122 7.3.2 LOW-VOLTAGE CONSIDERATIONS 123 7.4 DOWNCONVERSION MIXERS 124
7.4.1 BASIC PROPERTIES AND STANDARD TOPOLOGIES 124 7.4.2 LOW-VOLTAGE
CONSIDERATIONS 126 7.5 900 MHZ RECEIVER FRONT-END IN 0.18 /IM CMOS 127
7.5.1 DESIGN OF THE LNA 127 7.5.2 DESIGN OF THE DOWNCONVERSION MIXER 130
7.5.3 DESIGN OF THE LOBUFFERS. 134 7.5.4 MEASUREMENT AND RESULTS 135 A
ANALYSIS OF A DISTNBUTED MODEL FOR A MOS CAPACITOR 141 REFERENCES 147
INDEX 155
|
| adam_txt |
SHOURI CHATTERJEE KONG PANG PUN NEBOJSA STANIC YANNIS TSIVIDIS PETER
KINGET ANALOG CIRCUIT DESIGN TECHNIQUES AT 0.5V SPRINGER CONTENTS 1
INTRODUCTION 1 1.1 LOW-VOLTAGE ANALOG CIRCUIT DESIGN CHALLENGES 4 1.2
OPPORTUNITIES AT LOW VOLTAGES 9 1.3 ORGANIZATION OF THE BOOK 14 2 FULLY
DIFFERENTIAL OPERATIONAL TRANSCONDUCTANCE AMPLINERS (OTAS) . 17 2.1
BODY-INPUT OTA 19 2.2 GATE-INPUT OTA 23 2.3 ON-CHIP BIASING CIRCUITS FOR
THE GATE-INPUT OTA 29 2.3.1 ERROR AMPLIFIER 30 2.3.2 GENERATING A FIXED
LEVEL SHIFT 31 2.3.3 SETTING THE OTA OUTPUT DC COMMON-MODE VOLTAGE 32
2.3.4 GAIN ENHANCEMENT 33 2.3.5 START-UP 35 2.4 CHARACTERIZATION RESULTS
FOR THE BODY-INPUT AND GATE-INPUT OTAS . 35 2.4.1 BODY-INPUT OTA
MEASUREMENTS 35 2.4.2 GATE-INPUT OTA MEASUREMENTS 36 2.5 DISCUSSION ON
THE TWO OTA DESIGN TECHNIQUES 39 2.6 DESIGN METHODOLOGY FOR LOW VT
DEVICES, WITHOUT BODY ACCESS 41 2.6.1 FULLY DIFFERENTIAL OTA 41 2.6.2
BIAS CIRCUITS 45 2.7 SUMMARY 45 3 WEAK INVERSION MOS VARACTORS FOR
TUNABLE INTEGRATORS 49 3.1 BRIEF THEORETICAL OVERVIEW 50 3.2 DEVICE
MEASUREMENTS AND MODELING 50 3.2.1 CLOSED-FORM MODEL 52 3.2.2 CHANNEL
SEGMENTATION 54 3.2.3 COMPARISON BETWEEN MEASURED RESULTS AND
SIMULATIONS 56 3.3 CIRCUIT APPLICATIONS 56 3.3.1 DISCRETE PROTOTYPE
USING THE VARACTOR 56 X CONTENTS 3.3.2 APPLICATION OF THE VARACTOR IN AN
INTEGRATED SETTING 56 3.4 SUMMARY 60 4 A 0.5 V 5TH-ORDER LOW-PASS
ELLIPTIC FILTER 61 4.1 FILTER TOPOLOGY 61 4.2 ON-CHIP PLL-BASED
AUTOMATIC FREQUENCY TUNING LOOP 62 4.3 LAYOUT AND PROTOTYPE CHIP 65 4.4
CHARACTERIZATION RESULTS 66 4.4.1 TEST SET-UP 66 4.4.2 FREQUENCY
RESPONSE 66 4.4.3 NOISE 67 4.4.4 DISTORTION AND CHARACTERIZATION OVER
TUNING RAENGE 67 4.4.5 PERFORMANCE AT DIFFERENT POWER SUPPLY VOLTAGES 69
4.4.6 PERFORMANCE OVER DIFFERENT CHIPS 69 4.4.7 PERFORMANCE OVER
TEMPERATURE 71 4.5 SUMMARY 71 5 A 0.5 V TRACK-AND-HOLD (T/H) CIRCUIT 77
5.1 INTRODUCTION 77 5.2 T/H OPERATION AT ULTRA-LOW VOLTAGES 77 5.3
FULLY-DIFFERENTIAL 0.5 V T/H CIRCUIT 79 5.3.1 CHARGE INJECTION AND
SAMPLING TIMES 80 5.3.2 FULLY-DIFFERENTIAL IMPLEMENTATION 81 5.3.3
COMMON-MODE REJECTION 81 5.3.4 INTEGRATED NOISE 83 5.3.5 TRACK-AND-HOLD
TEST STRATEGY 86 5.4 DESIGN DETAILS AND MEASUREMENT RESULTS 86 5.4.1
GATE-INPUT OTA 86 5.4.2 SWITCHES 87 5.4.3 CLOCK GENERATION 87 5.4.4
PROTOTYPE CHIP 90 5.4.5 SIMULATED PERFORMANCE 91 5.4.6 MEASURED
PERFORMANCE 91 5.5 CONCLUSION 92 6 A 0.5 V CONTINUOUS-TIME SA MODULATOR
97 6.1 INTRODUCTION 97 6.2 RETURN-TO-OPEN DAC 98 6.2.1 SIMILAR DAC
CONCEPTS 99 6.2.2 NOISE IMPROVEMENTS BY RTO DAC 102 6.2.3 RETURN TO ZERO
URNING 103 6.3 SPLIT RTO DAC MODULATOR ARCHITECTURE 103 6.3.1 MODULATOR
CLOCKING 104 6.3.2 MODULATOR DESIGN 105 6.3.3 VALUES OF R AND C 106
CONTENTS XI 6.4 BUILDING BLOCK CIRCUITS FOR 0.5 V SUPPLY 108 6.4.1 RTO
DAC CIRCUIT 108 6.4.2 COMPARATOR 110 6.4.3 OPERATIONAL TRANSCONDUCTANCE
AMPLIFIERS 110 6.4.4 CLOCK GENERATION CIRCUIT 112 6.5 EXPERIMENTAL
RESULTS 112 6.6 CONCLUSIONS 120 7 0.5 V RECEIVER FRONT-END CIRCUITS 121
7.1 INTRODUCTION 121 7.2 RF RECEIVER SYSTEM-LEVEL CONSIDERATIONS 121 7.3
LOW-NOISE AMPLIFIERS 122 7.3.1 BASIC PROPERTIES AND STANDARD TOPOLOGIES
122 7.3.2 LOW-VOLTAGE CONSIDERATIONS 123 7.4 DOWNCONVERSION MIXERS 124
7.4.1 BASIC PROPERTIES AND STANDARD TOPOLOGIES 124 7.4.2 LOW-VOLTAGE
CONSIDERATIONS 126 7.5 900 MHZ RECEIVER FRONT-END IN 0.18 /IM CMOS 127
7.5.1 DESIGN OF THE LNA 127 7.5.2 DESIGN OF THE DOWNCONVERSION MIXER 130
7.5.3 DESIGN OF THE LOBUFFERS. 134 7.5.4 MEASUREMENT AND RESULTS 135 A
ANALYSIS OF A DISTNBUTED MODEL FOR A MOS CAPACITOR 141 REFERENCES 147
INDEX 155 |
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| isbn | 9780387699530 0387699538 |
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| physical | XI, 156 S. Ill., graph. Darst. |
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| series2 | Analog circuits and signal processing series |
| spelling | Analog circuit design techniques at 0.5V Shouri Chatterjee ... New York, NY Springer 2007 XI, 156 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Analog circuits and signal processing series Electronic circuit design Linear integrated circuits Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Analogschaltung (DE-588)4122796-7 gnd rswk-swf Analogschaltung (DE-588)4122796-7 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Chatterjee, Shouri Sonstige oth GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016151324&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Analog circuit design techniques at 0.5V Electronic circuit design Linear integrated circuits Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd Analogschaltung (DE-588)4122796-7 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4122796-7 |
| title | Analog circuit design techniques at 0.5V |
| title_auth | Analog circuit design techniques at 0.5V |
| title_exact_search | Analog circuit design techniques at 0.5V |
| title_exact_search_txtP | Analog circuit design techniques at 0.5V |
| title_full | Analog circuit design techniques at 0.5V Shouri Chatterjee ... |
| title_fullStr | Analog circuit design techniques at 0.5V Shouri Chatterjee ... |
| title_full_unstemmed | Analog circuit design techniques at 0.5V Shouri Chatterjee ... |
| title_short | Analog circuit design techniques at 0.5V |
| title_sort | analog circuit design techniques at 0 5v |
| topic | Electronic circuit design Linear integrated circuits Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd Analogschaltung (DE-588)4122796-7 gnd |
| topic_facet | Electronic circuit design Linear integrated circuits Design and construction Schaltungsentwurf Analogschaltung |
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