Phase locked loops: design, simulation, and applications
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York [u.a.]
McGraw-Hill
2007
|
| Ausgabe: | 6. ed. |
| Schriftenreihe: | McGraw-Hill professional engineering
|
| Schlagworte: | |
| Online-Zugang: | Beschreibung für Leser Inhaltsverzeichnis |
| Beschreibung: | XII, 482 S. Ill., graph. Darst. 1 CD-ROM (12 cm) |
| ISBN: | 0071493751 9780071493758 9780071499262 |
Internformat
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| 246 | 1 | 3 | |a Phase-locked loops |
| 250 | |a 6. ed. | ||
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| 300 | |a XII, 482 S. |b Ill., graph. Darst. |e 1 CD-ROM (12 cm) | ||
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Datensatz im Suchindex
| _version_ | 1804137051204878336 |
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| adam_text | PHASE-LOCKED LOOPS DESIGN, SIMULATION, AND APPLICATIONS ROLAND E. BEST
SIXTH EDITION ME GRAW HILL NEW YORK CHICAGO SAN FRANCISCO LISBON LONDON
MADRID MEXICO CITY MILAN NEW DELHI SAN JUAN SEOUL SINGAPORE SYDNEY
TORONTO CONTENTS PREFACE XI CHAPTER 1. INTRODUCTION TO PLLS 1 1.1
OPERATING PRINCIPLES OF THE PLL 1 1.2 HISTORICAL BACKGROUND 5 1.3
CLASSIFICATION OF PLL TYPES 6 CHAPTER 2. MIXED-SIGNAL PLL BUILDING
BLOCKS 9 2.1 BLOCK DIAGRAM OF THE MIXED-SIGNAL PLL 9 2.2 A NOTE ON PHASE
SIGNALS 10 2.3 BUILDING BLOCKS OF MIXED-SIGNAL PLLS 12 2.4 PHASE
DETECTORS 13 2.4.1 TYPE 1: MULTIPLIER PHASE DETECTORS 13 2.4.2 TYPE 2:
EXOR PHASE DETECTORS 16 2.4.3 TYPE 3: JK-FLIPFLOP PHASE DETECTORS 18
2.4.4 TYPE 4: PHASE-FREQUENCY DETECTORS (PFDS) 20 2.5 LOOP FILTERS
(FIRST ORDER) 28 2.5.1 TYPE 1: PASSIVE LEAD-LAG FILTERS 29 2.5.2 TYPE 2:
ACTIVE LEAD-LAG FILTERS 30 2.5.3 TYPE 3: ACTIVE PI FILTERS 31 2.6
CONTROLLED OSCILLATORS 32 2.6.1 RELAXATION OSCILLATORS 32 2.6.2 RESONANT
OSCILLATORS 36 2.7 DOWN SEALERS 36 CHAPTER 3. MIXED-SIGNAL PLL ANALYSIS
39 3.1 PLL PERFORMANCE IN THE LOCKED STATE 39 3.2 THE MATHEMATICAL MODEL
FOR THE LOCKED STATE 39 3.3 A DEFINITION OF TRANSFER FUNCTIONS 41 3.3.1
THE PLL TRANSFER FUNCTION FOR SYSTEMS USING THE VOLTAGE OUTPUT PHASE
DETECTOR 41 3.3.2 THE PLL TRANSFER FUNCTION FOR SYSTEMS USING CURRENT
OUTPUT PHASE DETECTOR 46 3.4 TRANSIENT RESPONSE OF THE PLL IN THE LOCKED
STATE 47 3.4.1 PHASE STEP APPLIED TO THE REFERENCE INPUT 47 3.4.2
FREQUENCY STEP APPLIED TO THE REFERENCE INPUT 48 3.4.3 FREQUENCY RAMP
APPLIED TO THE REFERENCE INPUT 49 VI CONTENTS 3.5 STEADY-STATE ERROR OF
THE PLL 50 3.6 THE ORDER OF THE PLL SYSTEM 52 3.6.1 THE NUMBER OF POLES
52 3.6.2 A SPECIAL CASE: THE FIRST-ORDER PLL 53 3.7 PLL PERFORMANCE IN
THE UNLOCKED STATE 53 3.8 MATHEMATICAL MODEL FOR THE UNLOCKED STATE 53
3.9 KEY PARAMETERS OF THE PLL 62 3.9.1 HOLD RANGE A H 62 3.9.2 LOCK
RANGE ATO L AND LOCK TIME T L 65 3.9.3 PULL-IN RANGE AM P AND PULL-IN
TIME T P 71 3.9.4 PULL-OUT RANGE A(O PO 83 3.10 OPTIMIZING THE LOCK
PROCESS 86 3.10.1 FASTLOCK TECHNIQUES 87 3.10.2 CYCLE SLIP REDUCTION
(CSR) 89 3.11 IN-LOCK DETECTORS 91 CHAPTER 4. PLL PERFORMANCE IN THE
PRESENCE OF NOISE 93 4.1 SOURCES AND TYPES OF NOISE IN A PLL 93 4.2
DEFINING NOISE PARAMETERS 95 4.3 THE IMPACT OF NOISE ON PLL PERFORMANCE
96 4.4 PULL-IN TECHNIQUES FOR NOISY SIGNALS 104 4.4.1 THE SWEEP
TECHNIQUE 104 4.4.2 THE SWITCHED-FILTER TECHNIQUE 106 CHAPTER 5. DESIGN
PROCEDURE FOR MIXED-SIGNAL PLLS 107 CHAPTER 6. MIXED-SIGNAL PLL
APPLICATIONS PART 1: INTEGER-A/ FREQUENCY SYNTHESIZERS 119 6.1
SYNTHESIZERS IN WIRELESS AND RF APPLICATIONS 119 6.2 INTEGER-AT
FREQUENCY SYNTHESIZERS WITHOUT PRESCALERS 120 6.3 INTEGER- N FREQUENCY
SYNTHESIZERS WITH PRESCALERS 121 6.3.1 FIXED DIVISION RATIO PRESCALERS
121 6.3.2 DUAL-MODULUS PRESCALERS 122 6.3.3 FOUR-MODULUS PRESCALERS 124
6.4 EXTENDING THE FREQUENCY RANGE WITH MIXERS AND FREQUENCY MULTIPLIERS
126 6.5 CASE STUDY: DESIGNING AN INTEGER-A/ PLL FREQUENCY SYNTHESIZER
128 6.6 SINGLE-LOOP AND MULTI-LOOP FREQUENCY SYNTHESIZERS 131 6.7 PHASE
NOISE AND SPURS IN INTEGER FREQUENCY SYNTHESIZERS 134 6.7.1 PHASE NOISE
CREATED BY THE REFERENCE OSCILLATOR 136 6.7.2 PHASE NOISE CREATED BY THE
VCO 145 6.7.3 SPURS CREATED BY THE PHASE DETECTOR 150 CHAPTER 7.
MIXED-SIGNAL PLL APPLICATIONS PART 2: FRACTIONAL-A/ FREQUENCY
SYNTHESIZERS 159 7.1 REALIZATION OF FRACTIONAL DIVIDER RATIOS 159 7.2
ANALOG SPUR REDUCTION TECHNIQUES 161 7.3 DIGITAL SPUR REDUCTION
TECHNIQUES 165 7.4 REVIEWING THE XA MODULATOR 166 * 7.4.1 THE 2A A/D
CONVERTER 166 7.4.2 THE 2 A D/A CONVERTER 181 7.4.3 THE XA MODULATOR
USED IN FREQUENCY SYNTHESIZERS 183 7.4.4 NONLINEAR EFFECTS IN XA
MODULATORS 193 CONTENTS VII 7.5 THE DESIGN PROCEDURE FOR XA MODULATORS
194 7.6 SPURS, FRACTIONAL SPURS, AND SUBFRACTIONAL SPURS 196 7.7
ALTERNATIVE XA MODULATORS: THE MASH CONVERTER 197 CHAPTER 8.
MIXED-SIGNAL PLL APPLICATIONS PART 3: MISCELLANEOUS APPLICATIONS 203 8.1
RETIMING AND CLOCK SIGNAL RECOVERY 203 8.2 MOTOR-SPEED CONTROL 210
CHAPTER 9. HIGHER-ORDER LOOPS 217 9.1 MOTIVATION FOR HIGHER-ORDER LOOPS
217 9.2 ANALYZING THE STABILITY OF HIGHER-ORDER LOOPS 217 9.3 DESIGNING
THIRD-ORDER PLLS 220 9.3.1 THE PASSIVE LEAD-LAG LOOP FILTER FOR VOLTAGE
INPUT 221 9.3.2 PASSIVE LEAD-LAG LOOP FILTER FOR CURRENT INPUT 223 9.3.3
ACTIVE LEAD-LAG LOOP FILTER 225 9.3.4 ACTIVE PI LOOP FILTER 227 9.4
DESIGNING FOURTH-ORDER PLLS 230 9.4.1 PASSIVE LEAD-LAG LOOP FILTERS FOR
VOLTAGE INPUT 230 9.4.2 THE PASSIVE LEAD-LAG LOOP FILTER FOR CURRENT
INPUT 233 9.4.3 THE ACTIVE LEAD-LAG LOOP FILTER 235 9.4.4 THE ACTIVE PI
LOOP FILTER 238 9.5 DESIGNING FIFTH-ORDER PLLS 241 9.5.1 PASSIVE
LEAD-LAG LOOP FILTER FOR VOLTAGE INPUT 242 9.5.2 THE PASSIVE LEAD-LAG
LOOP FILTER FOR CURRENT INPUT 244 9.5.3 ACTIVE LEAD-LAG LOOP FILTER 247
9.5.4 ACTIVE PI LOOP FILTER 251 9.6 THE KEY PARAMETERS OF HIGHER-ORDER
PLLS 255 CHAPTER 10. COMPUTER-AIDED DESIGN AND SIMULATION OF
MIXED-SIGNAL PLLS 257 10.1 OVERVIEW 257 10.2 QUICK TOUR 259 10.2.1
CONFIGURING THE PLL SYSTEM 259 10.2.2 DESIGNING THE LOOP FILTER 260
10.2.3 ANALYZING THE STABILITY OF THE LOOP 261 10.2.4 GETTING THE LOOP
FILTER SCHEMATIC 262 10.2.5 RUNNING SIMULATIONS 263 10.3 SIMULATIONS
WITH AND WITHOUT AVERAGING 264 10.4 SIMULATIONS WITH NOISY REFERENCE
SIGNALS 266 10.5 DISPLAYING WAVEFORMS OF TRI-STATE SIGNALS 267 10.6
GETTING HELP 268 10.7 SHAPING THE APPEARANCE OF GRAPHIC OBJECTS 268 10.8
SUGGESTIONS FOR CASE STUDIES 269 CHAPTER 11. ALL-DIGITAL PLLS (ADPLLS)
271 11.1 ADPLL COMPONENTS 271 11.1.1 ALL-DIGITAL PHASE DETECTORS 271
11.1.2 ALL-DIGITAL LOOP FILTERS 277 11.1.3 DIGITAL-CONTROLLED
OSCILLATORS 282 11.2 EXAMPLES OF IMPLEMENTED ADPLLS 286 VIII CONTENTS
11.3 THEORY OF A SELECTED TYPE OF ADPLL 292 11.3.1 THE EFFECTS OF
DISCRETE-TIME OPERATION 293 11.3.2 THE HOLD RANGE OF THE ADPLL 298
11.3.3 FREQUENCY-DOMAIN ANALYSIS OF THE ADPLL 30.1 11.3.4 RIPPLE
REDUCTION TECHNIQUES 303 11.3.5 HIGHER-ORDER ADPLLS 304 11.4 TYPICAL
ADPLL APPLICATIONS 305 11.5 DESIGNING AN ADPLL 307 11.5.1 CASE STUDY:
DESIGNING AN ADPLL FSK DECODER 307 CHAPTER 12. COMPUTER-AIDED DESIGN AND
SIMULATION OF ADPLLS 311 12.1 DESIGNING THE ADPLL 311 12.2 SIMULATING
ADPLL PERFORMANCE 313 12.3 CASE STUDIES ON ADPLL BEHAVIOR 314 CHAPTER
13. THE SOFTWARE PLL (SPLL) 321 13.1 THE HARDWARE-SOFTWARE TRADE-OFF 321
13.2 THE FEASIBILITY OF AN SPLL DESIGN 322 13.3 SPLL EXAMPLES 323 13.3.1
AN LPLL-LIKE SPLL 324 13.3.2 A DPLL-LIKE SPLL 330 13.3.3 A NOTE ON
ADPLL-LIKE SPLLS 339 CHAPTER 14. THE PLL IN COMMUNICATIONS 341 14.1
TYPES OF COMMUNICATIONS: BASEBAND AND BANDPASS 341 14.2 AMPLITUDE SHIFT
KEYING 343 14.3 PHASE SHIFT KEYING 343 14.3.1 BINARY PHASE SHIFT KEYING
(BPSK) 343 14.3.2 QUADRATURE PHASE SHIFT KEYING 345 14.3.3 OFFSET
QUADRATURE PSK (OQPSK) 346 14.3.4 M-ARYPSK 347 14.3.5 DIFFERENTIAL PSK
(DPSK) 347 14.4 FREQUENCY SHIFT KEYING 348 14.4.1 BINARY FSK 348 14.4.2
M-ARYFSK 350 14.4.3 MINIMUM SHIFT KEYING (MSK) AND GAUSSIAN MSK (GMSK)
351 14.5 QUADRATURE AMPLITUDE MODULATION (QAM) 355 14.6 THE ROLE OF
SYNCHRONIZATION IN DIGITAL COMMUNICATIONS 356 14.7 DIGITAL
COMMUNICATIONS USING BPSK 357 14.7.1 TRANSMITTER CONSIDERATIONS 357
14.7.2 RECEIVER CONSIDERATIONS 362 14.8 DIGITAL COMMUNICATIONS USING
QPSK 372 14.8.1 TRANSMITTER CONSIDERATIONS 372 14.8.2 RECEIVER
CONSIDERATIONS 373 14.9 DIGITAL COMMUNICATIONS USING QAM 375 14.10
DIGITAL COMMUNICATIONS USING FSK 377 14.10.1 SIMPLE FSK DECODERS: EASY
TO IMPLEMENT, BUT NOT EFFECTIVE 377 14.10.2 COHERENT FSK DETECTION 379
14.10.3 NONCOHERENT FSK DETECTION AND QUADRATURE FSK DECODERS 380 14.11
DIGITAL COMMUNICATIONS IN MOBILE PHONES 381 14.12 BANDWIDTH EFFICIENCY,
BIT ERROR RATE (BER), AND THE SIGNAL POWER EFFICIENCY OF DIGITAL
MODULATION SCHEMES 382 CONTENTS IX CHAPTER 15. SEARCHING PLL INTEGRATED
CIRCUITS 385 APPENDIX A. THE PULL-IN PROCESS 389 A.1 THE SIMPLIFIED
MODEL FOR THE PULL-IN RANGE A P OF THE LPLL 389 A.2 A SIMPLIFIED MODEL
FOR THE PULL-IN TIME T P OF THE LPLL 396 A.3 THE PULL-IN RANGE A P OF
THE DPLL 399 A.4 THE PULL-IN TIME T P OF THE DPLL 401 APPENDIX B. THE
LAPLACE TRANSFORM 403 B.1 TRANSFORMS ARE THE ENGINEER S TOOLS 403 B.2
LAPLACE TRANSFORM IS THE KEY TO SUCCESS 406 B.3 A NUMERICAL EXAMPLE OF
THE LAPLACE TRANSFORM 410 B.4 SOME BASIC PROPERTIES OF THE LAPLACE
TRANSFORM 413 B.4.1 ADDITION THEOREM 413 B.4.2 MULTIPLICATION BY A
CONSTANT FACTOR K 414 B.4.3 MULTIPLICATION OF SIGNALS 414 B.4.4 DELAY IN
THE TIME DOMAIN 415 B.4.5 DIFFERENTIATION AND INTEGRATION IN THE TIME
DOMAIN 415 B.4.6 THE INITIAL-AND FINAL-VALUE THEOREMS 419 B.5 USING THE
TABLE OF LAPLACE TRANSFORMS 420 B.6 APPLYING THE LAPLACE TRANSFORM TO
ELECTRIC NETWORKS 420 B.7 CLOSING THE GAP BETWEEN THE TIME DOMAIN AND
THE COMPLEX FREQUENCY DOMAIN 424 B.8 NETWORKS WITH NONZERO STORED ENERGY
AT F = 0 425 B.9 ANALYZING DYNAMIC PERFORMANCE BY THE POLE-ZERO PLOT 426
B.10 A SIMPLE PHYSICAL INTERPRETATION OF COMPLEX FREQUENCY 429
APPENDIX C. DIGITAL FILTER BASICS 431 C.1 THE TRANSFER FUNCTION H(Z) OF
DIGITAL FILTERS 431 C.2 MR FILTERS 433 C.2.1 THE IMPULSE-INVARIANT
Z-TRANSFORM 434 C.2.2 THE BILINEAR Z-TRANSFORM 441 C.3 FIR FILTERS 446
C.3.1 WINDOW-FIR FILTERS 450 C.3.2 DESIGNING FIR FILTERS WITH THE
PARKS-MCCLELLAN ALGORITHM 454 APPENDIX D. MEASURING PLL PARAMETERS 461
D.1 MEASUREMENT OF CENTER FREQUENCY F 0 461 D.2 MEASUREMENT OF VCO GAIN
K O 462 D.3 MEASUREMENT OF PHASE-DETECTOR GAIN K D 463 D.4 MEASUREMENT
OF HOLD RANGE ATO H AND PULL-IN RANGE AO P 465 D.5 MEASUREMENT OF
NATURAL FREQUENCY CO N , DAMPING FACTOR F, AND LOCK RANGE AA L 467
REFERENCES 473 INDEX 477
|
| adam_txt |
PHASE-LOCKED LOOPS DESIGN, SIMULATION, AND APPLICATIONS ROLAND E. BEST
SIXTH EDITION ME GRAW HILL NEW YORK CHICAGO SAN FRANCISCO LISBON LONDON
MADRID MEXICO CITY MILAN NEW DELHI SAN JUAN SEOUL SINGAPORE SYDNEY
TORONTO CONTENTS PREFACE XI CHAPTER 1. INTRODUCTION TO PLLS 1 1.1
OPERATING PRINCIPLES OF THE PLL 1 1.2 HISTORICAL BACKGROUND 5 1.3
CLASSIFICATION OF PLL TYPES 6 CHAPTER 2. MIXED-SIGNAL PLL BUILDING
BLOCKS 9 2.1 BLOCK DIAGRAM OF THE MIXED-SIGNAL PLL 9 2.2 A NOTE ON PHASE
SIGNALS 10 2.3 BUILDING BLOCKS OF MIXED-SIGNAL PLLS 12 2.4 PHASE
DETECTORS 13 2.4.1 TYPE 1: MULTIPLIER PHASE DETECTORS 13 2.4.2 TYPE 2:
EXOR PHASE DETECTORS 16 2.4.3 TYPE 3: JK-FLIPFLOP PHASE DETECTORS 18
2.4.4 TYPE 4: PHASE-FREQUENCY DETECTORS (PFDS) 20 2.5 LOOP FILTERS
(FIRST ORDER) 28 2.5.1 TYPE 1: PASSIVE LEAD-LAG FILTERS 29 2.5.2 TYPE 2:
ACTIVE LEAD-LAG FILTERS 30 2.5.3 TYPE 3: ACTIVE PI FILTERS 31 2.6
CONTROLLED OSCILLATORS 32 2.6.1 RELAXATION OSCILLATORS 32 2.6.2 RESONANT
OSCILLATORS 36 2.7 DOWN SEALERS 36 CHAPTER 3. MIXED-SIGNAL PLL ANALYSIS
39 3.1 PLL PERFORMANCE IN THE LOCKED STATE 39 3.2 THE MATHEMATICAL MODEL
FOR THE LOCKED STATE 39 3.3 A DEFINITION OF TRANSFER FUNCTIONS 41 3.3.1
THE PLL TRANSFER FUNCTION FOR SYSTEMS USING THE VOLTAGE OUTPUT PHASE
DETECTOR 41 3.3.2 THE PLL TRANSFER FUNCTION FOR SYSTEMS USING CURRENT
OUTPUT PHASE DETECTOR 46 3.4 TRANSIENT RESPONSE OF THE PLL IN THE LOCKED
STATE 47 3.4.1 PHASE STEP APPLIED TO THE REFERENCE INPUT 47 3.4.2
FREQUENCY STEP APPLIED TO THE REFERENCE INPUT 48 3.4.3 FREQUENCY RAMP
APPLIED TO THE REFERENCE INPUT 49 VI CONTENTS 3.5 STEADY-STATE ERROR OF
THE PLL 50 3.6 THE ORDER OF THE PLL SYSTEM 52 3.6.1 THE NUMBER OF POLES
52 3.6.2 A SPECIAL CASE: THE FIRST-ORDER PLL 53 3.7 PLL PERFORMANCE IN
THE UNLOCKED STATE 53 3.8 MATHEMATICAL MODEL FOR THE UNLOCKED STATE 53
3.9 KEY PARAMETERS OF THE PLL 62 3.9.1 HOLD RANGE A H 62 3.9.2 LOCK
RANGE ATO L AND LOCK TIME T L 65 3.9.3 PULL-IN RANGE AM P AND PULL-IN
TIME T P 71 3.9.4 PULL-OUT RANGE A(O PO 83 3.10 OPTIMIZING THE LOCK
PROCESS 86 3.10.1 FASTLOCK TECHNIQUES 87 3.10.2 CYCLE SLIP REDUCTION
(CSR) 89 3.11 IN-LOCK DETECTORS 91 CHAPTER 4. PLL PERFORMANCE IN THE
PRESENCE OF NOISE 93 4.1 SOURCES AND TYPES OF NOISE IN A PLL 93 4.2
DEFINING NOISE PARAMETERS 95 4.3 THE IMPACT OF NOISE ON PLL PERFORMANCE
96 4.4 PULL-IN TECHNIQUES FOR NOISY SIGNALS 104 4.4.1 THE SWEEP
TECHNIQUE 104 4.4.2 THE SWITCHED-FILTER TECHNIQUE 106 CHAPTER 5. DESIGN
PROCEDURE FOR MIXED-SIGNAL PLLS 107 CHAPTER 6. MIXED-SIGNAL PLL
APPLICATIONS PART 1: INTEGER-A/ FREQUENCY SYNTHESIZERS 119 6.1
SYNTHESIZERS IN WIRELESS AND RF APPLICATIONS 119 6.2 INTEGER-AT
FREQUENCY SYNTHESIZERS WITHOUT PRESCALERS 120 6.3 INTEGER- N FREQUENCY
SYNTHESIZERS WITH PRESCALERS 121 6.3.1 FIXED DIVISION RATIO PRESCALERS
121 6.3.2 DUAL-MODULUS PRESCALERS 122 6.3.3 FOUR-MODULUS PRESCALERS 124
6.4 EXTENDING THE FREQUENCY RANGE WITH MIXERS AND FREQUENCY MULTIPLIERS
126 6.5 CASE STUDY: DESIGNING AN INTEGER-A/ PLL FREQUENCY SYNTHESIZER
128 6.6 SINGLE-LOOP AND MULTI-LOOP FREQUENCY SYNTHESIZERS 131 6.7 PHASE
NOISE AND SPURS IN INTEGER FREQUENCY SYNTHESIZERS 134 6.7.1 PHASE NOISE
CREATED BY THE REFERENCE OSCILLATOR 136 6.7.2 PHASE NOISE CREATED BY THE
VCO 145 6.7.3 SPURS CREATED BY THE PHASE DETECTOR 150 CHAPTER 7.
MIXED-SIGNAL PLL APPLICATIONS PART 2: FRACTIONAL-A/ FREQUENCY
SYNTHESIZERS 159 7.1 REALIZATION OF FRACTIONAL DIVIDER RATIOS 159 7.2
ANALOG SPUR REDUCTION TECHNIQUES 161 7.3 DIGITAL SPUR REDUCTION
TECHNIQUES 165 7.4 REVIEWING THE XA MODULATOR 166 * ' 7.4.1 THE 2A A/D
CONVERTER 166 7.4.2 THE 2 A D/A CONVERTER 181 7.4.3 THE XA MODULATOR
USED IN FREQUENCY SYNTHESIZERS 183 7.4.4 NONLINEAR EFFECTS IN XA
MODULATORS 193 CONTENTS VII 7.5 THE DESIGN PROCEDURE FOR XA MODULATORS
194 7.6 SPURS, FRACTIONAL SPURS, AND SUBFRACTIONAL SPURS 196 7.7
ALTERNATIVE XA MODULATORS: THE MASH CONVERTER 197 CHAPTER 8.
MIXED-SIGNAL PLL APPLICATIONS PART 3: MISCELLANEOUS APPLICATIONS 203 8.1
RETIMING AND CLOCK SIGNAL RECOVERY 203 8.2 MOTOR-SPEED CONTROL 210
CHAPTER 9. HIGHER-ORDER LOOPS 217 9.1 MOTIVATION FOR HIGHER-ORDER LOOPS
217 9.2 ANALYZING THE STABILITY OF HIGHER-ORDER LOOPS 217 9.3 DESIGNING
THIRD-ORDER PLLS 220 9.3.1 THE PASSIVE LEAD-LAG LOOP FILTER FOR VOLTAGE
INPUT 221 9.3.2 PASSIVE LEAD-LAG LOOP FILTER FOR CURRENT INPUT 223 9.3.3
ACTIVE LEAD-LAG LOOP FILTER 225 9.3.4 ACTIVE PI LOOP FILTER 227 9.4
DESIGNING FOURTH-ORDER PLLS 230 9.4.1 PASSIVE LEAD-LAG LOOP FILTERS FOR
VOLTAGE INPUT 230 9.4.2 THE PASSIVE LEAD-LAG LOOP FILTER FOR CURRENT
INPUT 233 9.4.3 THE ACTIVE LEAD-LAG LOOP FILTER 235 9.4.4 THE ACTIVE PI
LOOP FILTER 238 9.5 DESIGNING FIFTH-ORDER PLLS 241 9.5.1 PASSIVE
LEAD-LAG LOOP FILTER FOR VOLTAGE INPUT 242 9.5.2 THE PASSIVE LEAD-LAG
LOOP FILTER FOR CURRENT INPUT 244 9.5.3 ACTIVE LEAD-LAG LOOP FILTER 247
9.5.4 ACTIVE PI LOOP FILTER 251 9.6 THE KEY PARAMETERS OF HIGHER-ORDER
PLLS 255 CHAPTER 10. COMPUTER-AIDED DESIGN AND SIMULATION OF
MIXED-SIGNAL PLLS 257 10.1 OVERVIEW 257 10.2 QUICK TOUR 259 10.2.1
CONFIGURING THE PLL SYSTEM 259 10.2.2 DESIGNING THE LOOP FILTER 260
10.2.3 ANALYZING THE STABILITY OF THE LOOP 261 10.2.4 GETTING THE LOOP
FILTER SCHEMATIC 262 10.2.5 RUNNING SIMULATIONS 263 10.3 SIMULATIONS
WITH AND WITHOUT AVERAGING 264 10.4 SIMULATIONS WITH NOISY REFERENCE
SIGNALS 266 10.5 DISPLAYING WAVEFORMS OF TRI-STATE SIGNALS 267 10.6
GETTING HELP 268 10.7 SHAPING THE APPEARANCE OF GRAPHIC OBJECTS 268 10.8
SUGGESTIONS FOR CASE STUDIES 269 CHAPTER 11. ALL-DIGITAL PLLS (ADPLLS)
271 11.1 ADPLL COMPONENTS 271 11.1.1 ALL-DIGITAL PHASE DETECTORS 271
11.1.2 ALL-DIGITAL LOOP FILTERS 277 11.1.3 DIGITAL-CONTROLLED
OSCILLATORS 282 11.2 EXAMPLES OF IMPLEMENTED ADPLLS 286 VIII CONTENTS
11.3 THEORY OF A SELECTED TYPE OF ADPLL 292 11.3.1 THE EFFECTS OF
DISCRETE-TIME OPERATION 293 11.3.2 THE HOLD RANGE OF THE ADPLL 298
11.3.3 FREQUENCY-DOMAIN ANALYSIS OF THE ADPLL 30.1 11.3.4 RIPPLE
REDUCTION TECHNIQUES 303 11.3.5 HIGHER-ORDER ADPLLS 304 11.4 TYPICAL
ADPLL APPLICATIONS 305 11.5 DESIGNING AN ADPLL 307 11.5.1 CASE STUDY:
DESIGNING AN ADPLL FSK DECODER 307 CHAPTER 12. COMPUTER-AIDED DESIGN AND
SIMULATION OF ADPLLS 311 12.1 DESIGNING THE ADPLL 311 12.2 SIMULATING
ADPLL PERFORMANCE 313 12.3 CASE STUDIES ON ADPLL BEHAVIOR 314 CHAPTER
13. THE SOFTWARE PLL (SPLL) 321 13.1 THE HARDWARE-SOFTWARE TRADE-OFF 321
13.2 THE FEASIBILITY OF AN SPLL DESIGN 322 13.3 SPLL EXAMPLES 323 13.3.1
AN LPLL-LIKE SPLL 324 13.3.2 A DPLL-LIKE SPLL 330 13.3.3 A NOTE ON
ADPLL-LIKE SPLLS 339 CHAPTER 14. THE PLL IN COMMUNICATIONS 341 14.1
TYPES OF COMMUNICATIONS: BASEBAND AND BANDPASS 341 14.2 AMPLITUDE SHIFT
KEYING 343 14.3 PHASE SHIFT KEYING 343 14.3.1 BINARY PHASE SHIFT KEYING
(BPSK) 343 14.3.2 QUADRATURE PHASE SHIFT KEYING 345 14.3.3 OFFSET
QUADRATURE PSK (OQPSK) 346 14.3.4 M-ARYPSK 347 14.3.5 DIFFERENTIAL PSK
(DPSK) 347 14.4 FREQUENCY SHIFT KEYING 348 14.4.1 BINARY FSK 348 14.4.2
M-ARYFSK 350 14.4.3 MINIMUM SHIFT KEYING (MSK) AND GAUSSIAN MSK (GMSK)
351 14.5 QUADRATURE AMPLITUDE MODULATION (QAM) 355 14.6 THE ROLE OF
SYNCHRONIZATION IN DIGITAL COMMUNICATIONS 356 14.7 DIGITAL
COMMUNICATIONS USING BPSK 357 14.7.1 TRANSMITTER CONSIDERATIONS 357
14.7.2 RECEIVER CONSIDERATIONS 362 14.8 DIGITAL COMMUNICATIONS USING
QPSK 372 14.8.1 TRANSMITTER CONSIDERATIONS 372 14.8.2 RECEIVER
CONSIDERATIONS 373 14.9 DIGITAL COMMUNICATIONS USING QAM 375 14.10
DIGITAL COMMUNICATIONS USING FSK 377 14.10.1 SIMPLE FSK DECODERS: EASY
TO IMPLEMENT, BUT NOT EFFECTIVE 377 14.10.2 COHERENT FSK DETECTION 379
14.10.3 NONCOHERENT FSK DETECTION AND QUADRATURE FSK DECODERS 380 14.11
DIGITAL COMMUNICATIONS IN MOBILE PHONES 381 14.12 BANDWIDTH EFFICIENCY,
BIT ERROR RATE (BER), AND THE SIGNAL POWER EFFICIENCY OF DIGITAL
MODULATION SCHEMES 382 CONTENTS IX CHAPTER 15. SEARCHING PLL INTEGRATED
CIRCUITS 385 APPENDIX A. THE PULL-IN PROCESS 389 A.1 THE SIMPLIFIED
MODEL FOR THE PULL-IN RANGE A P OF THE LPLL 389 A.2 A SIMPLIFIED MODEL
FOR THE PULL-IN TIME T P OF THE LPLL 396 A.3 THE PULL-IN RANGE A P OF
THE DPLL 399 A.4 THE PULL-IN TIME T P OF THE DPLL 401 APPENDIX B. THE
LAPLACE TRANSFORM 403 B.1 TRANSFORMS ARE THE ENGINEER'S TOOLS 403 B.2
LAPLACE TRANSFORM IS THE KEY TO SUCCESS 406 B.3 A NUMERICAL EXAMPLE OF
THE LAPLACE TRANSFORM 410 B.4 SOME BASIC PROPERTIES OF THE LAPLACE
TRANSFORM 413 B.4.1 ADDITION THEOREM 413 B.4.2 MULTIPLICATION BY A
CONSTANT FACTOR K 414 B.4.3 MULTIPLICATION OF SIGNALS 414 B.4.4 DELAY IN
THE TIME DOMAIN 415 B.4.5 DIFFERENTIATION AND INTEGRATION IN THE TIME
DOMAIN 415 B.4.6 THE INITIAL-AND FINAL-VALUE THEOREMS 419 B.5 USING THE
TABLE OF LAPLACE TRANSFORMS 420 B.6 APPLYING THE LAPLACE TRANSFORM TO
ELECTRIC NETWORKS 420 B.7 CLOSING THE GAP BETWEEN THE TIME DOMAIN AND
THE COMPLEX FREQUENCY DOMAIN 424 B.8 NETWORKS WITH NONZERO STORED ENERGY
AT F = 0 425 B.9 ANALYZING DYNAMIC PERFORMANCE BY THE POLE-ZERO PLOT 426
B.10 A SIMPLE PHYSICAL INTERPRETATION OF "COMPLEX FREQUENCY" 429
APPENDIX C. DIGITAL FILTER BASICS 431 C.1 THE TRANSFER FUNCTION H(Z) OF
DIGITAL FILTERS 431 C.2 MR FILTERS 433 C.2.1 THE IMPULSE-INVARIANT
Z-TRANSFORM 434 C.2.2 THE BILINEAR Z-TRANSFORM 441 C.3 FIR FILTERS 446
C.3.1 WINDOW-FIR FILTERS 450 C.3.2 DESIGNING FIR FILTERS WITH THE
PARKS-MCCLELLAN ALGORITHM 454 APPENDIX D. MEASURING PLL PARAMETERS 461
D.1 MEASUREMENT OF CENTER FREQUENCY F 0 461 D.2 MEASUREMENT OF VCO GAIN
K O 462 D.3 MEASUREMENT OF PHASE-DETECTOR GAIN K D 463 D.4 MEASUREMENT
OF HOLD RANGE ATO H AND PULL-IN RANGE AO P 465 D.5 MEASUREMENT OF
NATURAL FREQUENCY CO N , DAMPING FACTOR F, AND LOCK RANGE AA L 467
REFERENCES 473 INDEX '" 477 |
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| dewey-search | 621.3815/364 |
| dewey-sort | 3621.3815 3364 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 6. ed. |
| format | Book |
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| id | DE-604.BV022787197 |
| illustrated | Illustrated |
| index_date | 2024-07-02T18:38:31Z |
| indexdate | 2024-07-09T21:06:08Z |
| institution | BVB |
| isbn | 0071493751 9780071493758 9780071499262 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015992614 |
| oclc_num | 124538945 |
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| owner_facet | DE-91G DE-BY-TUM DE-634 DE-83 DE-706 DE-92 DE-19 DE-BY-UBM DE-859 |
| physical | XII, 482 S. Ill., graph. Darst. 1 CD-ROM (12 cm) |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | McGraw-Hill |
| record_format | marc |
| series2 | McGraw-Hill professional engineering |
| spelling | Best, Roland E. 1935- Verfasser (DE-588)128432152 aut Phase locked loops design, simulation, and applications Roland E. Best Phase-locked loops 6. ed. New York [u.a.] McGraw-Hill 2007 XII, 482 S. Ill., graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier McGraw-Hill professional engineering Phasenregelkreis (DE-588)4174166-3 gnd rswk-swf Phasenregelkreis (DE-588)4174166-3 s DE-604 http://catdir.loc.gov/catdir/enhancements/fy0726/2007019390-d.html Beschreibung für Leser HEBIS Datenaustausch Darmstadt application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015992614&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Best, Roland E. 1935- Phase locked loops design, simulation, and applications Phase-locked loops Phasenregelkreis (DE-588)4174166-3 gnd |
| subject_GND | (DE-588)4174166-3 |
| title | Phase locked loops design, simulation, and applications |
| title_alt | Phase-locked loops |
| title_auth | Phase locked loops design, simulation, and applications |
| title_exact_search | Phase locked loops design, simulation, and applications |
| title_exact_search_txtP | Phase locked loops design, simulation, and applications |
| title_full | Phase locked loops design, simulation, and applications Roland E. Best |
| title_fullStr | Phase locked loops design, simulation, and applications Roland E. Best |
| title_full_unstemmed | Phase locked loops design, simulation, and applications Roland E. Best |
| title_short | Phase locked loops |
| title_sort | phase locked loops design simulation and applications |
| title_sub | design, simulation, and applications |
| topic | Phase-locked loops Phasenregelkreis (DE-588)4174166-3 gnd |
| topic_facet | Phase-locked loops Phasenregelkreis |
| url | http://catdir.loc.gov/catdir/enhancements/fy0726/2007019390-d.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015992614&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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