Holdings: Advanced FPGA design

Advanced FPGA design: architecture, implementation and optimization

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Bibliographic Details
Main Author:	Kilts, Steve (Author)
Format:	Book
Language:	English
Published:	Hoboken, N.J. Wiley 2007
Subjects:	Field programmable gate arrays > Design and construction Field programmable gate array
Online Access:	Table of contents only Contributor biographical information Publisher description Inhaltsverzeichnis
Item Description:	Includes index.
Physical Description:	XV, 336 S. graph. Darst.
ISBN:	0470054379 9780470054376

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Record in the Search Index

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adam_text	ADVANCED FPGA DESIGN ARCHITECTURE, IMPLEMENTATION, AND OPTIMIZATION STEVE KILTS SPECTRUM DESIGN SOLUTIONS MINNEAPOLIS, MINNESOTA THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC., NEW YORK WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS PREFACE ACKNOWLEDGMENTS 1. ARCHITECTING SPEED XIII XV 1 .1 .2 .3 HIGH THROUGHPUT 2 LOW LATENCY 4 TIMING 6 1.3.1 ADD REGISTER LAYERS I 1.3.2 PARALLEL STRUCTURES 8 1.3.3 FLATTEN LOGIC STRUCTURES 1.3.4 REGISTER BALANCING 12 1.3.5 REORDER PATHS 14 1.4 SUMMARY OF KEY POINTS 16 2. ARCHITECTING AREA 17 2.1 ROLLING UP THE PIPELINE 18 2.2 CONTROL-BASED LOGIC REUSE 20 2.3 RESOURCE SHARING 23 2.4 IMPACT OF RESET ON AREA 25 2.4.1 RESOURCES WITHOUT RESET 25 2.4.2 RESOURCES WITHOUT SET 26 2.4.3 RESOURCES WITHOUT ASYNCHRONOUS RESET 27 2.4.4 RESETTING RAM 29 2.4.5 UTILIZING SET/RESET FLIP-FLOP PINS 31 2.5 SUMMARY OF KEY POINTS 34 3. ARCHITECTING POWER 37 3.1 CLOCK CONTROL 38 3.1.1 CLOCK SKEW 39 3.1.2 MANAGING SKEW 40 VLL VIUE CONTENTS 3.2 INPUT CONTROL 42 3.3 REDUCING THE VOLTAGE SUPPLY 44 3.4 DUAL-EDGE TRIGGERED FLIP-FLOPS 44 3.5 MODIFYING TERMINATIONS 45 3.6 SUMMARY OF KEY POINTS 46 4. EXAMPLE DESIGN: THE ADVANCED ENCRYPTION STANDARD 47 4.1 AES ARCHITECTURES 47 4.1.1 ONE STAGE FOR SUB-BYTES 51 4.1.2 ZERO STAGES FOR SHIFT ROWS 51 4.1.3 TWO PIPELINE STAGES FOR MIX-COLUMN 52 4.1.4 ONE STAGE FOR ADD ROUND KEY 52 4.1.5 COMPACT ARCHITECTURE 53 4.1.6 PARTIALLY PIPELINED ARCHITECTURE 57 4.1.7 FULLY PIPELINED ARCHITECTURE 60 4.2 PERFORMANCE VERSUS AREA 66 4.3 OTHER OPTIMIZATIONS 67 5. HIGH-LEVEL DESIGN 69 5.1 ABSTRACT DESIGN TECHNIQUES 69 5.2 GRAPHICAL STATE MACHINES 70 5.3 DSP DESIGN 75 5.4 SOFTWARE/HARDWARE CODESIGN 80 5.5 SUMMARY OF KEY POINTS 81 6. CLOCK DOMAINS 83 6.1 CROSSING CLOCK DOMAINS 84 6.1.1 METASTABILITY 86 6.1.2 SOLUTION 1: PHASE CONTROL 88 6.1.3 SOLUTION 2: DOUBLE FLOPPING 89 6.1.4 SOLUTION 3: FIFO STRUCTURE 92 6.1.5 PARTITIONING SYNCHRONIZER BLOCKS 97 6.2 GATED CLOCKS IN ASIC PROTOTYPES 97 6.2.1 CLOCKS MODULE 98 6.2.2 GATING REMOVAL 99 6.3 SUMMARY OF KEY POINTS 100 7. EXAMPLE DESIGN: I2S VERSUS SPDIF 101 7.1 I2S 101 7.1.1 PROTOCOL 102 7.1.2 HARDWARE ARCHITECTURE 102 CONTENTS IX 7.1.3 ANALYSIS 105 7.2 SPDIF 107 7.2.1 PROTOCOL 107 7.2.2 HARDWARE ARCHITECTURE 108 7.2.3 ANALYSIS 114 8. IMPLEMENTING MATH FUNCTIONS 117 8.1 HARDWARE DIVISION 117 8.1.1 MULTIPLY AND SHIFT 118 8.1.2 ITERATIVE DIVISION 119 8.1.3 THE GOLDSCHMIDT METHOD 120 8.2 TAYLOR AND MACLAURIN SERIES EXPANSION 122 8.3 THE CORDIC ALGORITHM 124 8.4 SUMMARY OF KEY POINTS 126 9. EXAMPLE DESIGN: FLOATING-POINT UNIT 127 9.1 FLOATING-POINT FORMATS 127 9.2 PIPELINED ARCHITECTURE 128 9.2.1 VERILOG IMPLEMENTATION 131 9.2.2 RESOURCES AND PERFORMANCE 137 10. RESET CIRCUITS 139 10.1 ASYNCHRONOUS VERSUS SYNCHRONOUS 140 10.1.1 PROBLEMS WITH FULLY ASYNCHRONOUS RESETS 140 10.1.2 FULLY SYNCHRONIZED RESETS 142 10.1.3 ASYNCHRONOUS ASSERTION, SYNCHRONOUS DEASSERTION 144 10.2 MIXING RESET TYPES 145 10.2.1 NONRESETABLE FLIP-FLOPS 145 10.2.2 INTERNALLY GENERATED RESETS 146 10.3 MULTIPLE CLOCK DOMAINS 148 10.4 SUMMARY OF KEY POINTS 149 11. ADVANCE D SIMULATION 151 11.1 TESTBENCH ARCHITECTURE 152 11.1.1 TESTBENCH COMPONENTS 152 11.1.2 TESTBENCH FLOW 153 11.1.2.1 MAINTHREAD 153 11.1.2.2 CLOCKS AND RESETS 154 11.1.2.3 TESTCASES 155 X CONTENTS 11.2 SYSTEM STIMULUS 157 11.2.1 MATLAB 157 11.2.2 BUS-FUNCTIONAL MODELS 158 11.3 CODECOVERAGE 159 11.4 GATE-LEVEL SIMULATIONS 159 11.5 TOGGLE COVERAGE 162 11.6 RUN-TIME TRAPS 165 11.6.1 TIMESCALE 165 11.6.2 GLITCH REJECTION 165 11.6.3 COMBMATORIAL DELAY MODELING 166 11.7 SUMMARY OF KEY POINTS 169 12. CODING FOR SYNTHESIS 171 12.1 DECISION TREES 172 12.1.1 PRIORITY VERSUS PARALLEL 172 12.1.2 FUELL CONDITIONS 176 12.1.3 MULTIPLE CONTROL BRANCHES 179 12.2 TRAPS 180 12.2.1 BLOCKING VERSUS NONBLOCKING 180 12.2.2 FOR-LOOPS 183 12.2.3 COMBMATORIAL LOOPS 185 12.2.4 INFERRED LATCHES 187 12.3 DESIGN ORGANIZATION 188 12.3.1 PARTITIONING 188 12.3.1.1 DATA PATH VERSUS CONTROL 188 12.3.1.2 CLOCK AND RESET STRUCTURES 189 12.3.1.3 MULTIPLE INSTANTIATIONS 190 12.3.2 PARAMETERIZATION 191 12.3.2.1 DEFINITIONS 191 12.3.2.2 PARAMETERS 192 12.3.2.3 PARAMETERS IN VERILOG-2001 194 12.4 SUMMARY OF KEY POINTS 195 13. EXAMPLE DESIGN: THE SECURE HASH ALGORITHM 197 13.1 SHA-1 ARCHITECTURE 197 13.2 IMPLEMENTATION RESULTS 204 14. SYNTHESIS OPTIMIZATION 205 14.1 SPEED VERSUS AREA 206 14.2 RESOURCE SHARING 208 CONTENTS XI 14.3 PIPELINING, RETIMING, AND REGISTER BALANCING 211 14.3.1 THE EFFECT OF RESET ON REGISTER BALANCING 213 14.3.2 RESYNCHRONIZATION REGISTERS 215 14.4 FSM COMPILATION 216 14.4.1 REMOVAL OF UNREACHABLE STATES 219 14.5 BLACK BOXES 220 14.6 PHYSICAL SYNTHESIS 223 14.6.1 FORWARD ANNOTATION VERSUS BACK-ANNOTATION 224 14.6.2 GRAPH-BASED PHYSICAL SYNTHESIS 225 14.7 SUMMARY OF KEY POINTS 226 15. FLOORPLANNING 229 15.1 DESIGN PARTITIONING 229 15.2 CRITICAL-PATH FLOORPLANNING 232 15.3 FLOORPLANNING DANGERS 233 15.4 OPTIMAL FLOORPLANNING 234 15.4.1 DATAPATH 234 15.4.2 HIGHFAN-OUT 234 15.4.3 DEVICE STRUCTURE 235 15.4.4 REUSABILITY 238 15.5 REDUCING POWER DISSIPATION 238 15.6 SUMMARY OF KEY POINTS 240 16. PLACE AND ROUTE OPTIMIZATION 241 16.1 OPTIMAL CONSTRAINTS 241 16.2 RELATIONSHIP BETWEEN PLACEMENT AND ROUTING 244 16.3 LOGIC REPLICATION 246 16.4 OPTIMIZATION ACROSS HIERARCHY 247 16.5 I/O REGISTERS 248 16.6 PACK FACTOR 250 16.7 MAPPING LOGIC INTO RAM 251 16.8 REGISTER ORDERING 251 16.9 PLACEMENT SEED 252 16.10 GUIDED PLACE AND ROUTE 254 16.11 SUMMARY OF KEY POINTS 254 17. EXAMPLE DESIGN: MICROPROCESSOR 257 17.1 SRC ARCHITECTURE 257 17.2 SYNTHESIS OPTIMIZATIONS 259 17.2.1 SPEED VERSUS AREA 260 XII CONTENTS 17.2.2 PIPELINING 261 17.2.3 PHYSICAL SYNTHESIS 262 17.3 FLOORPLAN OPTIMIZATIONS 262 17.3.1 PARTITIONED FLOORPLAN 263 17.3.2 CRITICAL-PATH FLOORPLAN: ABSTRACTION 1 264 17.3.3 CRITICAL-PATH FLOORPLAN: ABSTRACTION 2 265 18. STATIC TIMING ANALYSIS 269 18.1 STANDARD ANALYSIS 269 18.2 LATCHES 273 18.3 ASYNCHRONOUS CIRCUITS 276 18.3.1 COMBINATORIAL FEEDBACK 277 18.4 SUMMARY OF KEY POINTS 278 19. PCBISSUES 279 19.1 POWER SUPPLY 279 19.1.1 SUPPLY REQUIREMENTS 279 19.1.2 REGULATION 283 19.2 DECOUPLING CAPACITORS 283 19.2.1 CONCEPT 283 19.2.2 CALCULATING VALUES 285 19.2.3 CAPACITOR PLACEMENT 286 19.3 SUMMARY OF KEY POINTS 288 APPENDIX A APPENDIX B BIBLIOGRAPHY 289 303 319 INDEX 321
adam_txt	ADVANCED FPGA DESIGN ARCHITECTURE, IMPLEMENTATION, AND OPTIMIZATION STEVE KILTS SPECTRUM DESIGN SOLUTIONS MINNEAPOLIS, MINNESOTA THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC., NEW YORK WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS PREFACE ACKNOWLEDGMENTS 1. ARCHITECTING SPEED XIII XV 1 .1 .2 .3 HIGH THROUGHPUT 2 LOW LATENCY 4 TIMING 6 1.3.1 ADD REGISTER LAYERS I 1.3.2 PARALLEL STRUCTURES 8 1.3.3 FLATTEN LOGIC STRUCTURES 1.3.4 REGISTER BALANCING 12 1.3.5 REORDER PATHS 14 1.4 SUMMARY OF KEY POINTS 16 2. ARCHITECTING AREA 17 2.1 ROLLING UP THE PIPELINE 18 2.2 CONTROL-BASED LOGIC REUSE 20 2.3 RESOURCE SHARING 23 2.4 IMPACT OF RESET ON AREA 25 2.4.1 RESOURCES WITHOUT RESET 25 2.4.2 RESOURCES WITHOUT SET 26 2.4.3 RESOURCES WITHOUT ASYNCHRONOUS RESET 27 2.4.4 RESETTING RAM 29 2.4.5 UTILIZING SET/RESET FLIP-FLOP PINS 31 2.5 SUMMARY OF KEY POINTS 34 3. ARCHITECTING POWER 37 3.1 CLOCK CONTROL 38 3.1.1 CLOCK SKEW 39 3.1.2 MANAGING SKEW 40 VLL VIUE CONTENTS 3.2 INPUT CONTROL 42 3.3 REDUCING THE VOLTAGE SUPPLY 44 3.4 DUAL-EDGE TRIGGERED FLIP-FLOPS 44 3.5 MODIFYING TERMINATIONS 45 3.6 SUMMARY OF KEY POINTS 46 4. EXAMPLE DESIGN: THE ADVANCED ENCRYPTION STANDARD 47 4.1 AES ARCHITECTURES 47 4.1.1 ONE STAGE FOR SUB-BYTES 51 4.1.2 ZERO STAGES FOR SHIFT ROWS 51 4.1.3 TWO PIPELINE STAGES FOR MIX-COLUMN 52 4.1.4 ONE STAGE FOR ADD ROUND KEY 52 4.1.5 COMPACT ARCHITECTURE 53 4.1.6 PARTIALLY PIPELINED ARCHITECTURE 57 4.1.7 FULLY PIPELINED ARCHITECTURE 60 4.2 PERFORMANCE VERSUS AREA 66 4.3 OTHER OPTIMIZATIONS 67 5. HIGH-LEVEL DESIGN 69 5.1 ABSTRACT DESIGN TECHNIQUES 69 5.2 GRAPHICAL STATE MACHINES 70 5.3 DSP DESIGN 75 5.4 SOFTWARE/HARDWARE CODESIGN 80 5.5 SUMMARY OF KEY POINTS 81 6. CLOCK DOMAINS 83 6.1 CROSSING CLOCK DOMAINS 84 6.1.1 METASTABILITY 86 6.1.2 SOLUTION 1: PHASE CONTROL 88 6.1.3 SOLUTION 2: DOUBLE FLOPPING 89 6.1.4 SOLUTION 3: FIFO STRUCTURE 92 6.1.5 PARTITIONING SYNCHRONIZER BLOCKS 97 6.2 GATED CLOCKS IN ASIC PROTOTYPES 97 6.2.1 CLOCKS MODULE 98 6.2.2 GATING REMOVAL 99 6.3 SUMMARY OF KEY POINTS 100 7. EXAMPLE DESIGN: I2S VERSUS SPDIF 101 7.1 I2S 101 7.1.1 PROTOCOL 102 7.1.2 HARDWARE ARCHITECTURE 102 CONTENTS IX 7.1.3 ANALYSIS 105 7.2 SPDIF 107 7.2.1 PROTOCOL 107 7.2.2 HARDWARE ARCHITECTURE 108 7.2.3 ANALYSIS 114 8. IMPLEMENTING MATH FUNCTIONS 117 8.1 HARDWARE DIVISION 117 8.1.1 MULTIPLY AND SHIFT 118 8.1.2 ITERATIVE DIVISION 119 8.1.3 THE GOLDSCHMIDT METHOD 120 8.2 TAYLOR AND MACLAURIN SERIES EXPANSION 122 8.3 THE CORDIC ALGORITHM 124 8.4 SUMMARY OF KEY POINTS 126 9. EXAMPLE DESIGN: FLOATING-POINT UNIT 127 9.1 FLOATING-POINT FORMATS 127 9.2 PIPELINED ARCHITECTURE 128 9.2.1 VERILOG IMPLEMENTATION 131 9.2.2 RESOURCES AND PERFORMANCE 137 10. RESET CIRCUITS 139 10.1 ASYNCHRONOUS VERSUS SYNCHRONOUS 140 10.1.1 PROBLEMS WITH FULLY ASYNCHRONOUS RESETS 140 10.1.2 FULLY SYNCHRONIZED RESETS 142 10.1.3 ASYNCHRONOUS ASSERTION, SYNCHRONOUS DEASSERTION 144 10.2 MIXING RESET TYPES 145 10.2.1 NONRESETABLE FLIP-FLOPS 145 10.2.2 INTERNALLY GENERATED RESETS 146 10.3 MULTIPLE CLOCK DOMAINS 148 10.4 SUMMARY OF KEY POINTS 149 11. ADVANCE D SIMULATION 151 11.1 TESTBENCH ARCHITECTURE 152 11.1.1 TESTBENCH COMPONENTS 152 11.1.2 TESTBENCH FLOW 153 11.1.2.1 MAINTHREAD 153 11.1.2.2 CLOCKS AND RESETS 154 11.1.2.3 TESTCASES 155 X CONTENTS 11.2 SYSTEM STIMULUS 157 11.2.1 MATLAB 157 11.2.2 BUS-FUNCTIONAL MODELS 158 11.3 CODECOVERAGE 159 11.4 GATE-LEVEL SIMULATIONS 159 11.5 TOGGLE COVERAGE 162 11.6 RUN-TIME TRAPS 165 11.6.1 TIMESCALE 165 11.6.2 GLITCH REJECTION 165 11.6.3 COMBMATORIAL DELAY MODELING 166 11.7 SUMMARY OF KEY POINTS 169 12. CODING FOR SYNTHESIS 171 12.1 DECISION TREES 172 12.1.1 PRIORITY VERSUS PARALLEL 172 12.1.2 FUELL CONDITIONS 176 12.1.3 MULTIPLE CONTROL BRANCHES 179 12.2 TRAPS 180 12.2.1 BLOCKING VERSUS NONBLOCKING 180 12.2.2 FOR-LOOPS 183 12.2.3 COMBMATORIAL LOOPS 185 12.2.4 INFERRED LATCHES 187 12.3 DESIGN ORGANIZATION 188 12.3.1 PARTITIONING 188 12.3.1.1 DATA PATH VERSUS CONTROL 188 12.3.1.2 CLOCK AND RESET STRUCTURES 189 12.3.1.3 MULTIPLE INSTANTIATIONS 190 12.3.2 PARAMETERIZATION 191 12.3.2.1 DEFINITIONS 191 12.3.2.2 PARAMETERS 192 12.3.2.3 PARAMETERS IN VERILOG-2001 194 12.4 SUMMARY OF KEY POINTS 195 13. EXAMPLE DESIGN: THE SECURE HASH ALGORITHM 197 13.1 SHA-1 ARCHITECTURE 197 13.2 IMPLEMENTATION RESULTS 204 14. SYNTHESIS OPTIMIZATION 205 14.1 SPEED VERSUS AREA 206 14.2 RESOURCE SHARING 208 CONTENTS XI 14.3 PIPELINING, RETIMING, AND REGISTER BALANCING 211 14.3.1 THE EFFECT OF RESET ON REGISTER BALANCING 213 14.3.2 RESYNCHRONIZATION REGISTERS 215 14.4 FSM COMPILATION 216 14.4.1 REMOVAL OF UNREACHABLE STATES 219 14.5 BLACK BOXES 220 14.6 PHYSICAL SYNTHESIS 223 14.6.1 FORWARD ANNOTATION VERSUS BACK-ANNOTATION 224 14.6.2 GRAPH-BASED PHYSICAL SYNTHESIS 225 14.7 SUMMARY OF KEY POINTS 226 15. FLOORPLANNING 229 15.1 DESIGN PARTITIONING 229 15.2 CRITICAL-PATH FLOORPLANNING 232 15.3 FLOORPLANNING DANGERS 233 15.4 OPTIMAL FLOORPLANNING 234 15.4.1 DATAPATH 234 15.4.2 HIGHFAN-OUT 234 15.4.3 DEVICE STRUCTURE 235 15.4.4 REUSABILITY 238 15.5 REDUCING POWER DISSIPATION 238 15.6 SUMMARY OF KEY POINTS 240 16. PLACE AND ROUTE OPTIMIZATION 241 16.1 OPTIMAL CONSTRAINTS 241 16.2 RELATIONSHIP BETWEEN PLACEMENT AND ROUTING 244 16.3 LOGIC REPLICATION 246 16.4 OPTIMIZATION ACROSS HIERARCHY 247 16.5 I/O REGISTERS 248 16.6 PACK FACTOR 250 16.7 MAPPING LOGIC INTO RAM 251 16.8 REGISTER ORDERING 251 16.9 PLACEMENT SEED 252 16.10 GUIDED PLACE AND ROUTE 254 16.11 SUMMARY OF KEY POINTS 254 17. EXAMPLE DESIGN: MICROPROCESSOR 257 17.1 SRC ARCHITECTURE 257 17.2 SYNTHESIS OPTIMIZATIONS 259 17.2.1 SPEED VERSUS AREA 260 XII CONTENTS 17.2.2 PIPELINING 261 17.2.3 PHYSICAL SYNTHESIS 262 17.3 FLOORPLAN OPTIMIZATIONS 262 17.3.1 PARTITIONED FLOORPLAN 263 17.3.2 CRITICAL-PATH FLOORPLAN: ABSTRACTION 1 264 17.3.3 CRITICAL-PATH FLOORPLAN: ABSTRACTION 2 265 18. STATIC TIMING ANALYSIS 269 18.1 STANDARD ANALYSIS 269 18.2 LATCHES 273 18.3 ASYNCHRONOUS CIRCUITS 276 18.3.1 COMBINATORIAL FEEDBACK 277 18.4 SUMMARY OF KEY POINTS 278 19. PCBISSUES 279 19.1 POWER SUPPLY 279 19.1.1 SUPPLY REQUIREMENTS 279 19.1.2 REGULATION 283 19.2 DECOUPLING CAPACITORS 283 19.2.1 CONCEPT 283 19.2.2 CALCULATING VALUES 285 19.2.3 CAPACITOR PLACEMENT 286 19.3 SUMMARY OF KEY POINTS 288 APPENDIX A APPENDIX B BIBLIOGRAPHY 289 303 319 INDEX 321
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id	DE-604.BV022780553
illustrated	Illustrated
index_date	2024-07-02T18:36:06Z
indexdate	2024-07-09T21:06:00Z
institution	BVB
isbn	0470054379 9780470054376
language	English
lccn	2006033573
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-015986065
oclc_num	72799161
open_access_boolean
owner	DE-1043 DE-898 DE-BY-UBR DE-858 DE-703 DE-634 DE-859 DE-29T DE-83 DE-706
owner_facet	DE-1043 DE-898 DE-BY-UBR DE-858 DE-703 DE-634 DE-859 DE-29T DE-83 DE-706
physical	XV, 336 S. graph. Darst.
publishDate	2007
publishDateSearch	2007
publishDateSort	2007
publisher	Wiley
record_format	marc
spelling	Kilts, Steve Verfasser aut Advanced FPGA design architecture, implementation and optimization Steve Kilts Hoboken, N.J. Wiley 2007 XV, 336 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes index. Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s DE-604 http://www.loc.gov/catdir/toc/ecip072/2006033573.html Table of contents only http://www.loc.gov/catdir/enhancements/fy0739/2006033573-b.html Contributor biographical information http://www.loc.gov/catdir/enhancements/fy0739/2006033573-d.html Publisher description GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015986065&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Kilts, Steve Advanced FPGA design architecture, implementation and optimization Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd
subject_GND	(DE-588)4347749-5
title	Advanced FPGA design architecture, implementation and optimization
title_auth	Advanced FPGA design architecture, implementation and optimization
title_exact_search	Advanced FPGA design architecture, implementation and optimization
title_exact_search_txtP	Advanced FPGA design architecture, implementation and optimization
title_full	Advanced FPGA design architecture, implementation and optimization Steve Kilts
title_fullStr	Advanced FPGA design architecture, implementation and optimization Steve Kilts
title_full_unstemmed	Advanced FPGA design architecture, implementation and optimization Steve Kilts
title_short	Advanced FPGA design
title_sort	advanced fpga design architecture implementation and optimization
title_sub	architecture, implementation and optimization
topic	Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd
topic_facet	Field programmable gate arrays Design and construction Field programmable gate array
url	http://www.loc.gov/catdir/toc/ecip072/2006033573.html http://www.loc.gov/catdir/enhancements/fy0739/2006033573-b.html http://www.loc.gov/catdir/enhancements/fy0739/2006033573-d.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015986065&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT kiltssteve advancedfpgadesignarchitectureimplementationandoptimization

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