Advanced FPGA design: architecture, implementation and optimization
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Hoboken, N.J.
Wiley
2007
|
| Schlagworte: | |
| Online-Zugang: | Table of contents only Contributor biographical information Publisher description Inhaltsverzeichnis |
| Beschreibung: | Includes index. |
| Beschreibung: | XV, 336 S. graph. Darst. |
| ISBN: | 0470054379 9780470054376 |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV022780553 | ||
| 003 | DE-604 | ||
| 005 | 20090408 | ||
| 007 | t | ||
| 008 | 070918s2007 xxud||| |||| 00||| eng d | ||
| 010 | |a 2006033573 | ||
| 020 | |a 0470054379 |c cloth |9 0-470-05437-9 | ||
| 020 | |a 9780470054376 |9 978-0-470-05437-6 | ||
| 035 | |a (OCoLC)72799161 | ||
| 035 | |a (DE-599)BVBBV022780553 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 044 | |a xxu |c US | ||
| 049 | |a DE-1043 |a DE-898 |a DE-858 |a DE-703 |a DE-634 |a DE-859 |a DE-29T |a DE-83 |a DE-706 | ||
| 050 | 0 | |a TK7895.G36 | |
| 082 | 0 | |a 621.39/5 | |
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 084 | |a ZN 4950 |0 (DE-625)157424: |2 rvk | ||
| 084 | |a ZN 5630 |0 (DE-625)157471: |2 rvk | ||
| 100 | 1 | |a Kilts, Steve |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Advanced FPGA design |b architecture, implementation and optimization |c Steve Kilts |
| 264 | 1 | |a Hoboken, N.J. |b Wiley |c 2007 | |
| 300 | |a XV, 336 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes index. | ||
| 650 | 4 | |a Field programmable gate arrays |x Design and construction | |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 856 | 4 | |u http://www.loc.gov/catdir/toc/ecip072/2006033573.html |3 Table of contents only | |
| 856 | 4 | |u http://www.loc.gov/catdir/enhancements/fy0739/2006033573-b.html |3 Contributor biographical information | |
| 856 | 4 | |u http://www.loc.gov/catdir/enhancements/fy0739/2006033573-d.html |3 Publisher description | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015986065&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-015986065 | ||
Datensatz im Suchindex
| _version_ | 1804137042055004160 |
|---|---|
| adam_text | ADVANCED FPGA DESIGN ARCHITECTURE, IMPLEMENTATION, AND OPTIMIZATION
STEVE KILTS SPECTRUM DESIGN SOLUTIONS MINNEAPOLIS, MINNESOTA THE
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC., NEW YORK
WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS
PREFACE ACKNOWLEDGMENTS 1. ARCHITECTING SPEED XIII XV 1 .1 .2 .3 HIGH
THROUGHPUT 2 LOW LATENCY 4 TIMING 6 1.3.1 ADD REGISTER LAYERS I 1.3.2
PARALLEL STRUCTURES 8 1.3.3 FLATTEN LOGIC STRUCTURES 1.3.4 REGISTER
BALANCING 12 1.3.5 REORDER PATHS 14 1.4 SUMMARY OF KEY POINTS 16 2.
ARCHITECTING AREA 17 2.1 ROLLING UP THE PIPELINE 18 2.2 CONTROL-BASED
LOGIC REUSE 20 2.3 RESOURCE SHARING 23 2.4 IMPACT OF RESET ON AREA 25
2.4.1 RESOURCES WITHOUT RESET 25 2.4.2 RESOURCES WITHOUT SET 26 2.4.3
RESOURCES WITHOUT ASYNCHRONOUS RESET 27 2.4.4 RESETTING RAM 29 2.4.5
UTILIZING SET/RESET FLIP-FLOP PINS 31 2.5 SUMMARY OF KEY POINTS 34 3.
ARCHITECTING POWER 37 3.1 CLOCK CONTROL 38 3.1.1 CLOCK SKEW 39 3.1.2
MANAGING SKEW 40 VLL VIUE CONTENTS 3.2 INPUT CONTROL 42 3.3 REDUCING THE
VOLTAGE SUPPLY 44 3.4 DUAL-EDGE TRIGGERED FLIP-FLOPS 44 3.5 MODIFYING
TERMINATIONS 45 3.6 SUMMARY OF KEY POINTS 46 4. EXAMPLE DESIGN: THE
ADVANCED ENCRYPTION STANDARD 47 4.1 AES ARCHITECTURES 47 4.1.1 ONE STAGE
FOR SUB-BYTES 51 4.1.2 ZERO STAGES FOR SHIFT ROWS 51 4.1.3 TWO PIPELINE
STAGES FOR MIX-COLUMN 52 4.1.4 ONE STAGE FOR ADD ROUND KEY 52 4.1.5
COMPACT ARCHITECTURE 53 4.1.6 PARTIALLY PIPELINED ARCHITECTURE 57 4.1.7
FULLY PIPELINED ARCHITECTURE 60 4.2 PERFORMANCE VERSUS AREA 66 4.3 OTHER
OPTIMIZATIONS 67 5. HIGH-LEVEL DESIGN 69 5.1 ABSTRACT DESIGN TECHNIQUES
69 5.2 GRAPHICAL STATE MACHINES 70 5.3 DSP DESIGN 75 5.4
SOFTWARE/HARDWARE CODESIGN 80 5.5 SUMMARY OF KEY POINTS 81 6. CLOCK
DOMAINS 83 6.1 CROSSING CLOCK DOMAINS 84 6.1.1 METASTABILITY 86 6.1.2
SOLUTION 1: PHASE CONTROL 88 6.1.3 SOLUTION 2: DOUBLE FLOPPING 89 6.1.4
SOLUTION 3: FIFO STRUCTURE 92 6.1.5 PARTITIONING SYNCHRONIZER BLOCKS 97
6.2 GATED CLOCKS IN ASIC PROTOTYPES 97 6.2.1 CLOCKS MODULE 98 6.2.2
GATING REMOVAL 99 6.3 SUMMARY OF KEY POINTS 100 7. EXAMPLE DESIGN: I2S
VERSUS SPDIF 101 7.1 I2S 101 7.1.1 PROTOCOL 102 7.1.2 HARDWARE
ARCHITECTURE 102 CONTENTS IX 7.1.3 ANALYSIS 105 7.2 SPDIF 107 7.2.1
PROTOCOL 107 7.2.2 HARDWARE ARCHITECTURE 108 7.2.3 ANALYSIS 114 8.
IMPLEMENTING MATH FUNCTIONS 117 8.1 HARDWARE DIVISION 117 8.1.1 MULTIPLY
AND SHIFT 118 8.1.2 ITERATIVE DIVISION 119 8.1.3 THE GOLDSCHMIDT METHOD
120 8.2 TAYLOR AND MACLAURIN SERIES EXPANSION 122 8.3 THE CORDIC
ALGORITHM 124 8.4 SUMMARY OF KEY POINTS 126 9. EXAMPLE DESIGN:
FLOATING-POINT UNIT 127 9.1 FLOATING-POINT FORMATS 127 9.2 PIPELINED
ARCHITECTURE 128 9.2.1 VERILOG IMPLEMENTATION 131 9.2.2 RESOURCES AND
PERFORMANCE 137 10. RESET CIRCUITS 139 10.1 ASYNCHRONOUS VERSUS
SYNCHRONOUS 140 10.1.1 PROBLEMS WITH FULLY ASYNCHRONOUS RESETS 140
10.1.2 FULLY SYNCHRONIZED RESETS 142 10.1.3 ASYNCHRONOUS ASSERTION,
SYNCHRONOUS DEASSERTION 144 10.2 MIXING RESET TYPES 145 10.2.1
NONRESETABLE FLIP-FLOPS 145 10.2.2 INTERNALLY GENERATED RESETS 146 10.3
MULTIPLE CLOCK DOMAINS 148 10.4 SUMMARY OF KEY POINTS 149 11. ADVANCE D
SIMULATION 151 11.1 TESTBENCH ARCHITECTURE 152 11.1.1 TESTBENCH
COMPONENTS 152 11.1.2 TESTBENCH FLOW 153 11.1.2.1 MAINTHREAD 153
11.1.2.2 CLOCKS AND RESETS 154 11.1.2.3 TESTCASES 155 X CONTENTS 11.2
SYSTEM STIMULUS 157 11.2.1 MATLAB 157 11.2.2 BUS-FUNCTIONAL MODELS 158
11.3 CODECOVERAGE 159 11.4 GATE-LEVEL SIMULATIONS 159 11.5 TOGGLE
COVERAGE 162 11.6 RUN-TIME TRAPS 165 11.6.1 TIMESCALE 165 11.6.2 GLITCH
REJECTION 165 11.6.3 COMBMATORIAL DELAY MODELING 166 11.7 SUMMARY OF KEY
POINTS 169 12. CODING FOR SYNTHESIS 171 12.1 DECISION TREES 172 12.1.1
PRIORITY VERSUS PARALLEL 172 12.1.2 FUELL CONDITIONS 176 12.1.3 MULTIPLE
CONTROL BRANCHES 179 12.2 TRAPS 180 12.2.1 BLOCKING VERSUS NONBLOCKING
180 12.2.2 FOR-LOOPS 183 12.2.3 COMBMATORIAL LOOPS 185 12.2.4 INFERRED
LATCHES 187 12.3 DESIGN ORGANIZATION 188 12.3.1 PARTITIONING 188
12.3.1.1 DATA PATH VERSUS CONTROL 188 12.3.1.2 CLOCK AND RESET
STRUCTURES 189 12.3.1.3 MULTIPLE INSTANTIATIONS 190 12.3.2
PARAMETERIZATION 191 12.3.2.1 DEFINITIONS 191 12.3.2.2 PARAMETERS 192
12.3.2.3 PARAMETERS IN VERILOG-2001 194 12.4 SUMMARY OF KEY POINTS 195
13. EXAMPLE DESIGN: THE SECURE HASH ALGORITHM 197 13.1 SHA-1
ARCHITECTURE 197 13.2 IMPLEMENTATION RESULTS 204 14. SYNTHESIS
OPTIMIZATION 205 14.1 SPEED VERSUS AREA 206 14.2 RESOURCE SHARING 208
CONTENTS XI 14.3 PIPELINING, RETIMING, AND REGISTER BALANCING 211 14.3.1
THE EFFECT OF RESET ON REGISTER BALANCING 213 14.3.2 RESYNCHRONIZATION
REGISTERS 215 14.4 FSM COMPILATION 216 14.4.1 REMOVAL OF UNREACHABLE
STATES 219 14.5 BLACK BOXES 220 14.6 PHYSICAL SYNTHESIS 223 14.6.1
FORWARD ANNOTATION VERSUS BACK-ANNOTATION 224 14.6.2 GRAPH-BASED
PHYSICAL SYNTHESIS 225 14.7 SUMMARY OF KEY POINTS 226 15. FLOORPLANNING
229 15.1 DESIGN PARTITIONING 229 15.2 CRITICAL-PATH FLOORPLANNING 232
15.3 FLOORPLANNING DANGERS 233 15.4 OPTIMAL FLOORPLANNING 234 15.4.1
DATAPATH 234 15.4.2 HIGHFAN-OUT 234 15.4.3 DEVICE STRUCTURE 235 15.4.4
REUSABILITY 238 15.5 REDUCING POWER DISSIPATION 238 15.6 SUMMARY OF KEY
POINTS 240 16. PLACE AND ROUTE OPTIMIZATION 241 16.1 OPTIMAL CONSTRAINTS
241 16.2 RELATIONSHIP BETWEEN PLACEMENT AND ROUTING 244 16.3 LOGIC
REPLICATION 246 16.4 OPTIMIZATION ACROSS HIERARCHY 247 16.5 I/O
REGISTERS 248 16.6 PACK FACTOR 250 16.7 MAPPING LOGIC INTO RAM 251 16.8
REGISTER ORDERING 251 16.9 PLACEMENT SEED 252 16.10 GUIDED PLACE AND
ROUTE 254 16.11 SUMMARY OF KEY POINTS 254 17. EXAMPLE DESIGN:
MICROPROCESSOR 257 17.1 SRC ARCHITECTURE 257 17.2 SYNTHESIS
OPTIMIZATIONS 259 17.2.1 SPEED VERSUS AREA 260 XII CONTENTS 17.2.2
PIPELINING 261 17.2.3 PHYSICAL SYNTHESIS 262 17.3 FLOORPLAN
OPTIMIZATIONS 262 17.3.1 PARTITIONED FLOORPLAN 263 17.3.2 CRITICAL-PATH
FLOORPLAN: ABSTRACTION 1 264 17.3.3 CRITICAL-PATH FLOORPLAN: ABSTRACTION
2 265 18. STATIC TIMING ANALYSIS 269 18.1 STANDARD ANALYSIS 269 18.2
LATCHES 273 18.3 ASYNCHRONOUS CIRCUITS 276 18.3.1 COMBINATORIAL FEEDBACK
277 18.4 SUMMARY OF KEY POINTS 278 19. PCBISSUES 279 19.1 POWER SUPPLY
279 19.1.1 SUPPLY REQUIREMENTS 279 19.1.2 REGULATION 283 19.2 DECOUPLING
CAPACITORS 283 19.2.1 CONCEPT 283 19.2.2 CALCULATING VALUES 285 19.2.3
CAPACITOR PLACEMENT 286 19.3 SUMMARY OF KEY POINTS 288 APPENDIX A
APPENDIX B BIBLIOGRAPHY 289 303 319 INDEX 321
|
| adam_txt |
ADVANCED FPGA DESIGN ARCHITECTURE, IMPLEMENTATION, AND OPTIMIZATION
STEVE KILTS SPECTRUM DESIGN SOLUTIONS MINNEAPOLIS, MINNESOTA THE
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC., NEW YORK
WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION CONTENTS
PREFACE ACKNOWLEDGMENTS 1. ARCHITECTING SPEED XIII XV 1 .1 .2 .3 HIGH
THROUGHPUT 2 LOW LATENCY 4 TIMING 6 1.3.1 ADD REGISTER LAYERS I 1.3.2
PARALLEL STRUCTURES 8 1.3.3 FLATTEN LOGIC STRUCTURES 1.3.4 REGISTER
BALANCING 12 1.3.5 REORDER PATHS 14 1.4 SUMMARY OF KEY POINTS 16 2.
ARCHITECTING AREA 17 2.1 ROLLING UP THE PIPELINE 18 2.2 CONTROL-BASED
LOGIC REUSE 20 2.3 RESOURCE SHARING 23 2.4 IMPACT OF RESET ON AREA 25
2.4.1 RESOURCES WITHOUT RESET 25 2.4.2 RESOURCES WITHOUT SET 26 2.4.3
RESOURCES WITHOUT ASYNCHRONOUS RESET 27 2.4.4 RESETTING RAM 29 2.4.5
UTILIZING SET/RESET FLIP-FLOP PINS 31 2.5 SUMMARY OF KEY POINTS 34 3.
ARCHITECTING POWER 37 3.1 CLOCK CONTROL 38 3.1.1 CLOCK SKEW 39 3.1.2
MANAGING SKEW 40 VLL VIUE CONTENTS 3.2 INPUT CONTROL 42 3.3 REDUCING THE
VOLTAGE SUPPLY 44 3.4 DUAL-EDGE TRIGGERED FLIP-FLOPS 44 3.5 MODIFYING
TERMINATIONS 45 3.6 SUMMARY OF KEY POINTS 46 4. EXAMPLE DESIGN: THE
ADVANCED ENCRYPTION STANDARD 47 4.1 AES ARCHITECTURES 47 4.1.1 ONE STAGE
FOR SUB-BYTES 51 4.1.2 ZERO STAGES FOR SHIFT ROWS 51 4.1.3 TWO PIPELINE
STAGES FOR MIX-COLUMN 52 4.1.4 ONE STAGE FOR ADD ROUND KEY 52 4.1.5
COMPACT ARCHITECTURE 53 4.1.6 PARTIALLY PIPELINED ARCHITECTURE 57 4.1.7
FULLY PIPELINED ARCHITECTURE 60 4.2 PERFORMANCE VERSUS AREA 66 4.3 OTHER
OPTIMIZATIONS 67 5. HIGH-LEVEL DESIGN 69 5.1 ABSTRACT DESIGN TECHNIQUES
69 5.2 GRAPHICAL STATE MACHINES 70 5.3 DSP DESIGN 75 5.4
SOFTWARE/HARDWARE CODESIGN 80 5.5 SUMMARY OF KEY POINTS 81 6. CLOCK
DOMAINS 83 6.1 CROSSING CLOCK DOMAINS 84 6.1.1 METASTABILITY 86 6.1.2
SOLUTION 1: PHASE CONTROL 88 6.1.3 SOLUTION 2: DOUBLE FLOPPING 89 6.1.4
SOLUTION 3: FIFO STRUCTURE 92 6.1.5 PARTITIONING SYNCHRONIZER BLOCKS 97
6.2 GATED CLOCKS IN ASIC PROTOTYPES 97 6.2.1 CLOCKS MODULE 98 6.2.2
GATING REMOVAL 99 6.3 SUMMARY OF KEY POINTS 100 7. EXAMPLE DESIGN: I2S
VERSUS SPDIF 101 7.1 I2S 101 7.1.1 PROTOCOL 102 7.1.2 HARDWARE
ARCHITECTURE 102 CONTENTS IX 7.1.3 ANALYSIS 105 7.2 SPDIF 107 7.2.1
PROTOCOL 107 7.2.2 HARDWARE ARCHITECTURE 108 7.2.3 ANALYSIS 114 8.
IMPLEMENTING MATH FUNCTIONS 117 8.1 HARDWARE DIVISION 117 8.1.1 MULTIPLY
AND SHIFT 118 8.1.2 ITERATIVE DIVISION 119 8.1.3 THE GOLDSCHMIDT METHOD
120 8.2 TAYLOR AND MACLAURIN SERIES EXPANSION 122 8.3 THE CORDIC
ALGORITHM 124 8.4 SUMMARY OF KEY POINTS 126 9. EXAMPLE DESIGN:
FLOATING-POINT UNIT 127 9.1 FLOATING-POINT FORMATS 127 9.2 PIPELINED
ARCHITECTURE 128 9.2.1 VERILOG IMPLEMENTATION 131 9.2.2 RESOURCES AND
PERFORMANCE 137 10. RESET CIRCUITS 139 10.1 ASYNCHRONOUS VERSUS
SYNCHRONOUS 140 10.1.1 PROBLEMS WITH FULLY ASYNCHRONOUS RESETS 140
10.1.2 FULLY SYNCHRONIZED RESETS 142 10.1.3 ASYNCHRONOUS ASSERTION,
SYNCHRONOUS DEASSERTION 144 10.2 MIXING RESET TYPES 145 10.2.1
NONRESETABLE FLIP-FLOPS 145 10.2.2 INTERNALLY GENERATED RESETS 146 10.3
MULTIPLE CLOCK DOMAINS 148 10.4 SUMMARY OF KEY POINTS 149 11. ADVANCE D
SIMULATION 151 11.1 TESTBENCH ARCHITECTURE 152 11.1.1 TESTBENCH
COMPONENTS 152 11.1.2 TESTBENCH FLOW 153 11.1.2.1 MAINTHREAD 153
11.1.2.2 CLOCKS AND RESETS 154 11.1.2.3 TESTCASES 155 X CONTENTS 11.2
SYSTEM STIMULUS 157 11.2.1 MATLAB 157 11.2.2 BUS-FUNCTIONAL MODELS 158
11.3 CODECOVERAGE 159 11.4 GATE-LEVEL SIMULATIONS 159 11.5 TOGGLE
COVERAGE 162 11.6 RUN-TIME TRAPS 165 11.6.1 TIMESCALE 165 11.6.2 GLITCH
REJECTION 165 11.6.3 COMBMATORIAL DELAY MODELING 166 11.7 SUMMARY OF KEY
POINTS 169 12. CODING FOR SYNTHESIS 171 12.1 DECISION TREES 172 12.1.1
PRIORITY VERSUS PARALLEL 172 12.1.2 FUELL CONDITIONS 176 12.1.3 MULTIPLE
CONTROL BRANCHES 179 12.2 TRAPS 180 12.2.1 BLOCKING VERSUS NONBLOCKING
180 12.2.2 FOR-LOOPS 183 12.2.3 COMBMATORIAL LOOPS 185 12.2.4 INFERRED
LATCHES 187 12.3 DESIGN ORGANIZATION 188 12.3.1 PARTITIONING 188
12.3.1.1 DATA PATH VERSUS CONTROL 188 12.3.1.2 CLOCK AND RESET
STRUCTURES 189 12.3.1.3 MULTIPLE INSTANTIATIONS 190 12.3.2
PARAMETERIZATION 191 12.3.2.1 DEFINITIONS 191 12.3.2.2 PARAMETERS 192
12.3.2.3 PARAMETERS IN VERILOG-2001 194 12.4 SUMMARY OF KEY POINTS 195
13. EXAMPLE DESIGN: THE SECURE HASH ALGORITHM 197 13.1 SHA-1
ARCHITECTURE 197 13.2 IMPLEMENTATION RESULTS 204 14. SYNTHESIS
OPTIMIZATION 205 14.1 SPEED VERSUS AREA 206 14.2 RESOURCE SHARING 208
CONTENTS XI 14.3 PIPELINING, RETIMING, AND REGISTER BALANCING 211 14.3.1
THE EFFECT OF RESET ON REGISTER BALANCING 213 14.3.2 RESYNCHRONIZATION
REGISTERS 215 14.4 FSM COMPILATION 216 14.4.1 REMOVAL OF UNREACHABLE
STATES 219 14.5 BLACK BOXES 220 14.6 PHYSICAL SYNTHESIS 223 14.6.1
FORWARD ANNOTATION VERSUS BACK-ANNOTATION 224 14.6.2 GRAPH-BASED
PHYSICAL SYNTHESIS 225 14.7 SUMMARY OF KEY POINTS 226 15. FLOORPLANNING
229 15.1 DESIGN PARTITIONING 229 15.2 CRITICAL-PATH FLOORPLANNING 232
15.3 FLOORPLANNING DANGERS 233 15.4 OPTIMAL FLOORPLANNING 234 15.4.1
DATAPATH 234 15.4.2 HIGHFAN-OUT 234 15.4.3 DEVICE STRUCTURE 235 15.4.4
REUSABILITY 238 15.5 REDUCING POWER DISSIPATION 238 15.6 SUMMARY OF KEY
POINTS 240 16. PLACE AND ROUTE OPTIMIZATION 241 16.1 OPTIMAL CONSTRAINTS
241 16.2 RELATIONSHIP BETWEEN PLACEMENT AND ROUTING 244 16.3 LOGIC
REPLICATION 246 16.4 OPTIMIZATION ACROSS HIERARCHY 247 16.5 I/O
REGISTERS 248 16.6 PACK FACTOR 250 16.7 MAPPING LOGIC INTO RAM 251 16.8
REGISTER ORDERING 251 16.9 PLACEMENT SEED 252 16.10 GUIDED PLACE AND
ROUTE 254 16.11 SUMMARY OF KEY POINTS 254 17. EXAMPLE DESIGN:
MICROPROCESSOR 257 17.1 SRC ARCHITECTURE 257 17.2 SYNTHESIS
OPTIMIZATIONS 259 17.2.1 SPEED VERSUS AREA 260 XII CONTENTS 17.2.2
PIPELINING 261 17.2.3 PHYSICAL SYNTHESIS 262 17.3 FLOORPLAN
OPTIMIZATIONS 262 17.3.1 PARTITIONED FLOORPLAN 263 17.3.2 CRITICAL-PATH
FLOORPLAN: ABSTRACTION 1 264 17.3.3 CRITICAL-PATH FLOORPLAN: ABSTRACTION
2 265 18. STATIC TIMING ANALYSIS 269 18.1 STANDARD ANALYSIS 269 18.2
LATCHES 273 18.3 ASYNCHRONOUS CIRCUITS 276 18.3.1 COMBINATORIAL FEEDBACK
277 18.4 SUMMARY OF KEY POINTS 278 19. PCBISSUES 279 19.1 POWER SUPPLY
279 19.1.1 SUPPLY REQUIREMENTS 279 19.1.2 REGULATION 283 19.2 DECOUPLING
CAPACITORS 283 19.2.1 CONCEPT 283 19.2.2 CALCULATING VALUES 285 19.2.3
CAPACITOR PLACEMENT 286 19.3 SUMMARY OF KEY POINTS 288 APPENDIX A
APPENDIX B BIBLIOGRAPHY 289 303 319 INDEX 321 |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| author | Kilts, Steve |
| author_facet | Kilts, Steve |
| author_role | aut |
| author_sort | Kilts, Steve |
| author_variant | s k sk |
| building | Verbundindex |
| bvnumber | BV022780553 |
| callnumber-first | T - Technology |
| callnumber-label | TK7895 |
| callnumber-raw | TK7895.G36 |
| callnumber-search | TK7895.G36 |
| callnumber-sort | TK 47895 G36 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4904 ZN 4950 ZN 5630 |
| ctrlnum | (OCoLC)72799161 (DE-599)BVBBV022780553 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01922nam a2200457zc 4500</leader><controlfield tag="001">BV022780553</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20090408 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">070918s2007 xxud||| |||| 00||| eng d</controlfield><datafield tag="010" ind1=" " ind2=" "><subfield code="a">2006033573</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0470054379</subfield><subfield code="c">cloth</subfield><subfield code="9">0-470-05437-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470054376</subfield><subfield code="9">978-0-470-05437-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)72799161</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV022780553</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">US</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1043</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-858</subfield><subfield code="a">DE-703</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-859</subfield><subfield code="a">DE-29T</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-706</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7895.G36</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4904</subfield><subfield code="0">(DE-625)157419:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4950</subfield><subfield code="0">(DE-625)157424:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5630</subfield><subfield code="0">(DE-625)157471:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kilts, Steve</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Advanced FPGA design</subfield><subfield code="b">architecture, implementation and optimization</subfield><subfield code="c">Steve Kilts</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, N.J.</subfield><subfield code="b">Wiley</subfield><subfield code="c">2007</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XV, 336 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes index.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Field programmable gate arrays</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/toc/ecip072/2006033573.html</subfield><subfield code="3">Table of contents only</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0739/2006033573-b.html</subfield><subfield code="3">Contributor biographical information</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0739/2006033573-d.html</subfield><subfield code="3">Publisher description</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015986065&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-015986065</subfield></datafield></record></collection> |
| id | DE-604.BV022780553 |
| illustrated | Illustrated |
| index_date | 2024-07-02T18:36:06Z |
| indexdate | 2024-07-09T21:06:00Z |
| institution | BVB |
| isbn | 0470054379 9780470054376 |
| language | English |
| lccn | 2006033573 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015986065 |
| oclc_num | 72799161 |
| open_access_boolean | |
| owner | DE-1043 DE-898 DE-BY-UBR DE-858 DE-703 DE-634 DE-859 DE-29T DE-83 DE-706 |
| owner_facet | DE-1043 DE-898 DE-BY-UBR DE-858 DE-703 DE-634 DE-859 DE-29T DE-83 DE-706 |
| physical | XV, 336 S. graph. Darst. |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | Wiley |
| record_format | marc |
| spelling | Kilts, Steve Verfasser aut Advanced FPGA design architecture, implementation and optimization Steve Kilts Hoboken, N.J. Wiley 2007 XV, 336 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes index. Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s DE-604 http://www.loc.gov/catdir/toc/ecip072/2006033573.html Table of contents only http://www.loc.gov/catdir/enhancements/fy0739/2006033573-b.html Contributor biographical information http://www.loc.gov/catdir/enhancements/fy0739/2006033573-d.html Publisher description GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015986065&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Kilts, Steve Advanced FPGA design architecture, implementation and optimization Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4347749-5 |
| title | Advanced FPGA design architecture, implementation and optimization |
| title_auth | Advanced FPGA design architecture, implementation and optimization |
| title_exact_search | Advanced FPGA design architecture, implementation and optimization |
| title_exact_search_txtP | Advanced FPGA design architecture, implementation and optimization |
| title_full | Advanced FPGA design architecture, implementation and optimization Steve Kilts |
| title_fullStr | Advanced FPGA design architecture, implementation and optimization Steve Kilts |
| title_full_unstemmed | Advanced FPGA design architecture, implementation and optimization Steve Kilts |
| title_short | Advanced FPGA design |
| title_sort | advanced fpga design architecture implementation and optimization |
| title_sub | architecture, implementation and optimization |
| topic | Field programmable gate arrays Design and construction Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | Field programmable gate arrays Design and construction Field programmable gate array |
| url | http://www.loc.gov/catdir/toc/ecip072/2006033573.html http://www.loc.gov/catdir/enhancements/fy0739/2006033573-b.html http://www.loc.gov/catdir/enhancements/fy0739/2006033573-d.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015986065&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT kiltssteve advancedfpgadesignarchitectureimplementationandoptimization |