A task level programmable processor:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Duisburg
WiKu-Verl.
2006
|
| Schlagworte: | |
| Online-Zugang: | A task level programmable processor Inhaltsverzeichnis |
| Beschreibung: | XI, 127 S. graph. Darst. 210 mm x 138 mm |
| ISBN: | 9783865531704 3865531709 |
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Datensatz im Suchindex
| _version_ | 1804137005118914560 |
|---|---|
| adam_text | Contents
List of Figures vi
List of Tables viii
List of Listings ix
1 Introduction 1
1.1 Low Power Parameters 2
1.2 Data level Parallelism 3
1.3 Instruction level Parallelism 4
1.4 Task level Parallelism 5
1.5 Application Domain: Video G
1.6 Contributions of this thesis 7
1.7 Thesis Overview 8
2 Background 9
2.1 Processor Architecture Evolution 9
2.1.1 ISA 10
2.1.2 Pipelining 12
2.1.3 Parallelism 15
2.1.4 Dependeneies 18
2.2 Memory Allocation 19
2.3 Related Work 20
2.3.1 Stream Processors 21
2.3.2 Media Processing Engines 23
2.4 Motivation for a new DSP Architecture 24
3 Streamlined Compute Modules 26
3.1 Overview 26
3.2 Levels of Parallelism 28
3.3 Pipelining 30
3.4 Explicit Bypass Network Control 31
3.5 Power Saving 33
3.6 Summary 34
4 8BFT: Processor Architecture 35
4.1 Hardware 35
4.1.1 Requirements 36
4.1.2 Architecture Overview 40
4.1.3 Building Blocks 42
4.1.4 Summary 51
4.2 Programming Model 51
4.2.1 Task level Programming Single Issue 54
4.2.2 Task level Programming Multiple Issues 64
4.3 Real Time Scheduling Engine 78
4.3.1 Levels of Parallelism 78
4.3.2 Task Issuing Pipeline 83
4.3.3 Summary 84
5 Results 86
5.1 Power and Area 86
5.1.1 OFDM DSP 87
5.1.2 SAMIRA DSP 88
5.1.3 Fixed Point 93
5.2 8BFT: Processor Architecture 98
5.2.1 Speed up 99
5.3 Putting It Together 103
6 Summary 110
Bibliography 112
A Appendix 121
A.l Moving JPEG 121
A.2 Pipelined Task Execution 122
A.3 Design Flow 125
List of Figures
1.1 H.264 decoder 6
2.1 MOS6502 architecture 14
2.2 MIPS pipeline 14
2.3 Instruction issuing algorithm 17
2.4 RAW,WAR and WAW data dependencies 18
3.1 Compute module design template 28
3.2 RISC like datapath using design template 29
3.3 Simple RISC datapath 32
4.1 Example for parallel execution of multiple macroblocks ... 39
4.2 8BFT processor architecture 41
4.3 Compute module 44
4.4 Task description packet 45
4.5 Communication resource 46
4.6 Block diagram of a DDR SDRAM 48
4.7 DDR2 SDRAM Timing diagram 49
4.8 Simplified model of the processor hardware 52
4.9 Tasks mapped on the 8BFT 53
4.10 Simple FFT execution 55
4.11 FFT execution on the 8BFT processor 55
4.12 Unpipelined execution of tasks 57
4.14 Tree representation of simple video pipeline 58
4.13 Simple video pipeline 58
4.15 Overview of the Real Time Scheduling Engine 77
4.16 Two sets of three data dependent tasks 79
4.17 Acyclic directed dependency graph of tasks 81
5.1 OFDM DSP: Block diagram 87
5.2 OFDM DSP: Layout 88
5.3 SAMIRA DSP: GDSII plot 89
5.4 SAMIRA DSP: packaged in a PQFP120 89
5.5 SAMIRA DSP: Block diagram 90
5.6 SAMIRA DSP: Area consumption pie diagram 96
5.7 SAMIRA DSP: Power consumption pie diagram 96
5.8 SAMIRA DSP (fixed point, 4 way): Area consumption pie
diagram 97
5.9 SAMIRA DSP (fixed point, 4 way): Power consumption pie
diagram 97
5.10 Run time scheduler Simulation (1) 104
5.11 Run time scheduler Simulation (2) 105
5.12 Run time scheduler Simulation (3) 106
5.13 Run time scheduler Simulation (4) 107
5.14 H.264 decoder Simulation (1) 108
5.15 H.264 decoder Simulation (2) 109
A.l block diagram of moving jpeg decoder 121
A.2 Design Flow for the 8BFT processor 127
List of Tables
4.1 A pipelined implementation of the task tree 60
4.2 A pipelined implementation of the task tree using bypassing 61
4.3 Data dependencies of memory blocks (1) 65
4.4 Data dependencies of memory blocks (2) 66
4.5 Linked lists stored in the memory 73
5.1 Samira DSP: Description of Functional Units 91
5.2 SAMIRA DSP: area and power consumption 92
5.3 SAMIRA DSP (floating point, 4 way): Area and Power . . 95
5.4 SAMIRA DSP (fixed point, 4 way): Area and Power .... 98
List of Listings
2.1 KernelC example 22
4.1 Small assembly program 56
4.2 Example for data dependencies between meinory Blocks ... 75
4.3 Example for data dependencies between meinory blocks, 8BFT
implementation 76
4.4 Control code for a task set 82
5.1 Run time scheduler Simulation (1) 100
5.2 Run time scheduler Simulation (2) 102
5.3 Run time scheduler Simulation (3) 102
|
| adam_txt |
Contents
List of Figures vi
List of Tables viii
List of Listings ix
1 Introduction 1
1.1 Low Power Parameters 2
1.2 Data level Parallelism 3
1.3 Instruction level Parallelism 4
1.4 Task level Parallelism 5
1.5 Application Domain: Video G
1.6 Contributions of this thesis 7
1.7 Thesis Overview 8
2 Background 9
2.1 Processor Architecture Evolution 9
2.1.1 ISA 10
2.1.2 Pipelining 12
2.1.3 Parallelism 15
2.1.4 Dependeneies 18
2.2 Memory Allocation 19
2.3 Related Work 20
2.3.1 Stream Processors 21
2.3.2 Media Processing Engines 23
2.4 Motivation for a new DSP Architecture 24
3 Streamlined Compute Modules 26
3.1 Overview 26
3.2 Levels of Parallelism 28
3.3 Pipelining 30
3.4 Explicit Bypass Network Control 31
3.5 Power Saving 33
3.6 Summary 34
4 8BFT: Processor Architecture 35
4.1 Hardware 35
4.1.1 Requirements 36
4.1.2 Architecture Overview 40
4.1.3 Building Blocks 42
4.1.4 Summary 51
4.2 Programming Model 51
4.2.1 Task level Programming Single Issue 54
4.2.2 Task level Programming Multiple Issues 64
4.3 Real Time Scheduling Engine 78
4.3.1 Levels of Parallelism 78
4.3.2 Task Issuing Pipeline 83
4.3.3 Summary 84
5 Results 86
5.1 Power and Area 86
5.1.1 OFDM DSP 87
5.1.2 SAMIRA DSP 88
5.1.3 Fixed Point 93
5.2 8BFT: Processor Architecture 98
5.2.1 Speed up 99
5.3 Putting It Together 103
6 Summary 110
Bibliography 112
A Appendix 121
A.l Moving JPEG 121
A.2 Pipelined Task Execution 122
A.3 Design Flow 125
List of Figures
1.1 H.264 decoder 6
2.1 MOS6502 architecture 14
2.2 MIPS pipeline 14
2.3 Instruction issuing algorithm 17
2.4 RAW,WAR and WAW data dependencies 18
3.1 Compute module design template 28
3.2 RISC like datapath using design template 29
3.3 Simple RISC datapath 32
4.1 Example for parallel execution of multiple macroblocks . 39
4.2 8BFT processor architecture 41
4.3 Compute module 44
4.4 Task description packet 45
4.5 Communication resource 46
4.6 Block diagram of a DDR SDRAM 48
4.7 DDR2 SDRAM Timing diagram 49
4.8 Simplified model of the processor hardware 52
4.9 Tasks mapped on the 8BFT 53
4.10 Simple FFT execution 55
4.11 FFT execution on the 8BFT processor 55
4.12 Unpipelined execution of tasks 57
4.14 Tree representation of simple video pipeline 58
4.13 Simple video pipeline 58
4.15 Overview of the Real Time Scheduling Engine 77
4.16 Two sets of three data dependent tasks 79
4.17 Acyclic directed dependency graph of tasks 81
5.1 OFDM DSP: Block diagram 87
5.2 OFDM DSP: Layout 88
5.3 SAMIRA DSP: GDSII plot 89
5.4 SAMIRA DSP: packaged in a PQFP120 89
5.5 SAMIRA DSP: Block diagram 90
5.6 SAMIRA DSP: Area consumption pie diagram 96
5.7 SAMIRA DSP: Power consumption pie diagram 96
5.8 SAMIRA DSP (fixed point, 4 way): Area consumption pie
diagram 97
5.9 SAMIRA DSP (fixed point, 4 way): Power consumption pie
diagram 97
5.10 Run time scheduler Simulation (1) 104
5.11 Run time scheduler Simulation (2) 105
5.12 Run time scheduler Simulation (3) 106
5.13 Run time scheduler Simulation (4) 107
5.14 H.264 decoder Simulation (1) 108
5.15 H.264 decoder Simulation (2) 109
A.l block diagram of moving jpeg decoder 121
A.2 Design Flow for the 8BFT processor 127
List of Tables
4.1 A pipelined implementation of the task tree 60
4.2 A pipelined implementation of the task tree using bypassing 61
4.3 Data dependencies of memory blocks (1) 65
4.4 Data dependencies of memory blocks (2) 66
4.5 Linked lists stored in the memory 73
5.1 Samira DSP: Description of Functional Units 91
5.2 SAMIRA DSP: area and power consumption 92
5.3 SAMIRA DSP (floating point, 4 way): Area and Power . . 95
5.4 SAMIRA DSP (fixed point, 4 way): Area and Power . 98
List of Listings
2.1 KernelC example 22
4.1 Small assembly program 56
4.2 Example for data dependencies between meinory Blocks . 75
4.3 Example for data dependencies between meinory blocks, 8BFT
implementation 76
4.4 Control code for a task set 82
5.1 Run time scheduler Simulation (1) 100
5.2 Run time scheduler Simulation (2) 102
5.3 Run time scheduler Simulation (3) 102 |
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| author | Seidel, Hendrik |
| author_GND | (DE-588)132363445 |
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| bvnumber | BV022757491 |
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| dewey-full | 621.392028543 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.392028543 |
| dewey-search | 621.392028543 |
| dewey-sort | 3621.392028543 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Thesis Book |
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| id | DE-604.BV022757491 |
| illustrated | Illustrated |
| index_date | 2024-07-02T18:33:04Z |
| indexdate | 2024-07-09T21:05:25Z |
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| isbn | 9783865531704 3865531709 |
| language | English |
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| physical | XI, 127 S. graph. Darst. 210 mm x 138 mm |
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| spelling | Seidel, Hendrik Verfasser (DE-588)132363445 aut A task level programmable processor Hendrik Seidel task-level programmable processor Duisburg WiKu-Verl. 2006 XI, 127 S. graph. Darst. 210 mm x 138 mm txt rdacontent n rdamedia nc rdacarrier Dresden, Techn. Univ., Diss., 2006 Task (DE-588)4135913-6 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 gnd rswk-swf Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf Programmierung (DE-588)4076370-5 gnd rswk-swf HDTV (DE-588)4191818-6 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Computerarchitektur (DE-588)4048717-9 s Mikroprozessor (DE-588)4039232-6 s Task (DE-588)4135913-6 s Programmierung (DE-588)4076370-5 s Mehrprozessorsystem (DE-588)4038397-0 s HDTV (DE-588)4191818-6 s DE-604 http://digitool.hbz-nrw.de:1801/webclient/DeliveryManager?pid=1770186&custom_att_2=simple_viewer A task level programmable processor Inhaltsverzeichnis HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015963125&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Seidel, Hendrik A task level programmable processor Task (DE-588)4135913-6 gnd Mikroprozessor (DE-588)4039232-6 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd Programmierung (DE-588)4076370-5 gnd HDTV (DE-588)4191818-6 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| subject_GND | (DE-588)4135913-6 (DE-588)4039232-6 (DE-588)4038397-0 (DE-588)4076370-5 (DE-588)4191818-6 (DE-588)4048717-9 (DE-588)4113937-9 |
| title | A task level programmable processor |
| title_alt | task-level programmable processor |
| title_auth | A task level programmable processor |
| title_exact_search | A task level programmable processor |
| title_exact_search_txtP | A task level programmable processor |
| title_full | A task level programmable processor Hendrik Seidel |
| title_fullStr | A task level programmable processor Hendrik Seidel |
| title_full_unstemmed | A task level programmable processor Hendrik Seidel |
| title_short | A task level programmable processor |
| title_sort | a task level programmable processor |
| topic | Task (DE-588)4135913-6 gnd Mikroprozessor (DE-588)4039232-6 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd Programmierung (DE-588)4076370-5 gnd HDTV (DE-588)4191818-6 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Task Mikroprozessor Mehrprozessorsystem Programmierung HDTV Computerarchitektur Hochschulschrift |
| url | http://digitool.hbz-nrw.de:1801/webclient/DeliveryManager?pid=1770186&custom_att_2=simple_viewer http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015963125&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT seidelhendrik atasklevelprogrammableprocessor AT seidelhendrik tasklevelprogrammableprocessor |