Verfügbarkeit: Principles of modern digital design

Principles of modern digital design:

http://www.loc.gov/catdir/enhancements/fy0741/2006032483-d.html.

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Bibliographische Detailangaben
1. Verfasser:	Lala, Parag K. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Hoboken, NJ Wiley 2007
Schlagworte:	Logic design Logic circuits > Design and construction Digital electronics Logischer Entwurf
Online-Zugang:	Inhaltsverzeichnis
Zusammenfassung:	http://www.loc.gov/catdir/enhancements/fy0741/2006032483-d.html.
Beschreibung:	XV, 419 S. zahlr. graph. Darst. 1 CD-ROM (12 cm)
ISBN:	9780470072967 0470072962

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Datensatz im Suchindex

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adam_text	IMAGE 1 PREFACE P. XIII NUMBER SYSTEMS AND BINARY CODES P. 1 INTRODUCTION P. 1 DECIMAL NUMBERS P. 1 BINARY NUMBERS P. 2 BASIC BINARY ARITHMETIC P. 5 OCTAL NUMBERS P. 8 HEXADECIMAL NUMBERS P. 11 SIGNED NUMBERS P. 13 DIMINISHED RADIX COMPLEMENT P. 14 RADIX COMPLEMENT P. 16 FLOATING-POINT NUMBERS P. 19 BINARY ENCODING P. 20 WEIGHTED CODES P. 20 NONWEIGHTED CODES P. 22 EXERCISES P. 25 FUNDAMENTAL CONCEPTS OF DIGITAL LOGIC P. 29 INTRODUCTION P. 29 SETS P. 29 RELATIONS P. 32 PARTITIONS P. 34 GRAPHS P. 35 BOOLEAN ALGEBRA P. 37 BOOLEAN FUNCTIONS P. 41 DERIVATION AND CLASSIFICATION OF BOOLEAN FUNCTIONS P. 43 CANONICAL FORMS OF BOOLEAN FUNCTIONS P. 45 LOGIC GATES P. 48 EXERCISES P. 53 COMBINATIONAL LOGIC DESIGN P. 59 INTRODUCTION P. 59 MINIMIZATION OF BOOLEAN EXPRESSIONS P. 60 KARNAUGH MAPS P. 63 DON T CARE CONDITIONS P. 68 THE COMPLEMENTARY APPROACH P. 70 QUINE-MCCLUSKEY METHOD P. 73 SIMPLIFICATION OF BOOLEAN FUNCTION WITH DON T CARES P. 78 CUBICAL REPRESENTATION OF BOOLEAN FUNCTIONS P. 79 TAUTOLOGY P. 82 COMPLEMENTATION USING SHANNON S EXPANSION P. 84 HEURISTIC MINIMIZATION OF LOGIC CIRCUITS P. 85 EXPAND P. 85 IMAGE 2 REDUCE P. 88 IRREDUNDANT P. 90 ESPRESSO P. 92 MINIMIZATION OF MULTIPLE-OUTPUT FUNCTIONS P. 95 NAND-NAND AND NOR-NOR LOGIC P. 98 NAND-NAND LOGIC P. 98 NOR-NOR LOGIC P. 101 MULTILEVEL LOGIC DESIGN P. 102 ALGEBRAIC AND BOOLEAN DIVISION P. 105 KERNELS P. 106 MINIMIZATION OF MULTILEVEL CIRCUITS USING DON T CARES P. 109 SATISFIABILITY DON T CARES P. 110 OBSERVABILITY DON T CARES P. 112 COMBINATIONAL LOGIC IMPLEMENTATION USING EX-OR AND AND GATES P. 114 LOGIC CIRCUIT DESIGN USING MULTIPLEXERS AND DECODERS P. 117 MULTIPLEXERS P. 117 DEMULTIPLEXERS AND DECODERS P. 123 ARITHMETIC CIRCUITS P. 125 HALF-ADDERS P. 125 FULL ADDERS P. 126 CARRY-LOOKAHEAD ADDERS P. 129 CARRY-SELECT ADDER P. 130 CARRY-SAVE ADDITION P. 130 BCD ADDERS P. 132 HALF-SUBTRACTORS P. 133 FULL SUBTRACTORS P. 135 TWO S COMPLEMENT SUBTRACTORS P. 135 BCD SUBSTRACTORS P. 137 MULTIPLICATION P. 138 COMPARATOR P. 140 COMBINATIONAL CIRCUIT DESIGN USING PLDS P. 141 PROM P. 142 PLA P. 144 PAL P. 146 EXERCISES P. 150 REFERENCES P. 155 FUNDAMENTALS OF SYNCHRONOUS SEQUENTIAL CIRCUITS P. 157 INTRODUCTION P. 157 SYNCHRONOUS AND ASYNCHRONOUS OPERATION P. 158 LATCHES P. 159 FLIP-FLOPS P. 162 IMAGE 3 D FLIP-FLOP P. 163 JK FLIP-FLOP P. 165 T FLIP-FLOP P. 167 TIMING IN SYNCHRONOUS SEQUENTIAL CIRCUITS P. 168 STATE TABLES AND STATE DIAGRAMS P. 170 MEALY AND MOORE MODELS P. 172 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS P. 175 EXERCISES P. 177 REFERENCES P. 180 VHDL IN DIGITAL DESIGN P. 181 INTRODUCTION P. 181 ENTITY AND ARCHITECTURE P. 182 ENTITY P. 182 ARCHITECTURE P. 184 LEXICAL ELEMENTS IN VHDL P. 185 DATA TYPES P. 187 OPERATORS P. 189 CONCURRENT AND SEQUENTIAL STATEMENTS P. 192 ARCHITECTURE DESCRIPTION P. 194 STRUCTURAL DESCRIPTION P. 196 BEHAVIORAL DESCRIPTION P. 199 RTL DESCRIPTION P. 200 EXERCISES P. 202 COMBINATIONAL LOGIC DESIGN USING VHDL P. 205 INTRODUCTION P. 205 CONCURRENT ASSIGNMENT STATEMENTS P. 206 DIRECT SIGNAL ASSIGNMENT P. 206 CONDITIONAL SIGNAL ASSIGNMENT P. 207 SELECTED CONDITIONAL SIGNAL ASSIGNMENT P. 211 SEQUENTIAL ASSIGNMENT STATEMENTS P. 214 PROCESS P. 214 IF-THEN STATEMENT P. 216 CASE STATEMENT P. 220 IF VERSUS CASE STATEMENTS P. 223 LOOPS P. 225 FOR LOOP P. 225 WHILE LOOP P. 229 FOR-GENERATE STATEMENT P. 230 EXERCISES P. 233 SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN P. 235 INTRODUCTION P. 235 IMAGE 4 PROBLEM SPECIFICATION P. 236 STATE MINIMIZATION P. 239 PARTITIONING APPROACH P. 239 IMPLICATION TABLE P. 242 MINIMIZATION OF INCOMPLETELY SPECIFIED SEQUENTIAL CIRCUITS P. 244 DERIVATION OF FLIP-FLOP NEXT STATE EXPRESSIONS P. 249 STATE ASSIGNMENT P. 257 STATE ASSIGNMENT BASED ON DECOMPOSITION P. 261 FAN-OUT AND FAN-IN ORIENTED STATE ASSIGNMENT TECHNIQUES P. 265 STATE ASSIGNMENT BASED ON 1-HOT CODE P. 271 STATE ASSIGNMENT USING M-OUT-OF-N CODE P. 271 SEQUENTIAL PAL DEVICES P. 273 EXERCISES P. 286 REFERENCES P. 290 COUNTER DESIGN P. 291 INTRODUCTION P. 291 RIPPLE (ASYNCHRONOUS) COUNTERS P. 291 ASYNCHRONOUS UP-DOWN COUNTERS P. 294 SYNCHRONOUS COUNTERS P. 295 GRAY CODE COUNTERS P. 300 SHIFT REGISTER COUNTERS P. 302 RING COUNTERS P. 307 JOHNSON COUNTERS P. 310 EXERCISES P. 313 REFERENCES P. 313 SEQUENTIAL CIRCUIT DESIGN USING VHDL P. 315 INTRODUCTION P. 315 D LATCH P. 315 FLIP-FLOPS AND REGISTERS P. 316 D FLIP-FLOP P. 316 T AND JK FLIP-FLOPS P. 318 SYNCHRONOUS AND ASYNCHRONOUS RESET P. 320 SYNCHRONOUS AND ASYNCHRONOUS PRESET P. 322 REGISTERS P. 322 SHIFT REGISTERS P. 324 BIDIRECTIONAL SHIFT REGISTER P. 326 UNIVERSAL SHIFT REGISTER P. 327 BARREL SHIFTER P. 327 LINEAR FEEDBACK SHIFT REGISTERS P. 329 COUNTERS P. 332 DECADE COUNTER P. 334 IMAGE 5 GRAY CODE COUNTER P. 335 RING COUNTER P. 336 JOHNSON COUNTER P. 337 STATE MACHINES P. 338 MOORE-TYPE STATE MACHINES P. 338 MEALY-TYPE STATE MACHINES P. 341 VHDL CODES FOR STATE MACHINES USING ENUMERATED TYPES P. 342 MEALY MACHINE IN VHDL P. 345 USER-DEFINED STATE ENCODING P. 351 1-HOT ENCODING P. 355 CASE STUDIES P. 356 EXERCISES P. 368 REFERENCES P. 371 ASYNCHRONOUS SEQUENTIAL CIRCUITS P. 373 INTRODUCTION P. 373 FLOW TABLE P. 374 REDUCTION OF PRIMITIVE HOW TABLES P. 377 STATE ASSIGNMENT P. 379 RACES AND CYCLES P. 379 CRITICAL RACE-FREE STATE ASSIGNMENT P. 381 EXCITATION AND OUTPUT FUNCTIONS P. 387 HAZARDS P. 390 FUNCTION HAZARDS P. 391 LOGIC HAZARDS P. 393 ESSENTIAL HAZARDS P. 396 EXERCISES P. 398 REFERENCES P. 401 CMOS LOGIC P. 403 TRANSMISSION GATES P. 405 CLOCKED CMOS CIRCUITS P. 407 CMOS DOMINO LOGIC P. 408 INDEX P. 411 TABLE OF CONTENTS PROVIDED BY BLACKWELL S BOOK SERVICES AND R.R. BOWKER. USED WITH PERMISSION.
adam_txt	IMAGE 1 PREFACE P. XIII NUMBER SYSTEMS AND BINARY CODES P. 1 INTRODUCTION P. 1 DECIMAL NUMBERS P. 1 BINARY NUMBERS P. 2 BASIC BINARY ARITHMETIC P. 5 OCTAL NUMBERS P. 8 HEXADECIMAL NUMBERS P. 11 SIGNED NUMBERS P. 13 DIMINISHED RADIX COMPLEMENT P. 14 RADIX COMPLEMENT P. 16 FLOATING-POINT NUMBERS P. 19 BINARY ENCODING P. 20 WEIGHTED CODES P. 20 NONWEIGHTED CODES P. 22 EXERCISES P. 25 FUNDAMENTAL CONCEPTS OF DIGITAL LOGIC P. 29 INTRODUCTION P. 29 SETS P. 29 RELATIONS P. 32 PARTITIONS P. 34 GRAPHS P. 35 BOOLEAN ALGEBRA P. 37 BOOLEAN FUNCTIONS P. 41 DERIVATION AND CLASSIFICATION OF BOOLEAN FUNCTIONS P. 43 CANONICAL FORMS OF BOOLEAN FUNCTIONS P. 45 LOGIC GATES P. 48 EXERCISES P. 53 COMBINATIONAL LOGIC DESIGN P. 59 INTRODUCTION P. 59 MINIMIZATION OF BOOLEAN EXPRESSIONS P. 60 KARNAUGH MAPS P. 63 DON'T CARE CONDITIONS P. 68 THE COMPLEMENTARY APPROACH P. 70 QUINE-MCCLUSKEY METHOD P. 73 SIMPLIFICATION OF BOOLEAN FUNCTION WITH DON'T CARES P. 78 CUBICAL REPRESENTATION OF BOOLEAN FUNCTIONS P. 79 TAUTOLOGY P. 82 COMPLEMENTATION USING SHANNON'S EXPANSION P. 84 HEURISTIC MINIMIZATION OF LOGIC CIRCUITS P. 85 EXPAND P. 85 IMAGE 2 REDUCE P. 88 IRREDUNDANT P. 90 ESPRESSO P. 92 MINIMIZATION OF MULTIPLE-OUTPUT FUNCTIONS P. 95 NAND-NAND AND NOR-NOR LOGIC P. 98 NAND-NAND LOGIC P. 98 NOR-NOR LOGIC P. 101 MULTILEVEL LOGIC DESIGN P. 102 ALGEBRAIC AND BOOLEAN DIVISION P. 105 KERNELS P. 106 MINIMIZATION OF MULTILEVEL CIRCUITS USING DON'T CARES P. 109 SATISFIABILITY DON'T CARES P. 110 OBSERVABILITY DON'T CARES P. 112 COMBINATIONAL LOGIC IMPLEMENTATION USING EX-OR AND AND GATES P. 114 LOGIC CIRCUIT DESIGN USING MULTIPLEXERS AND DECODERS P. 117 MULTIPLEXERS P. 117 DEMULTIPLEXERS AND DECODERS P. 123 ARITHMETIC CIRCUITS P. 125 HALF-ADDERS P. 125 FULL ADDERS P. 126 CARRY-LOOKAHEAD ADDERS P. 129 CARRY-SELECT ADDER P. 130 CARRY-SAVE ADDITION P. 130 BCD ADDERS P. 132 HALF-SUBTRACTORS P. 133 FULL SUBTRACTORS P. 135 TWO'S COMPLEMENT SUBTRACTORS P. 135 BCD SUBSTRACTORS P. 137 MULTIPLICATION P. 138 COMPARATOR P. 140 COMBINATIONAL CIRCUIT DESIGN USING PLDS P. 141 PROM P. 142 PLA P. 144 PAL P. 146 EXERCISES P. 150 REFERENCES P. 155 FUNDAMENTALS OF SYNCHRONOUS SEQUENTIAL CIRCUITS P. 157 INTRODUCTION P. 157 SYNCHRONOUS AND ASYNCHRONOUS OPERATION P. 158 LATCHES P. 159 FLIP-FLOPS P. 162 IMAGE 3 D FLIP-FLOP P. 163 JK FLIP-FLOP P. 165 T FLIP-FLOP P. 167 TIMING IN SYNCHRONOUS SEQUENTIAL CIRCUITS P. 168 STATE TABLES AND STATE DIAGRAMS P. 170 MEALY AND MOORE MODELS P. 172 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS P. 175 EXERCISES P. 177 REFERENCES P. 180 VHDL IN DIGITAL DESIGN P. 181 INTRODUCTION P. 181 ENTITY AND ARCHITECTURE P. 182 ENTITY P. 182 ARCHITECTURE P. 184 LEXICAL ELEMENTS IN VHDL P. 185 DATA TYPES P. 187 OPERATORS P. 189 CONCURRENT AND SEQUENTIAL STATEMENTS P. 192 ARCHITECTURE DESCRIPTION P. 194 STRUCTURAL DESCRIPTION P. 196 BEHAVIORAL DESCRIPTION P. 199 RTL DESCRIPTION P. 200 EXERCISES P. 202 COMBINATIONAL LOGIC DESIGN USING VHDL P. 205 INTRODUCTION P. 205 CONCURRENT ASSIGNMENT STATEMENTS P. 206 DIRECT SIGNAL ASSIGNMENT P. 206 CONDITIONAL SIGNAL ASSIGNMENT P. 207 SELECTED CONDITIONAL SIGNAL ASSIGNMENT P. 211 SEQUENTIAL ASSIGNMENT STATEMENTS P. 214 PROCESS P. 214 IF-THEN STATEMENT P. 216 CASE STATEMENT P. 220 IF VERSUS CASE STATEMENTS P. 223 LOOPS P. 225 FOR LOOP P. 225 WHILE LOOP P. 229 FOR-GENERATE STATEMENT P. 230 EXERCISES P. 233 SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN P. 235 INTRODUCTION P. 235 IMAGE 4 PROBLEM SPECIFICATION P. 236 STATE MINIMIZATION P. 239 PARTITIONING APPROACH P. 239 IMPLICATION TABLE P. 242 MINIMIZATION OF INCOMPLETELY SPECIFIED SEQUENTIAL CIRCUITS P. 244 DERIVATION OF FLIP-FLOP NEXT STATE EXPRESSIONS P. 249 STATE ASSIGNMENT P. 257 STATE ASSIGNMENT BASED ON DECOMPOSITION P. 261 FAN-OUT AND FAN-IN ORIENTED STATE ASSIGNMENT TECHNIQUES P. 265 STATE ASSIGNMENT BASED ON 1-HOT CODE P. 271 STATE ASSIGNMENT USING M-OUT-OF-N CODE P. 271 SEQUENTIAL PAL DEVICES P. 273 EXERCISES P. 286 REFERENCES P. 290 COUNTER DESIGN P. 291 INTRODUCTION P. 291 RIPPLE (ASYNCHRONOUS) COUNTERS P. 291 ASYNCHRONOUS UP-DOWN COUNTERS P. 294 SYNCHRONOUS COUNTERS P. 295 GRAY CODE COUNTERS P. 300 SHIFT REGISTER COUNTERS P. 302 RING COUNTERS P. 307 JOHNSON COUNTERS P. 310 EXERCISES P. 313 REFERENCES P. 313 SEQUENTIAL CIRCUIT DESIGN USING VHDL P. 315 INTRODUCTION P. 315 D LATCH P. 315 FLIP-FLOPS AND REGISTERS P. 316 D FLIP-FLOP P. 316 T AND JK FLIP-FLOPS P. 318 SYNCHRONOUS AND ASYNCHRONOUS RESET P. 320 SYNCHRONOUS AND ASYNCHRONOUS PRESET P. 322 REGISTERS P. 322 SHIFT REGISTERS P. 324 BIDIRECTIONAL SHIFT REGISTER P. 326 UNIVERSAL SHIFT REGISTER P. 327 BARREL SHIFTER P. 327 LINEAR FEEDBACK SHIFT REGISTERS P. 329 COUNTERS P. 332 DECADE COUNTER P. 334 IMAGE 5 GRAY CODE COUNTER P. 335 RING COUNTER P. 336 JOHNSON COUNTER P. 337 STATE MACHINES P. 338 MOORE-TYPE STATE MACHINES P. 338 MEALY-TYPE STATE MACHINES P. 341 VHDL CODES FOR STATE MACHINES USING ENUMERATED TYPES P. 342 MEALY MACHINE IN VHDL P. 345 USER-DEFINED STATE ENCODING P. 351 1-HOT ENCODING P. 355 CASE STUDIES P. 356 EXERCISES P. 368 REFERENCES P. 371 ASYNCHRONOUS SEQUENTIAL CIRCUITS P. 373 INTRODUCTION P. 373 FLOW TABLE P. 374 REDUCTION OF PRIMITIVE HOW TABLES P. 377 STATE ASSIGNMENT P. 379 RACES AND CYCLES P. 379 CRITICAL RACE-FREE STATE ASSIGNMENT P. 381 EXCITATION AND OUTPUT FUNCTIONS P. 387 HAZARDS P. 390 FUNCTION HAZARDS P. 391 LOGIC HAZARDS P. 393 ESSENTIAL HAZARDS P. 396 EXERCISES P. 398 REFERENCES P. 401 CMOS LOGIC P. 403 TRANSMISSION GATES P. 405 CLOCKED CMOS CIRCUITS P. 407 CMOS DOMINO LOGIC P. 408 INDEX P. 411 TABLE OF CONTENTS PROVIDED BY BLACKWELL'S BOOK SERVICES AND R.R. BOWKER. USED WITH PERMISSION.
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spelling	Lala, Parag K. Verfasser aut Principles of modern digital design Parag K. Lala Hoboken, NJ Wiley 2007 XV, 419 S. zahlr. graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier http://www.loc.gov/catdir/enhancements/fy0741/2006032483-d.html. Logic design Logic circuits Design and construction Digital electronics Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 s DE-604 OEBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015862261&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Lala, Parag K. Principles of modern digital design Logic design Logic circuits Design and construction Digital electronics Logischer Entwurf (DE-588)4168051-0 gnd
subject_GND	(DE-588)4168051-0
title	Principles of modern digital design
title_auth	Principles of modern digital design
title_exact_search	Principles of modern digital design
title_exact_search_txtP	Principles of modern digital design
title_full	Principles of modern digital design Parag K. Lala
title_fullStr	Principles of modern digital design Parag K. Lala
title_full_unstemmed	Principles of modern digital design Parag K. Lala
title_short	Principles of modern digital design
title_sort	principles of modern digital design
topic	Logic design Logic circuits Design and construction Digital electronics Logischer Entwurf (DE-588)4168051-0 gnd
topic_facet	Logic design Logic circuits Design and construction Digital electronics Logischer Entwurf
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015862261&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT lalaparagk principlesofmoderndigitaldesign

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