FPGA implementations of neural networks:
Gespeichert in:
| Weitere Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Dordrecht
Springer
2006
|
| Schlagworte: | |
| Online-Zugang: | Inhaltstext Inhaltsverzeichnis |
| Beschreibung: | XII, 360 S. Ill., graph. Darst. |
| ISBN: | 9780387284859 0387284850 |
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Datensatz im Suchindex
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|---|---|
| adam_text | IMAGE 1
CONTENTS
PREFACE
FPGA NEUROCOMPUTERS ARNOS R. OMONDI, JAGATH C. RAJAPAKSE AND MARIUSZ
BAJGER 1.1. INTRODUCTION
1.2. REVIEW OF NEURAL-NETWORK BASICS 1.3. ASTC VS. FPGA NEUROCOMPUTERS
1.4. PARALLELISM IN NEURAL NETWORKS 1.5. XILINX VIRTEX-4 FPGA
1.6. ARITHMETIC
1.7. ACTIVATION-FUNCTION IMPLEMENTATION: UNIPOLAR SIGMOID 1.8.
PERFORMANCE EVALUATION 1.9. CONCLUSIONS
REFERENCES
2
ARITHMETIC PRECISION FOR IMPLEMENTING BP NETWORKS ON FPGA: A CASE S
MEDHAT MOUSSA AND SHAWKI AREIHI AND KRISTIAN NICHOLS 2.1 2.2
2.3 2.4 2.5
2.6
INTRODUCTION BACKGROUND ARCHITECTURE DESIGN AND IMPLEMENTATION
EXPERIMENTS USING LOGICAL-XOR PROBLEM RESULTS AND DISCUSSION CONCLUSIONS
REFERENCES
3
FPNA: CONCEPTS AND PROPERTIES BERNARD GIRAU 3.1 3.2
3.3 3.4 3.5 3.6
INTRODUCTION CHOOSING FPGAS FPNAS, FPNNS CORRECTNESS
UNDERPARAMETERIZED CONVOLUTIONS BY FPNNS CONCLUSIONS REFERENCES
IMAGE 2
VI
FPGA IMPLEMENTATION? OF NEURAL NETWORKS
FPNA: APPLIEATIONS AND IMPLEMENTATIONS BERNARD GIRAU 4.1 4.2
4.3 4.4 4.5 4.6 4.7 4.8 4.9
SUMMARY OF CHAPTER 3 TOWARDS SIMPLIFIED ARCHITECTURES: SYMMETRIE BOOLEAN
FUNETIONS BY FPNAS Y
BENCHMARK APPLIEATIONS
OTHER APPLIEATIONS GENERAL FPGA IMPLEMENTATION SYNCHRONOUS FPNNS
IMPLEMENTATIONS OF SYNCHRONOUS FPNNS IMPLEMENTATION PERFORMANCES
CONCLUSIONS REFERENCES
103
104
105 109 113 116 120 124 130 133 134
BACK-PROPAGATION ALGORITHM AEHIEVING 5 GOPS ON THE VIRTEX-E KOLIN PAUL
AND SANJAY RAJOPADHYE 5.1. INTRODUCTION
5.2. PROBLEM SPEEIFICATION 5.3. SYSTOLIC IMPLEMENTATION OF MATRIX-VECTOR
MULTIPLY 5.4. PIPELINED BACK-PROPAGATION ARCHITECTURE 5.5.
IMPLEMENTATION
5.6. M M A L P HA DESIGN ENVIRONMENT
5.7. ARCHITECTURE DERIVATION 5.8. HARDWARE GENERATION 5.9. PERFORMANCE
EVALUATION 5.10. RELATED WORK 5.1 1. CONCLUSION
APPENDIX REFERENCES
137
138 139 141 142 144 147 149 155 157 159 160
161 163
FPGA IMPLEMENTATION OF VERY LARGE ASSOCIATIVE MEMORIES DAN HAIMNERSTROM,
CHANGJIAN GAO, SHAOJUAN ZHU, MIKE BUTTS 6.1. INTRODUCTION
6.2. ASSOCIATIVE MEMORY 6.3. PC PERFORMANCE EVALUATION 6.4. FPGA
IMPLEMENTATION 6.5. PERFORMANCE COMPARISONS 6.6. SUMMARY AND CONCLUSIONS
REFERENCES
7
FPGA IMPLEMENTATIONS OF NEOCOGNITRONS ALESSANDRO NORIAKI IDE AND JOSE
HIROKI SAITO 1. 1. INTRODUCTION
7.2. NEOCOGNITRON
7.3. ALTERNATIVE NEOCOGNITRON 7.4. RECONFIGURABLE COMPUTER 7.5.
RECONFIGURABLE ORTHOGONAL MEMORY MULTIPROEESSOR
167
167 168 179 184 190 192 193
197
197 198 201 205 206
IMAGE 3
CONTENTS
7.6. ALTERNATIVE NEOCOGNITRON HARDWARE IMPLEMENTATION 7.7. PERFORMANCE
ANALYSIS 7.8. APPLICATIONS
7.9. CONCLUSIONS
REFERENCES
8
SEIF ORGANIZING FEATURE MAP FOR COLOR QUANTIZATION ON FPGA CHIP-HONG
CHANG, MENON SHIBU AND RUI XIAO 8.1. INTRODUCTION
8.2. ALGORITHMIC ADJUSTMENT 8.3. ARCHITECTURE
8.4. IMPLEMENTATION
8.5. EXPERIMENTAL RESULTS 8.6. CONCLUSIONS
REFERENCES
9
IMPLEMENTATION OF SELF-ORGANIZING FEATURE MAPS IN RECONFIGURABLE
HARDWARE MARIO PORRMANN, ULF WITKOWSKI, AND ULRICH RUECKEN 9.1.
INTRODUCTION
9.2. USING RECONFIGURABLE HARDWARE FOR NEURAL NETWORKS 9.3. THE
DYNAMICALLY RECONFIGURABLE RAPID PROTOTYPING SYSTEM RAPTOR2000 9.4.
IMPLEMENTING SELF-ORGANIZING FEATURE MAPS ON RAPTOR2000 9.5. CONCLUSIONS
REFERENCES
10 FPGA IMPLEMENTATION OF A FULLY AND PARTIALLY CONNECTED MLP
ANTONIO CANAS, EVA M. ORTIGOSA, EDUARDO ROS AND PILAR M. ORTIGOSA 10.1.
INTRODUCTION
10.2. MLP/XMLP AND SPEECH RECOGNITION 10.3. ACTIVATION FUNCTIONS AND
DISCRETIZATION PROBLEM 10.4. HARDWARE IMPLEMENTATIONS OF MLP 10.5.
HARDWARE IMPLEMENTATIONS OF XMLP
10.6. CONCLUSIONS
ACKNOWLEDGMENTS REFERENCES
11 FPGA IMPLEMENTATION OF NON-LINEAR PREDICTORS RAFAEL GADEA-GIRONES AND
AGUSTN RAMREZ-AGUNDIS 11.1. INTRODUCTION
11.2. PIPELINE AND BACK-PROPAGATION ALGORITHM 11.3. SYNTHESIS AND FPGAS
11.4. IMPLEMENTATION ON FPGA 11.5. CONCLUSIONS
REFERENCES
IMAGE 4
K
AEJ
V LN FPGA IMPLEMENTATION? OF NEURAL NETWORKS
12 THE REMAP RECONFIGURABLE ARCHITECTURE: A RETROSPECTIVE 325
LARS BENGTSSON, ARNE LINDE, TOMAS NORDSTROM, BERTIL SVENSSON, AND MIKAEL
TAVENIKU 12.1. INTRODUCTION 12.2. TARGET APPLICATION AREA
12.3. REMAP-/J - DESIGN AND IMPLEMENTATION 12.4. NEURAL NETWORKS MAPPED
ON REMAP-/3 12.5. REMAP-7 ARCHITECTURE 12.6. DISCUSSION
12.7. CONCLUSIONS ACKNOWLEDGMENTS REFERENCES
326 327 335 346 353 354 357 357
357
|
| adam_txt |
IMAGE 1
CONTENTS
PREFACE
FPGA NEUROCOMPUTERS ARNOS R. OMONDI, JAGATH C. RAJAPAKSE AND MARIUSZ
BAJGER 1.1. INTRODUCTION
1.2. REVIEW OF NEURAL-NETWORK BASICS 1.3. ASTC VS. FPGA NEUROCOMPUTERS
1.4. PARALLELISM IN NEURAL NETWORKS 1.5. XILINX VIRTEX-4 FPGA
1.6. ARITHMETIC
1.7. ACTIVATION-FUNCTION IMPLEMENTATION: UNIPOLAR SIGMOID 1.8.
PERFORMANCE EVALUATION 1.9. CONCLUSIONS
REFERENCES
2
ARITHMETIC PRECISION FOR IMPLEMENTING BP NETWORKS ON FPGA: A CASE S
MEDHAT MOUSSA AND SHAWKI AREIHI AND KRISTIAN NICHOLS 2.1 2.2
2.3 2.4 2.5
2.6
INTRODUCTION BACKGROUND ARCHITECTURE DESIGN AND IMPLEMENTATION
EXPERIMENTS USING LOGICAL-XOR PROBLEM RESULTS AND DISCUSSION CONCLUSIONS
REFERENCES
3
FPNA: CONCEPTS AND PROPERTIES BERNARD GIRAU 3.1 3.2
3.3 3.4 3.5 3.6
INTRODUCTION CHOOSING FPGAS FPNAS, FPNNS CORRECTNESS
UNDERPARAMETERIZED CONVOLUTIONS BY FPNNS CONCLUSIONS REFERENCES
IMAGE 2
VI
FPGA IMPLEMENTATION? OF NEURAL NETWORKS
FPNA: APPLIEATIONS AND IMPLEMENTATIONS BERNARD GIRAU 4.1 4.2
4.3 4.4 4.5 4.6 4.7 4.8 4.9
SUMMARY OF CHAPTER 3 TOWARDS SIMPLIFIED ARCHITECTURES: SYMMETRIE BOOLEAN
FUNETIONS BY FPNAS Y
BENCHMARK APPLIEATIONS
OTHER APPLIEATIONS GENERAL FPGA IMPLEMENTATION SYNCHRONOUS FPNNS
IMPLEMENTATIONS OF SYNCHRONOUS FPNNS IMPLEMENTATION PERFORMANCES
CONCLUSIONS REFERENCES
103
104
105 109 113 116 120 124 130 133 134
BACK-PROPAGATION ALGORITHM AEHIEVING 5 GOPS ON THE VIRTEX-E KOLIN PAUL
AND SANJAY RAJOPADHYE 5.1. INTRODUCTION
5.2. PROBLEM SPEEIFICATION 5.3. SYSTOLIC IMPLEMENTATION OF MATRIX-VECTOR
MULTIPLY 5.4. PIPELINED BACK-PROPAGATION ARCHITECTURE 5.5.
IMPLEMENTATION
5.6. M M A L P HA DESIGN ENVIRONMENT
5.7. ARCHITECTURE DERIVATION 5.8. HARDWARE GENERATION 5.9. PERFORMANCE
EVALUATION 5.10. RELATED WORK 5.1 1. CONCLUSION
APPENDIX REFERENCES
137
138 139 141 142 144 147 149 155 157 159 160
161 163
FPGA IMPLEMENTATION OF VERY LARGE ASSOCIATIVE MEMORIES DAN HAIMNERSTROM,
CHANGJIAN GAO, SHAOJUAN ZHU, MIKE BUTTS 6.1. INTRODUCTION
6.2. ASSOCIATIVE MEMORY 6.3. PC PERFORMANCE EVALUATION 6.4. FPGA
IMPLEMENTATION 6.5. PERFORMANCE COMPARISONS 6.6. SUMMARY AND CONCLUSIONS
REFERENCES
7
FPGA IMPLEMENTATIONS OF NEOCOGNITRONS ALESSANDRO NORIAKI IDE AND JOSE
HIROKI SAITO 1. 1. INTRODUCTION
7.2. NEOCOGNITRON
7.3. ALTERNATIVE NEOCOGNITRON 7.4. RECONFIGURABLE COMPUTER 7.5.
RECONFIGURABLE ORTHOGONAL MEMORY MULTIPROEESSOR
167
167 168 179 184 190 192 193
197
197 198 201 205 206
IMAGE 3
CONTENTS
7.6. ALTERNATIVE NEOCOGNITRON HARDWARE IMPLEMENTATION 7.7. PERFORMANCE
ANALYSIS 7.8. APPLICATIONS
7.9. CONCLUSIONS
REFERENCES
8
SEIF ORGANIZING FEATURE MAP FOR COLOR QUANTIZATION ON FPGA CHIP-HONG
CHANG, MENON SHIBU AND RUI XIAO 8.1. INTRODUCTION
8.2. ALGORITHMIC ADJUSTMENT 8.3. ARCHITECTURE
8.4. IMPLEMENTATION
8.5. EXPERIMENTAL RESULTS 8.6. CONCLUSIONS
REFERENCES
9
IMPLEMENTATION OF SELF-ORGANIZING FEATURE MAPS IN RECONFIGURABLE
HARDWARE MARIO PORRMANN, ULF WITKOWSKI, AND ULRICH RUECKEN 9.1.
INTRODUCTION
9.2. USING RECONFIGURABLE HARDWARE FOR NEURAL NETWORKS 9.3. THE
DYNAMICALLY RECONFIGURABLE RAPID PROTOTYPING SYSTEM RAPTOR2000 9.4.
IMPLEMENTING SELF-ORGANIZING FEATURE MAPS ON RAPTOR2000 9.5. CONCLUSIONS
REFERENCES
10 FPGA IMPLEMENTATION OF A FULLY AND PARTIALLY CONNECTED MLP
ANTONIO CANAS, EVA M. ORTIGOSA, EDUARDO ROS AND PILAR M. ORTIGOSA 10.1.
INTRODUCTION
10.2. MLP/XMLP AND SPEECH RECOGNITION 10.3. ACTIVATION FUNCTIONS AND
DISCRETIZATION PROBLEM 10.4. HARDWARE IMPLEMENTATIONS OF MLP 10.5.
HARDWARE IMPLEMENTATIONS OF XMLP
10.6. CONCLUSIONS
ACKNOWLEDGMENTS REFERENCES
11 FPGA IMPLEMENTATION OF NON-LINEAR PREDICTORS RAFAEL GADEA-GIRONES AND
AGUSTN RAMREZ-AGUNDIS 11.1. INTRODUCTION
11.2. PIPELINE AND BACK-PROPAGATION ALGORITHM 11.3. SYNTHESIS AND FPGAS
11.4. IMPLEMENTATION ON FPGA 11.5. CONCLUSIONS
REFERENCES
IMAGE 4
K
AEJ
V LN FPGA IMPLEMENTATION? OF NEURAL NETWORKS
12 THE REMAP RECONFIGURABLE ARCHITECTURE: A RETROSPECTIVE 325
LARS BENGTSSON, ARNE LINDE, TOMAS NORDSTROM, BERTIL SVENSSON, AND MIKAEL
TAVENIKU 12.1. INTRODUCTION 12.2. TARGET APPLICATION AREA
12.3. REMAP-/J - DESIGN AND IMPLEMENTATION 12.4. NEURAL NETWORKS MAPPED
ON REMAP-/3 12.5. REMAP-7 ARCHITECTURE 12.6. DISCUSSION
12.7. CONCLUSIONS ACKNOWLEDGMENTS REFERENCES
326 327 335 346 353 354 357 357
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| subject_GND | (DE-588)4347749-5 (DE-588)4226127-2 |
| title | FPGA implementations of neural networks |
| title_auth | FPGA implementations of neural networks |
| title_exact_search | FPGA implementations of neural networks |
| title_exact_search_txtP | FPGA implementations of neural networks |
| title_full | FPGA implementations of neural networks ed. by Amos R. Omondi ... |
| title_fullStr | FPGA implementations of neural networks ed. by Amos R. Omondi ... |
| title_full_unstemmed | FPGA implementations of neural networks ed. by Amos R. Omondi ... |
| title_short | FPGA implementations of neural networks |
| title_sort | fpga implementations of neural networks |
| topic | Field programmable gate arrays Neural networks (Computer science) Field programmable gate array (DE-588)4347749-5 gnd Neuronales Netz (DE-588)4226127-2 gnd |
| topic_facet | Field programmable gate arrays Neural networks (Computer science) Field programmable gate array Neuronales Netz |
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