Modeling and automated synthesis of reconfigurable interfaces:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
2006
|
| Schlagworte: | |
| Online-Zugang: | Volltext http://d-nb.info/98328363x/34 Inhaltsverzeichnis |
| Beschreibung: | Paderborn, Univ., Diss., 2006 |
| Beschreibung: | 1 Online-Ressource |
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Datensatz im Suchindex
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|---|---|
| adam_text | Contents
List of Figures ;, ;
List of Tables vjjj
1 Introduction
1.1 Motivation and Challenges 1
1.2 Aim of the Thesis 3
1.3 Contribution of the Thesis 5
1.4 Organization of the Work 6
2 Communication Framework for Embedded Systems 7
2.1 Framework 7
2.1.1 Tasks Media 8
2.1.2 System Composition 8
2.1.3 Hardware Software Interfaces 9
2.1.4 Modeling Interfaces 11
2.1.5 Scenarios for Interface Adaptation 17
2.2 System Architecture 17
2.2.1 The IFS System Architecture Model 17
2.2.2 Modeling the IFB Target Platform 19
2.2.3 Hardware Execution Platform 20
2.2.4 Software Execution Platform 22
2.2.5 The Hardware/Software Interface 23
2.3 The Role of Reconfiguration 25
2.4 Summary 26
3 Background Related Work 27
3.1 System Level Design 27
3.1.1 Levels of Abstraction 28
3.1.2 Y Chart and P Chart 30
3.1.3 Intellectual Property and IP Based Design 31
3.2 Interface Aware (System Level) Design Flows 34
3.2.1 Interface and IP Descriptions 34
3.2.2 Design Flows 40
3.3 R,econfigurable Systems 42
3.3.1 The FPGA A Reconfigurable Hardware Platform 42
3.3.2 Communication in Reconfigurable Architectures 44
3.3.3 How to Avoid the Communication Gap? 46
3.4 Dedicated Interface Synthesis Approaches 48
3.4.1 Interface Synthesis for Communication APIs (SW/SW) 50
3.4.2 Systematic Protocol Construction Approaches (HW/HW) 51
3.4.3 Protocol Wrapping/Adaptation Approaches (HW/HW) 52
3.4.4 Adaptation of Hardware Software Interfaces (HW/SW) 54
3.5 Summary 56
3.5.1 Interface Synthesis Requirements Specification 57
4 Interface Synthesis Methodology 59
4.1 Interface Synthesis Design Flow 60
4.1.1 Modeling Phase 61
4.1.2 Synthesis Phase 63
4.1.3 Integration Phase 65
4.2 IFS Modeling Concept 66
4.2.1 The Interface Synthesis Format 67
4.2.2 Interaction of XML and Java 70
4.2.3 UML 2.0 and its Interaction with XML and Java 71
4.3 Concepts of the Interface Block 73
4.3.1 IFB Macro Structure 73
4.4 IFB Reconfiguration 80
4.4.1 The Runtime Reconfigurable IFB (RTR IFB) 82
4.4.2 Fonnalization of the FPGA Placement 90
4.4.3 Runtime Self Reconfiguration Using the RCU 91
4.4.4 Example: A Multi Controller Design 92
4.5 Fail Safe Behavior 95
4.5.1 Basic Concepts of Error Processing 96
4.5.2 Integrating Error Processing into an IFB 97
4.5.3 Case Study: Robot Scenario 98
4.6 Relation to the ISO/OSI Model 100
4.7 Prototyping of Real Time Communication 101
4.8 Summary 103
5 The Detailed Interface Synthesis Design Flow 105
5.1 Modeling Phase 105
5.1.1 Modeling the UML 2.0 Profile 106
5.1.2 Tool Coupling of the IFS Editor with the CASE tool Fujaba .... 113
5.1.3 Model Transformation from UML 2.0 to Java 115
5.2 Synthesis Phase Design Step 1: IFB Model Synthesis 116
5.2.1 Prepare Synthesis Input 118
5.2.2 Basic Blocks 120
5.2.3 Protocol Matrix and Protocol Packages 120
5.2.4 Protocol Frames 122
5.2.5 Protocol Synthesis Generation of the Protocol State Machines . . . 124
5.2.6 IFD Mapping 130
5.2.7 IFD Optimization and Creation of the Protocol Frames 136
5.2.8 Assembly of the IFB Model (Intermediate Representation) 137
5.3 Synthesis Phase Design Step 2: IFB Code Generation 143
¦ 5.3.1 Frame Processing 144
5.3.2 Adapted Frame Processing Model 144
5.3.3 Overview of the Generated VHDL Code Pattern 145
5.3.4 The Three levels of IFS Code Generation 146
5.4 Code Integration Phase 147
5.5 Extension of the Interface Synthesis Design Flow 148
5.5.1 Creation of a Globally Optimized Communication Infrastructure . . . 148
5.6 Summary 151
6 The Interface Block (IFB) 153
6.1 IFB Hardware Template 153
6.1.1 Protocol Handler 156
6.1.2 Sequence Handler 156
6.1.3 Control Unit 158
6.2 Cycle Accurate Analysis of an IFB 161
6.3 Timing Analysis 162
6.3.1 Feasibility Analysis 162
6.3.2 Schedulability Analysis 164
6.4 IFB Optimization 168
6.4.1 Data Flow (Latency) Optimization 168
6.4.2 Area Optimization 173
6.5 Summary 179
7 Results 181
7.1 The IFS Design Environment: IFS Editor 181
7.2 Case Study: Adaptation of RFID to I2C 183
7.3 Comparison With Other Approaches 185
8 Conclusion and Outlook 187
8.1 Conclusion 187
8.2 Outlook 190
A Extensions to the Interface Synthesis 191
A.I Communication Cycles 191
A.2 Generating Basic Blocks 192
A. 3 Grammar of the IFD Mapping Language 193
A.4 VHDL Examples for the Created IFB Target Code 194
A.5 Template of the Reconfiguration Control Unit 198
A.6 Validity Period of Control Signals inside Protocol Frames 199
Own Previous Work 201
Advised Bachelor Thesis and Diploma Thesis 205
Bibliography 207
List of Abbreviations 223
|
| adam_txt |
Contents
List of Figures ;, ;
List of Tables vjjj
1 Introduction \
1.1 Motivation and Challenges 1
1.2 Aim of the Thesis 3
1.3 Contribution of the Thesis 5
1.4 Organization of the Work 6
2 Communication Framework for Embedded Systems 7
2.1 Framework 7
2.1.1 Tasks Media 8
2.1.2 System Composition 8
2.1.3 Hardware Software Interfaces 9
2.1.4 Modeling Interfaces 11
2.1.5 Scenarios for Interface Adaptation 17
2.2 System Architecture 17
2.2.1 The IFS System Architecture Model 17
2.2.2 Modeling the IFB Target Platform 19
2.2.3 Hardware Execution Platform 20
2.2.4 Software Execution Platform 22
2.2.5 The Hardware/Software Interface 23
2.3 The Role of Reconfiguration 25
2.4 Summary 26
3 Background Related Work 27
3.1 System Level Design 27
3.1.1 Levels of Abstraction 28
3.1.2 Y Chart and P Chart 30
3.1.3 Intellectual Property and IP Based Design 31
3.2 Interface Aware (System Level) Design Flows 34
3.2.1 Interface and IP Descriptions 34
3.2.2 Design Flows 40
3.3 R,econfigurable Systems 42
3.3.1 The FPGA A Reconfigurable Hardware Platform 42
3.3.2 Communication in Reconfigurable Architectures 44
3.3.3 How to Avoid the Communication Gap? 46
3.4 Dedicated Interface Synthesis Approaches 48
3.4.1 Interface Synthesis for Communication APIs (SW/SW) 50
3.4.2 Systematic Protocol Construction Approaches (HW/HW) 51
3.4.3 Protocol Wrapping/Adaptation Approaches (HW/HW) 52
3.4.4 Adaptation of Hardware Software Interfaces (HW/SW) 54
3.5 Summary 56
3.5.1 Interface Synthesis Requirements Specification 57
4 Interface Synthesis Methodology 59
4.1 Interface Synthesis Design Flow 60
4.1.1 Modeling Phase 61
4.1.2 Synthesis Phase 63
4.1.3 Integration Phase 65
4.2 IFS Modeling Concept 66
4.2.1 The Interface Synthesis Format 67
4.2.2 Interaction of XML and Java 70
4.2.3 UML 2.0 and its Interaction with XML and Java 71
4.3 Concepts of the Interface Block 73
4.3.1 IFB Macro Structure 73
4.4 IFB Reconfiguration 80
4.4.1 The Runtime Reconfigurable IFB (RTR IFB) 82
4.4.2 Fonnalization of the FPGA Placement 90
4.4.3 Runtime Self Reconfiguration Using the RCU 91
4.4.4 Example: A Multi Controller Design 92
4.5 Fail Safe Behavior 95
4.5.1 Basic Concepts of Error Processing 96
4.5.2 Integrating Error Processing into an IFB 97
4.5.3 Case Study: Robot Scenario 98
4.6 Relation to the ISO/OSI Model 100
4.7 Prototyping of Real Time Communication 101
4.8 Summary 103
5 The Detailed Interface Synthesis Design Flow 105
5.1 Modeling Phase 105
5.1.1 Modeling the UML 2.0 Profile 106
5.1.2 Tool Coupling of the IFS Editor with the CASE tool Fujaba . 113
5.1.3 Model Transformation from UML 2.0 to Java 115
5.2 Synthesis Phase Design Step 1: IFB Model Synthesis 116
5.2.1 Prepare Synthesis Input 118
5.2.2 Basic Blocks 120
5.2.3 Protocol Matrix and Protocol Packages 120
5.2.4 Protocol Frames 122
5.2.5 Protocol Synthesis Generation of the Protocol State Machines . . . 124
5.2.6 IFD Mapping 130
5.2.7 IFD Optimization and Creation of the Protocol Frames 136
5.2.8 Assembly of the IFB Model (Intermediate Representation) 137
5.3 Synthesis Phase Design Step 2: IFB Code Generation 143
¦ 5.3.1 Frame Processing 144
5.3.2 Adapted Frame Processing Model 144
5.3.3 Overview of the Generated VHDL Code Pattern 145
5.3.4 The Three levels of IFS Code Generation 146
5.4 Code Integration Phase 147
' 5.5 Extension of the Interface Synthesis Design Flow 148
5.5.1 Creation of a Globally Optimized Communication Infrastructure . . . 148
5.6 Summary 151
6 The Interface Block (IFB) 153
6.1 IFB Hardware Template 153
6.1.1 Protocol Handler 156
6.1.2 Sequence Handler 156
6.1.3 Control Unit 158
6.2 Cycle Accurate Analysis of an IFB 161
6.3 Timing Analysis 162
6.3.1 Feasibility Analysis 162
6.3.2 Schedulability Analysis 164
6.4 IFB Optimization 168
6.4.1 Data Flow (Latency) Optimization 168
6.4.2 Area Optimization 173
6.5 Summary 179
7 Results 181
7.1 The IFS Design Environment: IFS Editor 181
7.2 Case Study: Adaptation of RFID to I2C 183
7.3 Comparison With Other Approaches 185
8 Conclusion and Outlook 187
8.1 Conclusion 187
8.2 Outlook 190
A Extensions to the Interface Synthesis 191
A.I Communication Cycles 191
A.2 Generating Basic Blocks 192
A. 3 Grammar of the IFD Mapping Language 193
A.4 VHDL Examples for the Created IFB Target Code 194
A.5 Template of the Reconfiguration Control Unit 198
A.6 Validity Period of Control Signals inside Protocol Frames 199
Own Previous Work 201
Advised Bachelor Thesis and Diploma Thesis 205
Bibliography 207
List of Abbreviations 223 |
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| dewey-search | 004.21 |
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| discipline | Informatik |
| discipline_str_mv | Informatik |
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| spelling | Ihmor, Stefan 1977- Verfasser (DE-588)130851221 aut Modeling and automated synthesis of reconfigurable interfaces von Stefan Ihmor 2006 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Paderborn, Univ., Diss., 2006 Logiksynthese (DE-588)4348178-4 gnd rswk-swf Rekonfiguration (DE-588)4306238-6 gnd rswk-swf Schnittstelle (DE-588)4053059-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Schnittstelle (DE-588)4053059-0 s Rekonfiguration (DE-588)4306238-6 s Logiksynthese (DE-588)4348178-4 s DE-604 http://ubdata.uni-paderborn.de/ediss/17/2006/ihmor/ kostenfrei Volltext http://d-nb.info/98328363x/34 HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015506730&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Ihmor, Stefan 1977- Modeling and automated synthesis of reconfigurable interfaces Logiksynthese (DE-588)4348178-4 gnd Rekonfiguration (DE-588)4306238-6 gnd Schnittstelle (DE-588)4053059-0 gnd |
| subject_GND | (DE-588)4348178-4 (DE-588)4306238-6 (DE-588)4053059-0 (DE-588)4113937-9 |
| title | Modeling and automated synthesis of reconfigurable interfaces |
| title_auth | Modeling and automated synthesis of reconfigurable interfaces |
| title_exact_search | Modeling and automated synthesis of reconfigurable interfaces |
| title_exact_search_txtP | Modeling and automated synthesis of reconfigurable interfaces |
| title_full | Modeling and automated synthesis of reconfigurable interfaces von Stefan Ihmor |
| title_fullStr | Modeling and automated synthesis of reconfigurable interfaces von Stefan Ihmor |
| title_full_unstemmed | Modeling and automated synthesis of reconfigurable interfaces von Stefan Ihmor |
| title_short | Modeling and automated synthesis of reconfigurable interfaces |
| title_sort | modeling and automated synthesis of reconfigurable interfaces |
| topic | Logiksynthese (DE-588)4348178-4 gnd Rekonfiguration (DE-588)4306238-6 gnd Schnittstelle (DE-588)4053059-0 gnd |
| topic_facet | Logiksynthese Rekonfiguration Schnittstelle Hochschulschrift |
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| work_keys_str_mv | AT ihmorstefan modelingandautomatedsynthesisofreconfigurableinterfaces |