Real-time multitasking in embedded systems based on reconfigurable hardware:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
2006
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| Schlagworte: | |
| Online-Zugang: | kostenfrei http://d-nb.info/983267219/34 Inhaltsverzeichnis |
| Beschreibung: | Paderborn, Univ., Diss., 2006 |
| Beschreibung: | 1 Online-Ressource |
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Datensatz im Suchindex
| _version_ | 1804136312428560384 |
|---|---|
| adam_text | Contents
List of Figures vii
List of Tables ix
Abstract 1
1 Introduction 3
1.1 Motivation to Real Time Multitasking 4
1.2 Contribution of This Thesis 6
1.3 Chapter Outline 7
2 Background and Related Work 9
2.1 Reconfigurable Hardware Devices 10
2.1.1 Fine Grain RHDs (FPGAs) 10
2.1.2 Coarse Grain RHDs 12
2.1.3 Configuration Memory and Reconfiguration 13
2.1.4 Architecture of RHD Based Computer Platforms 14
2.2 Hardware Tasks 16
2.3 Multi Tasking on Reconfigurable Hardware 20
2.3.1 Resource Sharing Models 20
2.3.2 Task Scheduling and Placement Methods for RHDs 26
2.3.3 Dynamic Reconfigurable Systems 26
2.4 Real Time Scheduling 30
2.4.1 A Background on RT Systems 30
2.4.2 RT Scheduling Problems and Algorithms for Uniprocessor Systems 31
2.4.3 RT Scheduling Problems and Algorithms for Multiprocessor Systems 33
2.4.4 Real Time Scheduling on RHDs and Similar Architectures .... 38
2.5 Chapter Conclusion 40
3 Problem Modeling and Metrics 43
3.1 Task and Resource Models 43
3.2 Feasible Schedule 47
3.3 Utilization Metrics 48
3.4 Chapter Conclusion 50
iii
Contents
4 Three Scheduling Algorithms 51
4.1 Global Scheduling 53
4.1.1 Earliest Deadline First on RHDs 53
4.1.2 Relation to Multiprocessor EDF 55
4.1.3 Schedulability Analysis for EDF FkF 56
4.1.4 Conclusion on global EDF 62
4.2 Partitioned Scheduling 63
4.2.1 Partitioned Scheduling on RHDs 63
4.2.2 Relation to 2 Dimensional Packing Problems 65
4.2.3 Optimal Partitioning by ILP 66
4.2.4 Next Fit Decreasing Area Partitioning 69
4.2.5 Conclusion on Partitioned EDF 74
4.3 Server Based Scheduling 75
4.3.1 The Merge Server Distribute Load (MSDL) Algorithm 75
4.3.2 Exact Evaluation of Computation Time Reduction 78
4.3.3 Properties of MSDL 80
4.3.4 Conclusion on Server Based Scheduling 81
4.4 Chapter Conclusion 81
5 Comparison of Algorithm Scheduling Performance 83
5.1 Analytical Comparison and Scheduling Anomalies 83
5.2 Simulation Results 90
5.2.1 Creation of Benchmarks ¦ 90
5.2.2 Performance on Standard Benchmark BMstci 92
5.2.3 Impact of Area and Time utilization 94
5.2.4 Performance of Combined Algorithms 96
5.2.5 Impact of Number of Tasks 97
5.3 Conclusion on Algorithm Performance 99
6 Execution Model and Overhead Analysis 101
6.1 Global EDF Overhead Model . 101
6.1.1 Reconfiguration Modes and Task Placement 101
6.1.2 Runtime System Requirements 104
6.1.3 Reconfiguration Overheads 104
6.2 Partitioned EDF Overhead Model 106
6.2.1 Reconfiguration Modes and Task Placement 106
6.2.2 Runtime System Requirements 107
6.2.3 Reconfiguration Overheads 107
6.3 Server Based MSDL Overhead Model 109
6.3.1 Reconfiguration Modes and Task Placement 109
6.3.2 Runtime System Requirements 109
6.3.3 Reconfiguration Overheads 109
6.4 Performance Evaluation Including Overhead 110
6.4.1 Global EDF Overhead Evaluation 110
6.4.2 Partitioned EDF Overhead Evaluation 112
6.4.3 Server Based MSDL Overhead Evaluation 112
Contents
6.5 Conclusion on Execution Models and Overhead 113
7 Model Extensions 115
7.1 Periodic Tasks with Variants 115
7.1.1 Variant Rich Tasks 116
7.1.2 Partitioned Scheduling of Variant Rich Tasks 119
7.1.3 Optimal Partitioning by ILP 121
7.1.4 Performance Evaluation for Variant Rich Tasks 124
7.1.5 Approaches for Global and Server Scheduling of Variant Rich Tasksl26
7.2 Periodic Tasks with Memory Access 128
7.2.1 The Buffer Assignment Problem 129
7.2.2 Task Schedule Aware Buffer Assignment 132
7.2.3 Buffer Assignment Based on Integer Programming 134
7.2.4 Simulation Results 135
7.2.5 Concluding Discussion on Memory Demanding RT Applications 136
7.3 Chapter Conclusion 137
8 Prototype: FPGA Based Real Time Kernel 139
8.1 System Architecture 139
8.1.1 An All Hardware Runtime System 139
8.1.2 Scheduler Data Structures 141
8.1.3 The Scheduler Cycle 142
8.2 Synthesis Tool Flow 143
8.3 Synthesis Results 145
8.4 Chapter Conclusion 146
9 Conclusion and Outlook 149
9.1 Summary 149
9.2 Drawn Conclusions 150
9.3 Outlook and Future Work 152
Author s Publications 155
Bibliography 159
|
| adam_txt |
Contents
List of Figures vii
List of Tables ix
Abstract 1
1 Introduction 3
1.1 Motivation to Real Time Multitasking 4
1.2 Contribution of This Thesis 6
1.3 Chapter Outline 7
2 Background and Related Work 9
2.1 Reconfigurable Hardware Devices 10
2.1.1 Fine Grain RHDs (FPGAs) 10
2.1.2 Coarse Grain RHDs 12
2.1.3 Configuration Memory and Reconfiguration 13
2.1.4 Architecture of RHD Based Computer Platforms 14
2.2 Hardware Tasks 16
2.3 Multi Tasking on Reconfigurable Hardware 20
2.3.1 Resource Sharing Models 20
2.3.2 Task Scheduling and Placement Methods for RHDs 26
2.3.3 Dynamic Reconfigurable Systems 26
2.4 Real Time Scheduling 30
2.4.1 A Background on RT Systems 30
2.4.2 RT Scheduling Problems and Algorithms for Uniprocessor Systems 31
2.4.3 RT Scheduling Problems and Algorithms for Multiprocessor Systems 33
2.4.4 Real Time Scheduling on RHDs and Similar Architectures . 38
2.5 Chapter Conclusion 40
3 Problem Modeling and Metrics 43
3.1 Task and Resource Models 43
3.2 Feasible Schedule 47
3.3 Utilization Metrics 48
3.4 Chapter Conclusion 50
iii
Contents
4 Three Scheduling Algorithms 51
4.1 Global Scheduling 53
4.1.1 Earliest Deadline First on RHDs 53
4.1.2 Relation to Multiprocessor EDF 55
4.1.3 Schedulability Analysis for EDF FkF 56
4.1.4 Conclusion on global EDF 62
4.2 Partitioned Scheduling 63
4.2.1 Partitioned Scheduling on RHDs 63
4.2.2 Relation to 2 Dimensional Packing Problems 65
4.2.3 Optimal Partitioning by ILP 66
4.2.4 Next Fit Decreasing Area Partitioning 69
4.2.5 Conclusion on Partitioned EDF 74
4.3 Server Based Scheduling 75
4.3.1 The Merge Server Distribute Load (MSDL) Algorithm 75
4.3.2 Exact Evaluation of Computation Time Reduction 78
4.3.3 Properties of MSDL 80
4.3.4 Conclusion on Server Based Scheduling 81
4.4 Chapter Conclusion 81
5 Comparison of Algorithm Scheduling Performance 83
5.1 Analytical Comparison and Scheduling Anomalies 83
5.2 Simulation Results 90
5.2.1 Creation of Benchmarks ¦ 90
5.2.2 Performance on Standard Benchmark BMstci 92
5.2.3 Impact of Area and Time utilization 94
5.2.4 Performance of Combined Algorithms 96
5.2.5 Impact of Number of Tasks 97
5.3 Conclusion on Algorithm Performance 99
6 Execution Model and Overhead Analysis 101
6.1 Global EDF Overhead Model . 101
6.1.1 Reconfiguration Modes and Task Placement 101
6.1.2 Runtime System Requirements 104
6.1.3 Reconfiguration Overheads 104
6.2 Partitioned EDF Overhead Model 106
6.2.1 Reconfiguration Modes and Task Placement 106
6.2.2 Runtime System Requirements 107
6.2.3 Reconfiguration Overheads 107
6.3 Server Based MSDL Overhead Model 109
6.3.1 Reconfiguration Modes and Task Placement 109
6.3.2 Runtime System Requirements 109
6.3.3 Reconfiguration Overheads 109
6.4 Performance Evaluation Including Overhead 110
6.4.1 Global EDF Overhead Evaluation 110
6.4.2 Partitioned EDF Overhead Evaluation 112
6.4.3 Server Based MSDL Overhead Evaluation 112
Contents
6.5 Conclusion on Execution Models and Overhead 113
7 Model Extensions 115
7.1 Periodic Tasks with Variants 115
7.1.1 Variant Rich Tasks 116
7.1.2 Partitioned Scheduling of Variant Rich Tasks 119
7.1.3 Optimal Partitioning by ILP 121
7.1.4 Performance Evaluation for Variant Rich Tasks 124
7.1.5 Approaches for Global and Server Scheduling of Variant Rich Tasksl26
7.2 Periodic Tasks with Memory Access 128
7.2.1 The Buffer Assignment Problem 129
7.2.2 Task Schedule Aware Buffer Assignment 132
7.2.3 Buffer Assignment Based on Integer Programming 134
7.2.4 Simulation Results 135
7.2.5 Concluding Discussion on Memory Demanding RT Applications 136
7.3 Chapter Conclusion 137
8 Prototype: FPGA Based Real Time Kernel 139
8.1 System Architecture 139
8.1.1 An All Hardware Runtime System 139
8.1.2 Scheduler Data Structures 141
8.1.3 The Scheduler Cycle 142
8.2 Synthesis Tool Flow 143
8.3 Synthesis Results 145
8.4 Chapter Conclusion 146
9 Conclusion and Outlook 149
9.1 Summary 149
9.2 Drawn Conclusions 150
9.3 Outlook and Future Work 152
Author's Publications 155
Bibliography 159 |
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| spelling | Danne, Klaus 1976- Verfasser (DE-588)132652056 aut Real-time multitasking in embedded systems based on reconfigurable hardware von Klaus Danne 2006 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Paderborn, Univ., Diss., 2006 Rekonfiguration (DE-588)4306238-6 gnd rswk-swf Echtzeitverarbeitung (DE-588)4151002-1 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Eingebettetes System (DE-588)4396978-1 s Rekonfiguration (DE-588)4306238-6 s Echtzeitverarbeitung (DE-588)4151002-1 s DE-604 http://ubdata.uni-paderborn.de/ediss/17/2006/danne/ kostenfrei Volltext http://d-nb.info/983267219/34 HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015506630&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Danne, Klaus 1976- Real-time multitasking in embedded systems based on reconfigurable hardware Rekonfiguration (DE-588)4306238-6 gnd Echtzeitverarbeitung (DE-588)4151002-1 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| subject_GND | (DE-588)4306238-6 (DE-588)4151002-1 (DE-588)4396978-1 (DE-588)4113937-9 |
| title | Real-time multitasking in embedded systems based on reconfigurable hardware |
| title_auth | Real-time multitasking in embedded systems based on reconfigurable hardware |
| title_exact_search | Real-time multitasking in embedded systems based on reconfigurable hardware |
| title_exact_search_txtP | Real-time multitasking in embedded systems based on reconfigurable hardware |
| title_full | Real-time multitasking in embedded systems based on reconfigurable hardware von Klaus Danne |
| title_fullStr | Real-time multitasking in embedded systems based on reconfigurable hardware von Klaus Danne |
| title_full_unstemmed | Real-time multitasking in embedded systems based on reconfigurable hardware von Klaus Danne |
| title_short | Real-time multitasking in embedded systems based on reconfigurable hardware |
| title_sort | real time multitasking in embedded systems based on reconfigurable hardware |
| topic | Rekonfiguration (DE-588)4306238-6 gnd Echtzeitverarbeitung (DE-588)4151002-1 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| topic_facet | Rekonfiguration Echtzeitverarbeitung Eingebettetes System Hochschulschrift |
| url | http://ubdata.uni-paderborn.de/ediss/17/2006/danne/ http://d-nb.info/983267219/34 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=015506630&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT danneklaus realtimemultitaskinginembeddedsystemsbasedonreconfigurablehardware |