Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
1982
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| Schlagworte: | |
| Beschreibung: | Madison, Wis., Univ., Diss., 1982. -Kopie, erschienen im Verl. Univ. Microfilms Internat., Ann Arbor, Mich. |
| Beschreibung: | VIII, 246 S. graph. Darst. |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV021992671 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 060120s1982 d||| m||| 00||| eng d | ||
| 035 | |a (OCoLC)9169475 | ||
| 035 | |a (DE-599)BVBBV021992671 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-706 | ||
| 100 | 1 | |a Vaidya, Avinash Kashinath |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description |c by Avinash Kashinath Vaidya |
| 264 | 1 | |c 1982 | |
| 300 | |a VIII, 246 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Madison, Wis., Univ., Diss., 1982. -Kopie, erschienen im Verl. Univ. Microfilms Internat., Ann Arbor, Mich. | ||
| 650 | 4 | |a Electronic digital computers |x Design and construction | |
| 650 | 4 | |a Logic circuits | |
| 650 | 4 | |a Logic design | |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-015207417 | ||
Datensatz im Suchindex
| _version_ | 1804135968037404672 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Vaidya, Avinash Kashinath |
| author_facet | Vaidya, Avinash Kashinath |
| author_role | aut |
| author_sort | Vaidya, Avinash Kashinath |
| author_variant | a k v ak akv |
| building | Verbundindex |
| bvnumber | BV021992671 |
| ctrlnum | (OCoLC)9169475 (DE-599)BVBBV021992671 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01045nam a2200301zc 4500</leader><controlfield tag="001">BV021992671</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">060120s1982 d||| m||| 00||| eng d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)9169475</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021992671</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Vaidya, Avinash Kashinath</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description</subfield><subfield code="c">by Avinash Kashinath Vaidya</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1982</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">VIII, 246 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Madison, Wis., Univ., Diss., 1982. -Kopie, erschienen im Verl. Univ. Microfilms Internat., Ann Arbor, Mich.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic digital computers</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic circuits</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic design</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-015207417</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV021992671 |
| illustrated | Illustrated |
| index_date | 2024-07-02T16:10:40Z |
| indexdate | 2024-07-09T20:48:55Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015207417 |
| oclc_num | 9169475 |
| open_access_boolean | |
| owner | DE-706 |
| owner_facet | DE-706 |
| physical | VIII, 246 S. graph. Darst. |
| publishDate | 1982 |
| publishDateSearch | 1982 |
| publishDateSort | 1982 |
| record_format | marc |
| spelling | Vaidya, Avinash Kashinath Verfasser aut Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description by Avinash Kashinath Vaidya 1982 VIII, 246 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Madison, Wis., Univ., Diss., 1982. -Kopie, erschienen im Verl. Univ. Microfilms Internat., Ann Arbor, Mich. Electronic digital computers Design and construction Logic circuits Logic design (DE-588)4113937-9 Hochschulschrift gnd-content |
| spellingShingle | Vaidya, Avinash Kashinath Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description Electronic digital computers Design and construction Logic circuits Logic design |
| subject_GND | (DE-588)4113937-9 |
| title | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description |
| title_auth | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description |
| title_exact_search | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description |
| title_exact_search_txtP | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description |
| title_full | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description by Avinash Kashinath Vaidya |
| title_fullStr | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description by Avinash Kashinath Vaidya |
| title_full_unstemmed | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description by Avinash Kashinath Vaidya |
| title_short | Automatic logic synthesis for VLSI gate array implementations of a digital system from a conlan description |
| title_sort | automatic logic synthesis for vlsi gate array implementations of a digital system from a conlan description |
| topic | Electronic digital computers Design and construction Logic circuits Logic design |
| topic_facet | Electronic digital computers Design and construction Logic circuits Logic design Hochschulschrift |
| work_keys_str_mv | AT vaidyaavinashkashinath automaticlogicsynthesisforvlsigatearrayimplementationsofadigitalsystemfromaconlandescription |