Retiming synchronous circuitry:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge, Mass.
Mass. Inst. of Technology, Laboratory for Computer Science
1986
|
| Schlagworte: | |
| Beschreibung: | 30 S. |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV021896322 | ||
| 003 | DE-604 | ||
| 005 | 20040301000000.0 | ||
| 007 | t | ||
| 008 | 910307s1986 |||| 00||| eng d | ||
| 035 | |a (OCoLC)17559335 | ||
| 035 | |a (DE-599)BVBBV021896322 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-706 | ||
| 088 | |a MIT LCS TM 309 | ||
| 100 | 1 | |a Leiserson, Charles E. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Retiming synchronous circuitry |c Charles Leiserson ; James B. Saxe |
| 264 | 1 | |a Cambridge, Mass. |b Mass. Inst. of Technology, Laboratory for Computer Science |c 1986 | |
| 300 | |a 30 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Electronic circuits | |
| 650 | 4 | |a Integrated circuits |x Design and construction | |
| 650 | 0 | 7 | |a Algorithmus |0 (DE-588)4001183-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Graph |0 (DE-588)4021842-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Kombinatorische Optimierung |0 (DE-588)4031826-6 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Algorithmus |0 (DE-588)4001183-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Graph |0 (DE-588)4021842-9 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Kombinatorische Optimierung |0 (DE-588)4031826-6 |D s |
| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Saxe, James B. |e Verfasser |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-015111505 | ||
Datensatz im Suchindex
| _version_ | 1804135841159708672 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Leiserson, Charles E. Saxe, James B. |
| author_facet | Leiserson, Charles E. Saxe, James B. |
| author_role | aut aut |
| author_sort | Leiserson, Charles E. |
| author_variant | c e l ce cel j b s jb jbs |
| building | Verbundindex |
| bvnumber | BV021896322 |
| ctrlnum | (OCoLC)17559335 (DE-599)BVBBV021896322 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01308nam a2200397zc 4500</leader><controlfield tag="001">BV021896322</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20040301000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">910307s1986 |||| 00||| eng d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)17559335</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021896322</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield></datafield><datafield tag="088" ind1=" " ind2=" "><subfield code="a">MIT LCS TM 309</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Leiserson, Charles E.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Retiming synchronous circuitry</subfield><subfield code="c">Charles Leiserson ; James B. Saxe</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge, Mass.</subfield><subfield code="b">Mass. Inst. of Technology, Laboratory for Computer Science</subfield><subfield code="c">1986</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">30 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Algorithmus</subfield><subfield code="0">(DE-588)4001183-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Graph</subfield><subfield code="0">(DE-588)4021842-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Kombinatorische Optimierung</subfield><subfield code="0">(DE-588)4031826-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Algorithmus</subfield><subfield code="0">(DE-588)4001183-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Graph</subfield><subfield code="0">(DE-588)4021842-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Kombinatorische Optimierung</subfield><subfield code="0">(DE-588)4031826-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Saxe, James B.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-015111505</subfield></datafield></record></collection> |
| id | DE-604.BV021896322 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T16:04:23Z |
| indexdate | 2024-07-09T20:46:54Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015111505 |
| oclc_num | 17559335 |
| open_access_boolean | |
| owner | DE-706 |
| owner_facet | DE-706 |
| physical | 30 S. |
| publishDate | 1986 |
| publishDateSearch | 1986 |
| publishDateSort | 1986 |
| publisher | Mass. Inst. of Technology, Laboratory for Computer Science |
| record_format | marc |
| spelling | Leiserson, Charles E. Verfasser aut Retiming synchronous circuitry Charles Leiserson ; James B. Saxe Cambridge, Mass. Mass. Inst. of Technology, Laboratory for Computer Science 1986 30 S. txt rdacontent n rdamedia nc rdacarrier Electronic circuits Integrated circuits Design and construction Algorithmus (DE-588)4001183-5 gnd rswk-swf Graph (DE-588)4021842-9 gnd rswk-swf Kombinatorische Optimierung (DE-588)4031826-6 gnd rswk-swf Algorithmus (DE-588)4001183-5 s DE-604 Graph (DE-588)4021842-9 s Kombinatorische Optimierung (DE-588)4031826-6 s Saxe, James B. Verfasser aut |
| spellingShingle | Leiserson, Charles E. Saxe, James B. Retiming synchronous circuitry Electronic circuits Integrated circuits Design and construction Algorithmus (DE-588)4001183-5 gnd Graph (DE-588)4021842-9 gnd Kombinatorische Optimierung (DE-588)4031826-6 gnd |
| subject_GND | (DE-588)4001183-5 (DE-588)4021842-9 (DE-588)4031826-6 |
| title | Retiming synchronous circuitry |
| title_auth | Retiming synchronous circuitry |
| title_exact_search | Retiming synchronous circuitry |
| title_exact_search_txtP | Retiming synchronous circuitry |
| title_full | Retiming synchronous circuitry Charles Leiserson ; James B. Saxe |
| title_fullStr | Retiming synchronous circuitry Charles Leiserson ; James B. Saxe |
| title_full_unstemmed | Retiming synchronous circuitry Charles Leiserson ; James B. Saxe |
| title_short | Retiming synchronous circuitry |
| title_sort | retiming synchronous circuitry |
| topic | Electronic circuits Integrated circuits Design and construction Algorithmus (DE-588)4001183-5 gnd Graph (DE-588)4021842-9 gnd Kombinatorische Optimierung (DE-588)4031826-6 gnd |
| topic_facet | Electronic circuits Integrated circuits Design and construction Algorithmus Graph Kombinatorische Optimierung |
| work_keys_str_mv | AT leisersoncharlese retimingsynchronouscircuitry AT saxejamesb retimingsynchronouscircuitry |