Layouts for the shuffle-exchange graph and lower bound techniques for VLSI:
The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include (1) an asymptotically optimal, area layout for the N-mode shuffle-exchange graph, and (2) several practical layouts for small shuffle-exchange graph...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge, Mass.
laboratory for Computer Science, Massachusetts Inst. of Technology
1982
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| Schlagworte: | |
| Zusammenfassung: | The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include (1) an asymptotically optimal, area layout for the N-mode shuffle-exchange graph, and (2) several practical layouts for small shuffle-exchange graphs. The new layouts require substantially less area than previously known layouts and can serve as the basis for designing large scale shuffle-exchange chips. In the second part of thee thesis, we develop general methods for proving lower bounds on the layout area, crossing number, bisection width and maximum edge length of VLSI networks. The area results indicate that some graphs with O(s. rt. of N)-separators (and, in particular, some planar graphs) do not have linear-area layouts, thus disproving a popular conjecture. The edge length bounds indicate that the layouts of some networks must have very long wires (possibly as long as the width of the layout). |
| Beschreibung: | Zugl.: Diss., 1981 |
| Beschreibung: | 105 S. |
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| id | DE-604.BV021876381 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T16:03:36Z |
| indexdate | 2024-07-09T20:46:30Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015091997 |
| oclc_num | 227552911 |
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| owner_facet | DE-706 |
| physical | 105 S. |
| publishDate | 1982 |
| publishDateSearch | 1982 |
| publishDateSort | 1982 |
| publisher | laboratory for Computer Science, Massachusetts Inst. of Technology |
| record_format | marc |
| spelling | Leighton, Frank T. Verfasser aut Layouts for the shuffle-exchange graph and lower bound techniques for VLSI Frank Thomson Leighton Cambridge, Mass. laboratory for Computer Science, Massachusetts Inst. of Technology 1982 105 S. txt rdacontent n rdamedia nc rdacarrier Zugl.: Diss., 1981 The thesis is divided into two parts. In the first part, we describe and analyze several new VLSI layouts for the shuffle-exchange graph. These include (1) an asymptotically optimal, area layout for the N-mode shuffle-exchange graph, and (2) several practical layouts for small shuffle-exchange graphs. The new layouts require substantially less area than previously known layouts and can serve as the basis for designing large scale shuffle-exchange chips. In the second part of thee thesis, we develop general methods for proving lower bounds on the layout area, crossing number, bisection width and maximum edge length of VLSI networks. The area results indicate that some graphs with O(s. rt. of N)-separators (and, in particular, some planar graphs) do not have linear-area layouts, thus disproving a popular conjecture. The edge length bounds indicate that the layouts of some networks must have very long wires (possibly as long as the width of the layout). Boundaries dtict Chips(electronics) dtict Circuit interconnections dtict Computations dtict Computer Hardware scgdst Computer architecture dtict Computer logic dtict Electrical and Electronic Equipment scgdst Graphs dtict Grids(coordinates) dtict Integrated circuits dtict Nodes dtict Numerical Mathematics scgdst Parallel processors dtict Theses dtict Transistors dtict Wire dtict Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 s DE-604 |
| spellingShingle | Leighton, Frank T. Layouts for the shuffle-exchange graph and lower bound techniques for VLSI Boundaries dtict Chips(electronics) dtict Circuit interconnections dtict Computations dtict Computer Hardware scgdst Computer architecture dtict Computer logic dtict Electrical and Electronic Equipment scgdst Graphs dtict Grids(coordinates) dtict Integrated circuits dtict Nodes dtict Numerical Mathematics scgdst Parallel processors dtict Theses dtict Transistors dtict Wire dtict Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4179389-4 |
| title | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI |
| title_auth | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI |
| title_exact_search | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI |
| title_exact_search_txtP | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI |
| title_full | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI Frank Thomson Leighton |
| title_fullStr | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI Frank Thomson Leighton |
| title_full_unstemmed | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI Frank Thomson Leighton |
| title_short | Layouts for the shuffle-exchange graph and lower bound techniques for VLSI |
| title_sort | layouts for the shuffle exchange graph and lower bound techniques for vlsi |
| topic | Boundaries dtict Chips(electronics) dtict Circuit interconnections dtict Computations dtict Computer Hardware scgdst Computer architecture dtict Computer logic dtict Electrical and Electronic Equipment scgdst Graphs dtict Grids(coordinates) dtict Integrated circuits dtict Nodes dtict Numerical Mathematics scgdst Parallel processors dtict Theses dtict Transistors dtict Wire dtict Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Boundaries Chips(electronics) Circuit interconnections Computations Computer Hardware Computer architecture Computer logic Electrical and Electronic Equipment Graphs Grids(coordinates) Integrated circuits Nodes Numerical Mathematics Parallel processors Theses Transistors Wire Schaltungsentwurf |
| work_keys_str_mv | AT leightonfrankt layoutsfortheshuffleexchangegraphandlowerboundtechniquesforvlsi |