Artwork analysis tools for VLSI circuits:
Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than try it and see if it works is needed. Checking of...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge, Mass.
Massachusetts Inst. of Technology, Laboratory for Computer Science
1980
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| Schlagworte: | |
| Zusammenfassung: | Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than try it and see if it works is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years. This increase in complexity precludes any manual verification methods; some better method is needed. A series of programs that use the actual mask descriptions for input are described. These programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual 'design rule' checks of looking for minimum line widths and adequate spacing between wires. However, there are many more constraints in VLSI circuits than are expressed by usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain errors are detected. The detection of semantic errors requires various levels of simulation. The input to the simulators is derived from the artwork. |
| Beschreibung: | Zugl.: Diss., 1980 |
| Beschreibung: | 75 Bl. |
Internformat
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| 264 | 1 | |a Cambridge, Mass. |b Massachusetts Inst. of Technology, Laboratory for Computer Science |c 1980 | |
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| 520 | 3 | |a Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than try it and see if it works is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years. This increase in complexity precludes any manual verification methods; some better method is needed. A series of programs that use the actual mask descriptions for input are described. These programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual 'design rule' checks of looking for minimum line widths and adequate spacing between wires. However, there are many more constraints in VLSI circuits than are expressed by usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain errors are detected. The detection of semantic errors requires various levels of simulation. The input to the simulators is derived from the artwork. | |
| 650 | 7 | |a Algorithms |2 dtict | |
| 650 | 7 | |a Chips(electronics) |2 dtict | |
| 650 | 7 | |a Computer aided design |2 dtict | |
| 650 | 7 | |a Computerized simulation |2 dtict | |
| 650 | 7 | |a Electrical and Electronic Equipment |2 scgdst | |
| 650 | 7 | |a Errors |2 dtict | |
| 650 | 7 | |a Fabrication |2 dtict | |
| 650 | 7 | |a Field effect transistors |2 dtict | |
| 650 | 7 | |a Integrated circuits |2 dtict | |
| 650 | 7 | |a Masks |2 dtict | |
| 650 | 7 | |a Nand gates |2 dtict | |
| 650 | 7 | |a Nodes |2 dtict | |
| 650 | 7 | |a Nor gates |2 dtict | |
| 650 | 7 | |a Solid State Physics |2 scgdst | |
| 650 | 7 | |a Theses |2 dtict | |
| 650 | 7 | |a Visual inspection |2 dtict | |
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Datensatz im Suchindex
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| author | Baker, Clark M. |
| author_facet | Baker, Clark M. |
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| author_sort | Baker, Clark M. |
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| building | Verbundindex |
| bvnumber | BV021876322 |
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| id | DE-604.BV021876322 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T16:03:36Z |
| indexdate | 2024-07-09T20:46:30Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015091942 |
| oclc_num | 227454152 |
| open_access_boolean | |
| owner | DE-706 |
| owner_facet | DE-706 |
| physical | 75 Bl. |
| publishDate | 1980 |
| publishDateSearch | 1980 |
| publishDateSort | 1980 |
| publisher | Massachusetts Inst. of Technology, Laboratory for Computer Science |
| record_format | marc |
| spelling | Baker, Clark M. Verfasser aut Artwork analysis tools for VLSI circuits by Clark Marshall Baker Cambridge, Mass. Massachusetts Inst. of Technology, Laboratory for Computer Science 1980 75 Bl. txt rdacontent n rdamedia nc rdacarrier Zugl.: Diss., 1980 Current methods of designing Very Large Scale Integrated (VLSI) chips do not insure that the chips will perform correctly when manufactured. Because the turnaround time on chip fabrication varies from a few weeks to a few months, a scheme other than try it and see if it works is needed. Checking of chips by hand simulation and visual inspection of checkplots will not catch all of the errors. In addition, the number of transistors per chip is likely to increase from ten thousand to over a million in the next few years. This increase in complexity precludes any manual verification methods; some better method is needed. A series of programs that use the actual mask descriptions for input are described. These programs perform various levels of checks on the masks, yielding files suitable for simulation. Some of the checks are the usual 'design rule' checks of looking for minimum line widths and adequate spacing between wires. However, there are many more constraints in VLSI circuits than are expressed by usual design rules. The programs check these constraints using the mask descriptions as input. All of the errors mentioned so far can be classified as syntactic errors; in addition, certain errors are detected. The detection of semantic errors requires various levels of simulation. The input to the simulators is derived from the artwork. Algorithms dtict Chips(electronics) dtict Computer aided design dtict Computerized simulation dtict Electrical and Electronic Equipment scgdst Errors dtict Fabrication dtict Field effect transistors dtict Integrated circuits dtict Masks dtict Nand gates dtict Nodes dtict Nor gates dtict Solid State Physics scgdst Theses dtict Visual inspection dtict Zuverlässigkeit (DE-588)4059245-5 gnd rswk-swf Fehlersuche (DE-588)4016615-6 gnd rswk-swf Fehlersuche (DE-588)4016615-6 s DE-604 Zuverlässigkeit (DE-588)4059245-5 s |
| spellingShingle | Baker, Clark M. Artwork analysis tools for VLSI circuits Algorithms dtict Chips(electronics) dtict Computer aided design dtict Computerized simulation dtict Electrical and Electronic Equipment scgdst Errors dtict Fabrication dtict Field effect transistors dtict Integrated circuits dtict Masks dtict Nand gates dtict Nodes dtict Nor gates dtict Solid State Physics scgdst Theses dtict Visual inspection dtict Zuverlässigkeit (DE-588)4059245-5 gnd Fehlersuche (DE-588)4016615-6 gnd |
| subject_GND | (DE-588)4059245-5 (DE-588)4016615-6 |
| title | Artwork analysis tools for VLSI circuits |
| title_auth | Artwork analysis tools for VLSI circuits |
| title_exact_search | Artwork analysis tools for VLSI circuits |
| title_exact_search_txtP | Artwork analysis tools for VLSI circuits |
| title_full | Artwork analysis tools for VLSI circuits by Clark Marshall Baker |
| title_fullStr | Artwork analysis tools for VLSI circuits by Clark Marshall Baker |
| title_full_unstemmed | Artwork analysis tools for VLSI circuits by Clark Marshall Baker |
| title_short | Artwork analysis tools for VLSI circuits |
| title_sort | artwork analysis tools for vlsi circuits |
| topic | Algorithms dtict Chips(electronics) dtict Computer aided design dtict Computerized simulation dtict Electrical and Electronic Equipment scgdst Errors dtict Fabrication dtict Field effect transistors dtict Integrated circuits dtict Masks dtict Nand gates dtict Nodes dtict Nor gates dtict Solid State Physics scgdst Theses dtict Visual inspection dtict Zuverlässigkeit (DE-588)4059245-5 gnd Fehlersuche (DE-588)4016615-6 gnd |
| topic_facet | Algorithms Chips(electronics) Computer aided design Computerized simulation Electrical and Electronic Equipment Errors Fabrication Field effect transistors Integrated circuits Masks Nand gates Nodes Nor gates Solid State Physics Theses Visual inspection Zuverlässigkeit Fehlersuche |
| work_keys_str_mv | AT bakerclarkm artworkanalysistoolsforvlsicircuits |