The hierarchical analysis of VLSI designs:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
1984
|
| Schlagworte: | |
| Beschreibung: | New York, N.Y., Univ., Diss., 1983 |
| Beschreibung: | II, 170 S. |
Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV021875819 | ||
| 003 | DE-604 | ||
| 005 | 20040229000000.0 | ||
| 007 | t | ||
| 008 | 880219s1984 |||| 00||| und d | ||
| 035 | |a (OCoLC)634018740 | ||
| 035 | |a (DE-599)BVBBV021875819 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | |a und | ||
| 049 | |a DE-706 | ||
| 100 | 1 | |a Hon, Robert W. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a The hierarchical analysis of VLSI designs |
| 264 | 1 | |c 1984 | |
| 300 | |a II, 170 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a New York, N.Y., Univ., Diss., 1983 | ||
| 650 | 0 | 7 | |a Hierarchisches System |0 (DE-588)4159833-7 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Verifikation |0 (DE-588)4135577-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Analyse |0 (DE-588)4122795-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Analyse |0 (DE-588)4122795-5 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Verifikation |0 (DE-588)4135577-5 |D s |
| 689 | 2 | |5 DE-604 | |
| 689 | 3 | 0 | |a Hierarchisches System |0 (DE-588)4159833-7 |D s |
| 689 | 3 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-015091463 | ||
Datensatz im Suchindex
| _version_ | 1804135815170752512 |
|---|---|
| adam_txt | |
| any_adam_object | |
| any_adam_object_boolean | |
| author | Hon, Robert W. |
| author_facet | Hon, Robert W. |
| author_role | aut |
| author_sort | Hon, Robert W. |
| author_variant | r w h rw rwh |
| building | Verbundindex |
| bvnumber | BV021875819 |
| ctrlnum | (OCoLC)634018740 (DE-599)BVBBV021875819 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01200nam a2200397zc 4500</leader><controlfield tag="001">BV021875819</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20040229000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">880219s1984 |||| 00||| und d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)634018740</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV021875819</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Hon, Robert W.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">The hierarchical analysis of VLSI designs</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1984</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">II, 170 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">New York, N.Y., Univ., Diss., 1983</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Hierarchisches System</subfield><subfield code="0">(DE-588)4159833-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Verifikation</subfield><subfield code="0">(DE-588)4135577-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Analyse</subfield><subfield code="0">(DE-588)4122795-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Analyse</subfield><subfield code="0">(DE-588)4122795-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Verifikation</subfield><subfield code="0">(DE-588)4135577-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Hierarchisches System</subfield><subfield code="0">(DE-588)4159833-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-015091463</subfield></datafield></record></collection> |
| id | DE-604.BV021875819 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T16:03:35Z |
| indexdate | 2024-07-09T20:46:30Z |
| institution | BVB |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015091463 |
| oclc_num | 634018740 |
| open_access_boolean | |
| owner | DE-706 |
| owner_facet | DE-706 |
| physical | II, 170 S. |
| publishDate | 1984 |
| publishDateSearch | 1984 |
| publishDateSort | 1984 |
| record_format | marc |
| spelling | Hon, Robert W. Verfasser aut The hierarchical analysis of VLSI designs 1984 II, 170 S. txt rdacontent n rdamedia nc rdacarrier New York, N.Y., Univ., Diss., 1983 Hierarchisches System (DE-588)4159833-7 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Verifikation (DE-588)4135577-5 gnd rswk-swf Analyse (DE-588)4122795-5 gnd rswk-swf VLSI (DE-588)4117388-0 s DE-604 Analyse (DE-588)4122795-5 s Verifikation (DE-588)4135577-5 s Hierarchisches System (DE-588)4159833-7 s |
| spellingShingle | Hon, Robert W. The hierarchical analysis of VLSI designs Hierarchisches System (DE-588)4159833-7 gnd VLSI (DE-588)4117388-0 gnd Verifikation (DE-588)4135577-5 gnd Analyse (DE-588)4122795-5 gnd |
| subject_GND | (DE-588)4159833-7 (DE-588)4117388-0 (DE-588)4135577-5 (DE-588)4122795-5 |
| title | The hierarchical analysis of VLSI designs |
| title_auth | The hierarchical analysis of VLSI designs |
| title_exact_search | The hierarchical analysis of VLSI designs |
| title_exact_search_txtP | The hierarchical analysis of VLSI designs |
| title_full | The hierarchical analysis of VLSI designs |
| title_fullStr | The hierarchical analysis of VLSI designs |
| title_full_unstemmed | The hierarchical analysis of VLSI designs |
| title_short | The hierarchical analysis of VLSI designs |
| title_sort | the hierarchical analysis of vlsi designs |
| topic | Hierarchisches System (DE-588)4159833-7 gnd VLSI (DE-588)4117388-0 gnd Verifikation (DE-588)4135577-5 gnd Analyse (DE-588)4122795-5 gnd |
| topic_facet | Hierarchisches System VLSI Verifikation Analyse |
| work_keys_str_mv | AT honrobertw thehierarchicalanalysisofvlsidesigns |