Low-power deep sub-micron CMOS logic: sub-threshold current reduction
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston, Mass. [u.a.]
Kluwer, Acad. Publ.
2004
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
841 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIV, 154 S. graph. Darst. |
| ISBN: | 1402028482 1402028490 |
Internformat
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Datensatz im Suchindex
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| adam_text | LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION BY
P.R. VAN DER MEER DELFT UNIVERSITY OF TECHNOLOGY. DELFT, THE NETHERLANDS
AND A. VAN STAVEREN NATIONAL SEMICONDUCTOR CORPORATION, DELFT, THE
NETHERLANDS AND A.H.M. VAN ROENNUND EINDHO VEN 11 N I VE RS ILY OF TECHN
OLOGY, EINDHOVEN, THE NETHERLANDS KLUWER ACADEMIC PUBLISHERS BOSTON /
DORDRECHT / LONDON CONTENTS INDEX OF SYMBOLS IX 1. INTRODUCTION 1 1.1
POWER-DISSIPATION TRENDS IN CMOS CIRCUITS 1 1.2 OVERVIEW OF PRESENT
POWER-REDUCTION SOLUTIONS 2 1.3 AIM AND SCOPE OF THIS BOOK 3 1.4
ORGANIZATION OFTHE BOOK 4 2. POWER VERSUS ENERGY 5 2.1 POWER
CONSIDERATIONS 5 2.2 ENERGY CONSIDERATIONS 8 2.3 CONCLUSIONS 9 3. POWER
DISSIPATION IN DIGITAL CMOS CIRCUITS 11 3.1 THERTNODYNAMICS OF
COMPUTATION 13 3.1.1 FUNDAMENTAL LIMITS OF POWER DISSIPATION 14 3.1.2
THERMODYNAMIC LAWS 17 3.2 FUNCTIONAL POWER DISSIPATION 19 3.3
PARASITICAL POWER DISSIPATION 22 3.3.1 LEAK AGE POWER DI S S IPATION 24
3.3.1.1 CHANNEL LEAKAGE CURRENT 24 3.3.1.2 DIODE LEAKAGE CURRENT 38
3.3.1.3 GATE LEAKAGE CURRENT 42 3.3.2 SHORT-CIRCUIT POWER DISSIPATION 45
3.4 TRENDS IN POWER DISSIPATION 48 3.5 CONCLUSIONS 49 V VI CONTENTS 4.
REDUCTION OF FUNCTIONAL POWER DTSSTPATTON 53 4.1 NODE TRANSITION-CYCLE
ACTIVITY FACTOR 53 4.2 CLOCK FREQUENCY 54 4.3 TRANSITION-CYCLE ENERGY 54
4.3.1 REVERSIBILITY FACTOR 57 4.3.1.1 RAMP-WISE CHARGING 59 4.3.1.2
STEP-WISE CHARGING 61 4.3.1.3 RESONANT CHARGING 63 4.3.2 LOAD
CAPACITANCE 68 4.3.3 VOTTAGE SWING 69 4.3.3.1 STATIC VOLTAGE SCALING 70
4.3.3.2 DYNAMIC VOLTAGE SCALING 72 4.4 CONCLUSIONS 75 5. REDUCTION OF
PARASITICAL POWER DISSTPATTON 77 5.1 LEAKAGE POWER DISSIPATION 77 5.1.1
CHANNEL LEAKAGE CURRENT 78 5.1.1.1 WEAK-INVERSION CURRENT 78 5.1.1.2
DRAIN-INDUCED BARRIER LOWERING CURRENT 80 5.1.1.3 CHANNEL EDGE CURRENT
81 5.1.2 DIODE LEAKAGE CURRENT 83 5.1.2.1 REVERSE BIAS LEAKAGE 83
5.1.2.2 GATE-INDUCED DRAIN LEAKAGE 84 5.1.3 GATE LEAKAGE CURRENT 85 5.2
SHORT-CIRCUIT POWER DISSIPATION 89 5.3 NEED FOR WEAK-INVERSION CURRENT
REDUCTION 90 5.4 CONCLUSIONS 91 6. WEAK-INVERSION CURRENT REDUCTION 93
6.1 CLASSIFICATION 93 6.1.1 POWER REDUCTION WITH STATE RETENTION 94
6.1.1.1 STORAGE IN INTRINSICALLY LOW-LEAKAGE MEMORY 95 6.1.1.2 SUBSTRATE
BIASING 96 6.1.1.3 SOURCE AND GATE BIASING 97 6.1.1.4 FIXED HIGH
THRESHOLD VOLTAGE 99 6.1.1.5 TRIPLE-S TECHNIQUE 100 6.1.2 POWER
REDUCTION WITHOUT STATE RETENTION 102 6.2 CONCLUSIONS 104 VLL 7.
EFFECTIVENESS OF WE AK-INVERSION CURRENT REDUCTION 105 7.1 GENERAL
EFFECTIVENESS 105 7.1.1 IDEAL CASE 106 7.1.2 DISSIPATION OF STORED
ENERGY 107 7.1.3 OVERHEAD COSTS 108 7.2 TECHNIQUE-SPECIFIC EFFECTIVENESS
111 7.2.1 EFFECTIVENESS OF SUBSTRATE BIASING 111 7.2.2 EFFECTIVENESS OF
SOURCE AND GATE BIASING 113 7.2.3 EFFECTIVENESS OF THE TRIPLE-S
TECHNIQUE 117 7.3 CONCLUSIONS 120 8. TRIPLE-S CIRCUIT DESIGNS 121 8.1
PROCESS FLOW 121 8.2 EXPERIMENTAL CIRCUITS 123 8.3 LEAKAGE, SPEED, AREA
AND FUNCTIONAL POWER 125 8.3.1 LEAKAGE 126 8.3.2 SPEED 129 8.3.3 AREA
131 8.3.4 FUNCTIONAL POWER 132 8.4 PRACTICAL APPLICATIONS AND
LIMITATIONS 135 8.5 CONCLUSIONS 137 9. CONCLUSIONS 139 10. S UMMARY 141
REFERENCES 145 INDEX 151
|
| adam_txt |
LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION BY
P.R. VAN DER MEER DELFT UNIVERSITY OF TECHNOLOGY. DELFT, THE NETHERLANDS
AND A. VAN STAVEREN NATIONAL SEMICONDUCTOR CORPORATION, DELFT, THE
NETHERLANDS AND A.H.M. VAN ROENNUND EINDHO VEN 11 N I VE RS ILY OF TECHN
OLOGY, EINDHOVEN, THE NETHERLANDS KLUWER ACADEMIC PUBLISHERS BOSTON /
DORDRECHT / LONDON CONTENTS INDEX OF SYMBOLS IX 1. INTRODUCTION 1 1.1
POWER-DISSIPATION TRENDS IN CMOS CIRCUITS 1 1.2 OVERVIEW OF PRESENT
POWER-REDUCTION SOLUTIONS 2 1.3 AIM AND SCOPE OF THIS BOOK 3 1.4
ORGANIZATION OFTHE BOOK 4 2. POWER VERSUS ENERGY 5 2.1 POWER
CONSIDERATIONS 5 2.2 ENERGY CONSIDERATIONS 8 2.3 CONCLUSIONS 9 3. POWER
DISSIPATION IN DIGITAL CMOS CIRCUITS 11 3.1 THERTNODYNAMICS OF
COMPUTATION 13 3.1.1 FUNDAMENTAL LIMITS OF POWER DISSIPATION 14 3.1.2
THERMODYNAMIC LAWS 17 3.2 FUNCTIONAL POWER DISSIPATION 19 3.3
PARASITICAL POWER DISSIPATION 22 3.3.1 LEAK AGE POWER DI S S IPATION 24
3.3.1.1 CHANNEL LEAKAGE CURRENT 24 3.3.1.2 DIODE LEAKAGE CURRENT 38
3.3.1.3 GATE LEAKAGE CURRENT 42 3.3.2 SHORT-CIRCUIT POWER DISSIPATION 45
3.4 TRENDS IN POWER DISSIPATION 48 3.5 CONCLUSIONS 49 V VI CONTENTS 4.
REDUCTION OF FUNCTIONAL POWER DTSSTPATTON 53 4.1 NODE TRANSITION-CYCLE
ACTIVITY FACTOR 53 4.2 CLOCK FREQUENCY 54 4.3 TRANSITION-CYCLE ENERGY 54
4.3.1 REVERSIBILITY FACTOR 57 4.3.1.1 RAMP-WISE CHARGING 59 4.3.1.2
STEP-WISE CHARGING 61 4.3.1.3 RESONANT CHARGING 63 4.3.2 LOAD
CAPACITANCE 68 4.3.3 VOTTAGE SWING 69 4.3.3.1 STATIC VOLTAGE SCALING 70
4.3.3.2 DYNAMIC VOLTAGE SCALING 72 4.4 CONCLUSIONS 75 5. REDUCTION OF
PARASITICAL POWER DISSTPATTON 77 5.1 LEAKAGE POWER DISSIPATION 77 5.1.1
CHANNEL LEAKAGE CURRENT 78 5.1.1.1 WEAK-INVERSION CURRENT 78 5.1.1.2
DRAIN-INDUCED BARRIER LOWERING CURRENT 80 5.1.1.3 CHANNEL EDGE CURRENT
81 5.1.2 DIODE LEAKAGE CURRENT 83 5.1.2.1 REVERSE BIAS LEAKAGE 83
5.1.2.2 GATE-INDUCED DRAIN LEAKAGE 84 5.1.3 GATE LEAKAGE CURRENT 85 5.2
SHORT-CIRCUIT POWER DISSIPATION 89 5.3 NEED FOR WEAK-INVERSION CURRENT
REDUCTION 90 5.4 CONCLUSIONS 91 6. WEAK-INVERSION CURRENT REDUCTION 93
6.1 CLASSIFICATION 93 6.1.1 POWER REDUCTION WITH STATE RETENTION 94
6.1.1.1 STORAGE IN INTRINSICALLY LOW-LEAKAGE MEMORY 95 6.1.1.2 SUBSTRATE
BIASING 96 6.1.1.3 SOURCE AND GATE BIASING 97 6.1.1.4 FIXED HIGH
THRESHOLD VOLTAGE 99 6.1.1.5 TRIPLE-S TECHNIQUE 100 6.1.2 POWER
REDUCTION WITHOUT STATE RETENTION 102 6.2 CONCLUSIONS 104 VLL 7.
EFFECTIVENESS OF WE AK-INVERSION CURRENT REDUCTION 105 7.1 GENERAL
EFFECTIVENESS 105 7.1.1 IDEAL CASE 106 7.1.2 DISSIPATION OF STORED
ENERGY 107 7.1.3 OVERHEAD COSTS 108 7.2 TECHNIQUE-SPECIFIC EFFECTIVENESS
111 7.2.1 EFFECTIVENESS OF SUBSTRATE BIASING 111 7.2.2 EFFECTIVENESS OF
SOURCE AND GATE BIASING 113 7.2.3 EFFECTIVENESS OF THE TRIPLE-S
TECHNIQUE 117 7.3 CONCLUSIONS 120 8. TRIPLE-S CIRCUIT DESIGNS 121 8.1
PROCESS FLOW 121 8.2 EXPERIMENTAL CIRCUITS 123 8.3 LEAKAGE, SPEED, AREA
AND FUNCTIONAL POWER 125 8.3.1 LEAKAGE 126 8.3.2 SPEED 129 8.3.3 AREA
131 8.3.4 FUNCTIONAL POWER 132 8.4 PRACTICAL APPLICATIONS AND
LIMITATIONS 135 8.5 CONCLUSIONS 137 9. CONCLUSIONS 139 10. S UMMARY 141
REFERENCES 145 INDEX 151 |
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| spelling | Meer, Paul Robert van der Verfasser aut Low-power deep sub-micron CMOS logic sub-threshold current reduction by P. R. van der Meer and A. van Staveren and A. H. M. van Roermund Boston, Mass. [u.a.] Kluwer, Acad. Publ. 2004 XIV, 154 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 841 Low voltage integrated circuits Design Metal oxide semiconductors, Complementary CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf 1\p (DE-588)4113937-9 Hochschulschrift gnd-content CMOS-Schaltung (DE-588)4148111-2 s DE-604 Staveren, Arie van Verfasser aut Roermund, Arthur H. M. van 1951- Verfasser (DE-588)142689297 aut GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721930&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Meer, Paul Robert van der Staveren, Arie van Roermund, Arthur H. M. van 1951- Low-power deep sub-micron CMOS logic sub-threshold current reduction Low voltage integrated circuits Design Metal oxide semiconductors, Complementary CMOS-Schaltung (DE-588)4148111-2 gnd |
| subject_GND | (DE-588)4148111-2 (DE-588)4113937-9 |
| title | Low-power deep sub-micron CMOS logic sub-threshold current reduction |
| title_auth | Low-power deep sub-micron CMOS logic sub-threshold current reduction |
| title_exact_search | Low-power deep sub-micron CMOS logic sub-threshold current reduction |
| title_exact_search_txtP | Low-power deep sub-micron CMOS logic sub-threshold current reduction |
| title_full | Low-power deep sub-micron CMOS logic sub-threshold current reduction by P. R. van der Meer and A. van Staveren and A. H. M. van Roermund |
| title_fullStr | Low-power deep sub-micron CMOS logic sub-threshold current reduction by P. R. van der Meer and A. van Staveren and A. H. M. van Roermund |
| title_full_unstemmed | Low-power deep sub-micron CMOS logic sub-threshold current reduction by P. R. van der Meer and A. van Staveren and A. H. M. van Roermund |
| title_short | Low-power deep sub-micron CMOS logic |
| title_sort | low power deep sub micron cmos logic sub threshold current reduction |
| title_sub | sub-threshold current reduction |
| topic | Low voltage integrated circuits Design Metal oxide semiconductors, Complementary CMOS-Schaltung (DE-588)4148111-2 gnd |
| topic_facet | Low voltage integrated circuits Design Metal oxide semiconductors, Complementary CMOS-Schaltung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721930&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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