A designer's guide to built-in self-test:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Boston [u.a.]
Kluwer
2002
|
| Series: | Frontiers in electronic testing
|
| Subjects: | |
| Online Access: | Table of contents Inhaltsverzeichnis |
| Physical Description: | XVI, 319 S. Ill. |
| ISBN: | 1402070500 |
Staff View
MARC
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| adam_text | Table of Contents
Preface xi
Aboutthe Author xv
1 An Overview of BIST 1
1.1 An Overview of Testing 1
/././ Pmduct Development and Design Verification 2
1.1.2 Manufacturing Test 4
1.1.3 System Operation 6
1.1.4 The Testing Problem 7
1.2 What Is BIST? How Does It Work? 8
1.2.1 Basic BIST Architecture 9
1.2.2 A Simple BIST Design 10
1.3 Advantages and Disadvantages of BIST 12
2 Fault Models, Detection, and Simulation 15
2.1 Testing and Fault Simulation 15
2.2 Fault Models and Detection 18
A Designer s Guide to Built In Self Test
2.2.1 Gate Level Stuck At Fault Model 18
2.2.2 Transistor Level Stuck Fault Model 20
2.2.3 Bridging Fault Models 23
2.2.4 DelayFaults 26
2.2.5 Single vs. Multiple Fault Models 27
2.2.6 Equivalent Faults and Fault Collapsing 27
2.2.7 Bridging Fault Extraction 30
2.2.8 Statistical FaultSampling 32
2.3 Fault Detection and Fault Coverage 33
2.3.1 Controllability and Observability 33
2.3.2 Path Sensitization 34
2.3.3 Undetectable Faults 35
2.3.4 PotentiallyDetectedFaults 38
2.3.5 Fault Coverage 39
2.3.6 N Detectability 41
3 Design for Testability 43
3.1 Overview of Design for Testability 43
3.2 Ad Hoc Techniques 45
3.3 Scan Design Techniques 48
3.3.1 Multiple Scan Chains 52
3.3.2 Partial Scan Design 52
3.4 Boundary Scan 53
3.5 BIST 56
3.6 Evaluation Criteria for DFT Approaches 57
4 Test Pattern Generation 61
4.1 TypesofTestPatterns 61
4.2 Counters 63
4.3 Finite State Machines 63
4.4 Linear Feedback Shift Registers 65
4.4.1 Primitive Polynomials 67
4.4.2 Producing theAll Os Pattern 70
4.4.3 Reciprocal Polynomial 7/
4.5 Cellular Automata 72
4.6 Weighted Pseudo Random Test Patterns 75
vi
Table of Contents
4.7 OtherTPGs 77
4.8 Comparing TPGs 79
5 Output Response Analysis 81
5.1 Types of Output Data Compaction 81
5.2 Concentrators 83
5.3 Comparators 84
5.4 Counting Techniques 86
5.5 Signature Analysis 88
5.6 Accumulators 94
5.7 Parity Check 95
5.8 Fault Simulation Considerations 96
5.9 Comparing ORAs 97
5.10 Summary of Methods to Reduce Aliasing 100
6 Manufacturing and System Level Use of BIST 101
6.1 Manufacturing Use of BIST 101
6.1.1 Collapsed Vectors Sets 101
6.1.2 Low CoslATE 103
6.1.3 Burn In Testing 104
6.1.4 Otherlssues 105
6.2 System Level Use of BIST 105
6.2.1 Requirements for System Level Use ofBIST 106
6.2.2 Input Isolation 108
6.2.3 Test Controller 110
6.2.4 Design Verification ofBIST ///
6.2.5 Effective Fault Coverage 113
6.2.6 Diagnostic Evaluation 114
6.2.7 Multiple BISTSessions 114
6.3 General BIST Architectures 116
6.4 Overview ofBIST Design Process 118
6.5 The Clock Enable Problem 119
vii
A Designer s Guide to Built In Self Test
7 Built In Logic Block Observer 121
7.1 BILBO Architecture 121
7.2 BILBO Operation 125
7.3 Test Session Scheduling 126
7.4 BIST Controller 128
7.5 Concurrent BILBO 129
7.6 Benefits and Limitations 132
8 Pseudo Exhaustive BIST 137
8.1 Autonomous Test 137
8.2 Hardware Partitioning 139
8.3 Pseudo Exhaustive Self Test 141
8.4 Sensitized Partitioning 143
8.5 Test Point Insertion 146
8.6 Benefits and Limitations 147
9 Circular BIST 149
9.1 Circuiar BIST Architecture 149
9.2 Circular BIST Operation 153
9.3 BIST Controller 156
9.4 Selective Replacement of Flip Flops 157
9.5 Register Adjacency 160
9.6 Limit Cycling 161
9.6.1 Design Guidelines for Limit Cycling 162
9.6.2 Hardware Solutions to Limit Cycling 164
9.7 Benefits and Limitations 168
10 Scan Based BIST 169
10.1 Scan BIST Architectures and Operation 169
10.1.1 The First Scan BIST? 173
10.1.2 Random Test Socket 174
10.1.3 STUMPS 176
10.2 Linear and Structural Dependencies 177
viii
Table of Contents
10.2.1 Structural Dependencies 177
10.2.2 Linear Dependencies 179
10.3 Linear and Structural Dependency Solutions 181
10.3.1 Reseeding LFSRs and Multiple Polynomiah 181
10.3.2 Bit Manipulation 182
10.3.3 Test Point Insertion 183
10.3.4 Phase Shifters 184
10.3.5 Multiple Capture Cycles andPartialScan 188
10.4 Benefits and Limitations 189
11 Non Intrusive BIST 191
11.1 Non Intrusive BIST Architectures 191
11.1.1 Board Level Implementations 192
11.1.2 Device Level Implementations 195
11.1.3 System Level Implementations 197
11.1.4 Vertical Testability Implementations 199
11.2 Benefits and Limitations 204
11.3 The Clock Enable Problem Revisited 206
12 BIST for Regulär Structures 207
12.1 Regulär Structure Fault Models 208
12.2 RAM BIST Architectures 210
12.3 ROM and PLA BIST Architectures 215
12.4 Bypassing Regulär Structures During BIST 218
12.5 Benefits and Limitations 219
13 BIST for FPGAs and CPLDs 221
13.1 Overviewof FPGAs and CPLDs 222
13.2 Logic BIST Architectures 225
13.2.1 LUT/RAM based PLBs 228
13.2.2 Fully Programmable OR Plane PLA basedPLBs 229
13.2.3 Partially Programmable OR Plane PLA based PLBs 233
13.3 Interconnect BIST Architectures 236
13.4 Boundary Scan Access to BIST 240
13.4.1 Using Existing Boundary Scan Cells 241
ix
A Designer s Guide to Built In Self Test
13.4.2 Configuration Memory Readback 242
13.4.3 User Defmed Scan Chain 243
13.5 On LineBIST 244
13.6 Benefits and Limitations 248
14 Applying Digital BIST to Mixed Signal Systems..251
14.1 Mixed Signal BIST Architecture 252
14.1.1 TPGsfor Mixed Signal BIST 254
14.1.2 ORAsfor Mixed Signal BIST. 258
14.2 Mixed Signal BIST Operation 259
14.3 AnalysisofBISTApproach 261
14.3.1 Benchmark Circuits 262
14.3.2 Fault Simulation Results 263
14.4 Benefits and Limitations 265
15 Merging BIST and Concurrent Fault Detection...267
15.1 System UseofCFDCs 268
15.2 OverviewofCFDCs 271
15.2.1 Parity Circuits 271
15.2.2 Cyclic Redundancy Check (CRC) Circuits 272
15.2.3 Checksum Circuits 274
15.2.4 Hamming Circuits 275
15.2.5 Berger and Böse Lin Circuits 278
15.2.6 Comparing CFDCs 279
15.3 Using CFDCs for Off Line BIST 280
15.4 On Line BIST Approaches 284
15.5 Benefits and Limitations 286
Acronyms 287
Bibliography 291
Index 313
x
|
| adam_txt |
Table of Contents
Preface xi
Aboutthe Author xv
1 An Overview of BIST 1
1.1 An Overview of Testing 1
/././ Pmduct Development and Design Verification 2
1.1.2 Manufacturing Test 4
1.1.3 System Operation 6
1.1.4 The Testing Problem 7
1.2 What Is BIST? How Does It Work? 8
1.2.1 Basic BIST Architecture 9
1.2.2 A Simple BIST Design 10
1.3 Advantages and Disadvantages of BIST 12
2 Fault Models, Detection, and Simulation 15
2.1 Testing and Fault Simulation 15
2.2 Fault Models and Detection 18
A Designer's Guide to Built In Self Test
2.2.1 Gate Level Stuck At Fault Model 18
2.2.2 Transistor Level Stuck Fault Model 20
2.2.3 Bridging Fault Models 23
2.2.4 DelayFaults 26
2.2.5 Single vs. Multiple Fault Models 27
2.2.6 Equivalent Faults and Fault Collapsing 27
2.2.7 Bridging Fault Extraction 30
2.2.8 Statistical FaultSampling 32
2.3 Fault Detection and Fault Coverage 33
2.3.1 Controllability and Observability 33
2.3.2 Path Sensitization 34
2.3.3 Undetectable Faults 35
2.3.4 PotentiallyDetectedFaults 38
2.3.5 Fault Coverage 39
2.3.6 N Detectability 41
3 Design for Testability 43
3.1 Overview of Design for Testability 43
3.2 Ad Hoc Techniques 45
3.3 Scan Design Techniques 48
3.3.1 Multiple Scan Chains 52
3.3.2 Partial Scan Design 52
3.4 Boundary Scan 53
3.5 BIST 56
3.6 Evaluation Criteria for DFT Approaches 57
4 Test Pattern Generation 61
4.1 TypesofTestPatterns 61
4.2 Counters 63
4.3 Finite State Machines 63
4.4 Linear Feedback Shift Registers 65
4.4.1 Primitive Polynomials 67
4.4.2 Producing theAll Os Pattern 70
4.4.3 Reciprocal Polynomial 7/
4.5 Cellular Automata 72
4.6 Weighted Pseudo Random Test Patterns 75
vi
Table of Contents
4.7 OtherTPGs 77
4.8 Comparing TPGs 79
5 Output Response Analysis 81
5.1 Types of Output Data Compaction 81
5.2 Concentrators 83
5.3 Comparators 84
5.4 Counting Techniques 86
5.5 Signature Analysis 88
5.6 Accumulators 94
5.7 Parity Check 95
5.8 Fault Simulation Considerations 96
5.9 Comparing ORAs 97
5.10 Summary of Methods to Reduce Aliasing 100
6 Manufacturing and System Level Use of BIST 101
6.1 Manufacturing Use of BIST 101
6.1.1 Collapsed Vectors Sets 101
6.1.2 Low CoslATE 103
6.1.3 Burn In Testing 104
6.1.4 Otherlssues 105
6.2 System Level Use of BIST 105
6.2.1 Requirements for System Level Use ofBIST 106
6.2.2 Input Isolation 108
6.2.3 Test Controller 110
6.2.4 Design Verification ofBIST ///
6.2.5 Effective Fault Coverage 113
6.2.6 Diagnostic Evaluation 114
6.2.7 Multiple BISTSessions 114
6.3 General BIST Architectures 116
6.4 Overview ofBIST Design Process 118
6.5 The Clock Enable Problem 119
vii
A Designer's Guide to Built In Self Test
7 Built In Logic Block Observer 121
7.1 BILBO Architecture 121
7.2 BILBO Operation 125
7.3 Test Session Scheduling 126
7.4 BIST Controller 128
7.5 Concurrent BILBO 129
7.6 Benefits and Limitations 132
8 Pseudo Exhaustive BIST 137
8.1 Autonomous Test 137
8.2 Hardware Partitioning 139
8.3 Pseudo Exhaustive Self Test 141
8.4 Sensitized Partitioning 143
8.5 Test Point Insertion 146
8.6 Benefits and Limitations 147
9 Circular BIST 149
9.1 Circuiar BIST Architecture 149
9.2 Circular BIST Operation 153
9.3 BIST Controller 156
9.4 Selective Replacement of Flip Flops 157
9.5 Register Adjacency 160
9.6 Limit Cycling 161
9.6.1 Design Guidelines for Limit Cycling 162
9.6.2 Hardware Solutions to Limit Cycling 164
9.7 Benefits and Limitations 168
10 Scan Based BIST 169
10.1 Scan BIST Architectures and Operation 169
10.1.1 The First Scan BIST? 173
10.1.2 Random Test Socket 174
10.1.3 STUMPS 176
10.2 Linear and Structural Dependencies 177
viii
Table of Contents
10.2.1 Structural Dependencies 177
10.2.2 Linear Dependencies 179
10.3 Linear and Structural Dependency Solutions 181
10.3.1 Reseeding LFSRs and Multiple Polynomiah 181
10.3.2 Bit Manipulation 182
10.3.3 Test Point Insertion 183
10.3.4 Phase Shifters 184
10.3.5 Multiple Capture Cycles andPartialScan 188
10.4 Benefits and Limitations 189
11 Non Intrusive BIST 191
11.1 Non Intrusive BIST Architectures 191
11.1.1 Board Level Implementations 192
11.1.2 Device Level Implementations 195
11.1.3 System Level Implementations 197
11.1.4 Vertical Testability Implementations 199
11.2 Benefits and Limitations 204
11.3 The Clock Enable Problem Revisited 206
12 BIST for Regulär Structures 207
12.1 Regulär Structure Fault Models 208
12.2 RAM BIST Architectures 210
12.3 ROM and PLA BIST Architectures 215
12.4 Bypassing Regulär Structures During BIST 218
12.5 Benefits and Limitations 219
13 BIST for FPGAs and CPLDs 221
13.1 Overviewof FPGAs and CPLDs 222
13.2 Logic BIST Architectures 225
13.2.1 LUT/RAM based PLBs 228
13.2.2 Fully Programmable OR Plane PLA basedPLBs 229
13.2.3 Partially Programmable OR Plane PLA based PLBs 233
13.3 Interconnect BIST Architectures 236
13.4 Boundary Scan Access to BIST 240
13.4.1 Using Existing Boundary Scan Cells 241
ix
A Designer's Guide to Built In Self Test
13.4.2 Configuration Memory Readback 242
13.4.3 User Defmed Scan Chain 243
13.5 On LineBIST 244
13.6 Benefits and Limitations 248
14 Applying Digital BIST to Mixed Signal Systems.251
14.1 Mixed Signal BIST Architecture 252
14.1.1 TPGsfor Mixed Signal BIST 254
14.1.2 ORAsfor Mixed Signal BIST. 258
14.2 Mixed Signal BIST Operation 259
14.3 AnalysisofBISTApproach 261
14.3.1 Benchmark Circuits 262
14.3.2 Fault Simulation Results 263
14.4 Benefits and Limitations 265
15 Merging BIST and Concurrent Fault Detection.267
15.1 System UseofCFDCs 268
15.2 OverviewofCFDCs 271
15.2.1 Parity Circuits 271
15.2.2 Cyclic Redundancy Check (CRC) Circuits 272
15.2.3 Checksum Circuits 274
15.2.4 Hamming Circuits 275
15.2.5 Berger and Böse Lin Circuits 278
15.2.6 Comparing CFDCs 279
15.3 Using CFDCs for Off Line BIST 280
15.4 On Line BIST Approaches 284
15.5 Benefits and Limitations 286
Acronyms 287
Bibliography 291
Index 313
x |
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| id | DE-604.BV021504576 |
| illustrated | Illustrated |
| index_date | 2024-07-02T14:16:40Z |
| indexdate | 2024-07-09T20:37:19Z |
| institution | BVB |
| isbn | 1402070500 |
| language | English |
| lccn | 2002016230 |
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| physical | XVI, 319 S. Ill. |
| publishDate | 2002 |
| publishDateSearch | 2002 |
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| publisher | Kluwer |
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| series2 | Frontiers in electronic testing |
| spelling | Stroud, Charles E. Verfasser aut A designer's guide to built-in self-test Charles E. Stroud Boston [u.a.] Kluwer 2002 XVI, 319 S. Ill. txt rdacontent n rdamedia nc rdacarrier Frontiers in electronic testing Dispositivos eletrônicos (projeto e construção) larpcal aElectronic apparatus and appliances xTesting aElectronic apparatus and appliances xDesign and construction aAutomatic test equipment Built-in self test (DE-588)4516486-1 gnd rswk-swf Built-in self test (DE-588)4516486-1 s DE-604 http://www.loc.gov/catdir/toc/fy031/2002016230.html Table of contents HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721262&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Stroud, Charles E. A designer's guide to built-in self-test Dispositivos eletrônicos (projeto e construção) larpcal aElectronic apparatus and appliances xTesting aElectronic apparatus and appliances xDesign and construction aAutomatic test equipment Built-in self test (DE-588)4516486-1 gnd |
| subject_GND | (DE-588)4516486-1 |
| title | A designer's guide to built-in self-test |
| title_auth | A designer's guide to built-in self-test |
| title_exact_search | A designer's guide to built-in self-test |
| title_exact_search_txtP | A designer's guide to built-in self-test |
| title_full | A designer's guide to built-in self-test Charles E. Stroud |
| title_fullStr | A designer's guide to built-in self-test Charles E. Stroud |
| title_full_unstemmed | A designer's guide to built-in self-test Charles E. Stroud |
| title_short | A designer's guide to built-in self-test |
| title_sort | a designer s guide to built in self test |
| topic | Dispositivos eletrônicos (projeto e construção) larpcal aElectronic apparatus and appliances xTesting aElectronic apparatus and appliances xDesign and construction aAutomatic test equipment Built-in self test (DE-588)4516486-1 gnd |
| topic_facet | Dispositivos eletrônicos (projeto e construção) aElectronic apparatus and appliances xTesting aElectronic apparatus and appliances xDesign and construction aAutomatic test equipment Built-in self test |
| url | http://www.loc.gov/catdir/toc/fy031/2002016230.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014721262&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT stroudcharlese adesignersguidetobuiltinselftest |