Integrated circuit and system design: power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2005
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| Schriftenreihe: | Lecture notes in computer science
3728 |
| Schlagworte: | |
| Online-Zugang: | Inhaltstext Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XV, 753 S. Ill., graph. Darst. |
| ISBN: | 9783540290131 3540290133 |
Internformat
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| 245 | 1 | 0 | |a Integrated circuit and system design |b power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings |c Vassilis Paliouras ... (eds.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2005 | |
| 300 | |a XV, 753 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 3728 | |
| 500 | |a Literaturangaben | ||
| 650 | 4 | |a Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès | |
| 650 | 4 | |a Conception assistée par ordinateur - Congrès | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer-aided design |v Congresses | |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 2005 |z Löwen |2 gnd-content | |
| 689 | 0 | 0 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Paliouras, Vassilis |e Sonstige |4 oth | |
| 711 | 2 | |a PATMOS |n 15 |d 2005 |c Löwen |j Sonstige |0 (DE-588)10114200-6 |4 oth | |
| 830 | 0 | |a Lecture notes in computer science |v 3728 |w (DE-604)BV000000707 |9 3728 | |
| 856 | 4 | 2 | |q text/html |u http://deposit.dnb.de/cgi-bin/dokserv?id=2672123&prov=M&dok_var=1&dok_ext=htm |3 Inhaltstext |
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Datensatz im Suchindex
| _version_ | 1820874961881923584 |
|---|---|
| adam_text |
Table of Contents
Session
A Power-Efficient and Scalable Load-Store Queue Design
Fernando Castro, Daniel Chaver, Luis Pinuel, Manuel
Michael C. Huang, and Francisco
Power Consumption Reduction Using Dynamic Control
of Micro Processor Performance
David Rios-Arambula,
Low Power Techniques Applied to a 80C51 Microcontroller
for High Temperature Applications
Philippe Manet, David
Dynamic Instruction Cascading on GALS Microprocessors
Hiroshi Sasaki, Masaaki Kondo, andHiroshi Nakamura
Power Reduction of Superscalar Processor Functional Units
by Resizing Adder-Width
Guadalupe
and José Manuel Colmenar
Session
A Retargetable Environment for Power-Aware Code Evaluation:
An Approach Based on Coloured Petti Net
Meuse
Cesar Oliveira, Adilson Arcoverde,
and Leornado Amorin
Designing Low-Power Embedded Software for Mass-Produced Microprocessor
by Using a Loop Table in On-Chip Memory
Rodrigo
Energy Characterization of Garbage Collectors for Dynamic Applications
on Embedded Systems
Jose M. Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor,
Francisco
Optimizing the Configuration of Dynamic Voltage Scaling Points
in
Huizhan Yi andXuejun Yang
X Table of
Session
Systematic Preprocessing of Data Dependent Constructs
for Embedded Systems
Martin Palkovic, Erik Bmckmeyer, P. Vanbroekhoven, Henk
and Francky Catthoor
Temperature Aware Datapath Scheduling
AliManzak
Memory Hierarchy Energy Cost of a Direct Filtering Implementation
of the Wavelet Transform
Bert Geelen,
andDiederik Verkest
Improving the Memory Bandwidth Utilization Using Loop Transformations
Minas Dasygenis,
and
Power-Aware Scheduling for Hard
Using Voltage-Scaling Enabled Architectures
AmjadMohsen and Richard
Session
Design of Digital Filters for Low Power Applications
Using Integer Quadratic Programming
Mustafa Aktan and Giinhan Diindar
A High Level Constant Coefficient Multiplier Power Model
for Power Estimation on High Levels of Abstraction
Arne Schulz,
Axel
An Energy-Tree Based Routing Algorithm
in Wireless Ad-Hoc Network Environments
Hyun Ho Kim, Jung Hee Kim, Yong-hyeog Rang, and Young Ik Eom
Energy-Aware System-on-Chip for
Labros
and Roberto Zcfalon
Low-Power VLSI Architectures for OFDM Transmitters
Based on PAPR Reduction
Th, Giannopoulos and Vassilis Paliouras
Session
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits
JosepRius,
Table of
Power Management for Low-Power Battery Operated Portable Systems
Using Current-Mode Techniques
Jean-Félix
Power Consumption in Reversible Logic Addressed by a Ramp Voltage
Alexis
Leakage and Dynamic Glitch Power Minimization
Using Integer Linear Programming for Vm Assignment and Path Balancing
Yuanlin
Back Annotation in High Speed Asynchronous Design
Pankaj Golani and Peter
Session
Optimization of Reliability and Power Consumption in Systems on a Chip
Tajona
Performance Gains from Partitioning Embedded Applications
in Processor-FPGA SoCs
Michalis D. Galanis, Gregory Dimitroulakos, and
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands
for Low Power SOC Design
Ytci
Power Supply Selective Mapping for Accurate Timing Analysis
Mariagrazia
Session
Switching Sensitive Driver Circuit to Combat Dynamic Delay
in On-Chip Buses
Rosnan
andHannu Tenhunen
PSK Signalling on NoC Buses
Crescenza D'Alessandro,
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding
Ashutosh Chakraborty, Enrico Macii, and Massimo Poncino
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Giorgos Dimitrakopoulos and Dimitris Nikolos
Efficient Simulation of Power/Ground Networks with Package and Vias
Jin Shi, Yici
Xu
Session
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers
for Timing Performance Optimisation
Gregorio
Application of
in SCMOS Gates
Alejandro
Paulino Ruiz
Compact Static Power Model of Complex CMOS Gates
Jose L
Energy Consumption in RC Tree Circuits with Exponential Inputs:
An Analytical Model
Massimo Alioto, Gaetano Palumbo, and Massimo
Statistical Critical Path Analysis Considering Correlations
Yaping Than, Andrzej J. Strojwas, Mahesh Sharma, and David Newmark
Session
A CAD Platform for Sensor Interfaces in Low-Power Applications
Didier
An Integrated Environment for Embedded Hard
with Timing and Energy Constraints
Eduardo
Adilson Arcoverde, Gabriel Ahes Jr.,
and Arthur Bessa
Efficient Post-layout Power-Delay Curve Generation
Miodrag Vujkovic, David Wadkins, and
Power
Radu Zlatanovici and Borivoje
Switching-Activity Directed Clustering Algorithm
for Low Net-Power Implementation of FPGAs
Siobhán
Session
Logic-Level Fast Current Simulation for Digital CMOS Circuits
Paulino Ruiz
Alejandro
Design of Variable Input Delay Gates for Low Dynamic Power
Tezaswi Raja, Vishwani D. Agrawal, and Michael Bushnell
Table of Contents XHt
Two-Phase Clocking and a New Latch Design
for Low-Power Portable Applications
Flavio Carbognani, Felix
and Wolfgang
Power Dissipation Reduction During Synthesis of Two-Level Logic
Based on Probability of Input Vectors Changes
Ireneusz Brzpzowski andAndrzej
Session
Energy-Efficient Value-Based Selective Refresh for Embedded
K.
Design and Implementation of a Memory Generator
for Low-Energy Application-Specific Block-Enabled SRAMs
Prassanna
Static Noise Margin Analysis of Sub-threshold SRAM Cells
in Deep Sub-micron Technology
Armin Wellig
An Adaptive Technique for Reducing Leakage and Dynamic Power
in Register Files and Reorder Buffers
Shadi T. Khasawneh and Kanad Ghose
Parameter Variation Effects on Timing Characteristics
of High Performance Clocked Registers
William R. Roberts and Dimitrios Velenis
Poster Session
Low-Power Aspects of Nonlinear Signal Processing
Konstantina
Reducing Energy Consumption of Computer Display
by Camera-Based User Monitoring
Vastly G. Moshnyaga andEiji Morikawa
Controlling Peak Power Consumption During Scan Testing:
Power-Aware DfT and Test Set Perspectives
Nabu
and Christian Landrault
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic
François
and
XIV Table of Contents
Power Consumption Characterisation
of me Texas tostramentsTMS320VC5510 DSP
Miguel Casas-Sanchez, Jose Rizo-Morente, and Chris J. Bleakley
A Method to Design Compact Dual-rail Asynchronous Primitives
¿din Razqfindraibe, Michel Robert, Marc Renaudin, and Philippe Maurine
Enhanced GALS Techniques for Datapath Applications
Eckhard
Christian
Optimizing SHA-1 Hash Function for High Throughput
with a Partial Unrolling Study
U.E. Michail,
Poster Session
Area-Aware Pipeline Gating for Embedded Processors
Babak Salamat and
Fast Low-Power 64-Bit Modular Hybrid Adder
Stefania
Speed Indicators for Circuit Optimization
Alexandre
Synthesis of Hybrid CBL/CMOS Cell
Using Multiobjective Evolutionary Algorithms
Francisco
Power-Clock Gating in
Philip
and Doris Schmitt-Landsiedel
The Design
Based on Data Characteristics .
Yijun Im and Steve Furber
Efficient Clock
Daniel
and Antonio Uoris
Power
on Look-Up Table Architectures
Francisco-Javier Veredas
Poster Session
The Optimal Wire Order for Low Power CMOS
Paul
Table of Contents XV
Effect of Post-oxidation Annealing on the Electrical Properties
of Anodic Oxidized Films in Pure Water
BécharîaNadji
Temperature Dependency in UDSM Process
B. Lasbouygws, Robin Wilson,
Circuit Design Techniques
for On-Chip Power Supply Noise Monitoring System
Howard Chen and Louis Hsu
A Novel Approach to the Design of a Linearized Widely Tunable
Very Low Power and Low Noise Differential
Hamid
A New
in Current-Mode Logic Frequency Dividers
Marko
Special Session: Digital Hearing Aids:
Challenges and Solutions for Ultra Low Power
Digital Hearing Aids: Challenges and Solutions for Ultra Low Power
Wolfgang
Tutorial Hearing Aid Algorithms
Thomas Rohdenburg,
Optimization of Digital Audio Processing Algorithms Suitable
for Hearing Aids
Arne Schulz
Optimization of Modules for Digital Audio Processing
Thomas
and Frank
Invited Talks
Traveling the Wild Frontier of Ultra Low-Power Design
Jan Rabaey
DLV (Deep Low Voltage): Circuits and Devices
Sung Bae Park
Wireless Sensor Networks: A New Life Paradigm
Magdy Bayoumi
Cryptography: Circuits and Systems Approach
O. Koufopavlou, G. Selimis, N. Sklavos, and P. Kitsos
Author Index |
| adam_txt |
Table of Contents
Session
A Power-Efficient and Scalable Load-Store Queue Design
Fernando Castro, Daniel Chaver, Luis Pinuel, Manuel
Michael C. Huang, and Francisco
Power Consumption Reduction Using Dynamic Control
of Micro Processor Performance
David Rios-Arambula,
Low Power Techniques Applied to a 80C51 Microcontroller
for High Temperature Applications
Philippe Manet, David
Dynamic Instruction Cascading on GALS Microprocessors
Hiroshi Sasaki, Masaaki Kondo, andHiroshi Nakamura
Power Reduction of Superscalar Processor Functional Units
by Resizing Adder-Width
Guadalupe
and José Manuel Colmenar
Session
A Retargetable Environment for Power-Aware Code Evaluation:
An Approach Based on Coloured Petti Net
Meuse
Cesar Oliveira, Adilson Arcoverde,
and Leornado Amorin
Designing Low-Power Embedded Software for Mass-Produced Microprocessor
by Using a Loop Table in On-Chip Memory
Rodrigo
Energy Characterization of Garbage Collectors for Dynamic Applications
on Embedded Systems
Jose M. Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor,
Francisco
Optimizing the Configuration of Dynamic Voltage Scaling Points
in
Huizhan Yi andXuejun Yang
X Table of
Session
Systematic Preprocessing of Data Dependent Constructs
for Embedded Systems
Martin Palkovic, Erik Bmckmeyer, P. Vanbroekhoven, Henk
and Francky Catthoor
Temperature Aware Datapath Scheduling
AliManzak
Memory Hierarchy Energy Cost of a Direct Filtering Implementation
of the Wavelet Transform
Bert Geelen,
andDiederik Verkest
Improving the Memory Bandwidth Utilization Using Loop Transformations
Minas Dasygenis,
and
Power-Aware Scheduling for Hard
Using Voltage-Scaling Enabled Architectures
AmjadMohsen and Richard
Session
Design of Digital Filters for Low Power Applications
Using Integer Quadratic Programming
Mustafa Aktan and Giinhan Diindar
A High Level Constant Coefficient Multiplier Power Model
for Power Estimation on High Levels of Abstraction
Arne Schulz,
Axel
An Energy-Tree Based Routing Algorithm
in Wireless Ad-Hoc Network Environments
Hyun Ho Kim, Jung Hee Kim, Yong-hyeog Rang, and Young Ik Eom
Energy-Aware System-on-Chip for
Labros
and Roberto Zcfalon
Low-Power VLSI Architectures for OFDM Transmitters
Based on PAPR Reduction
Th, Giannopoulos and Vassilis Paliouras
Session
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits
JosepRius,
Table of
Power Management for Low-Power Battery Operated Portable Systems
Using Current-Mode Techniques
Jean-Félix
Power Consumption in Reversible Logic Addressed by a Ramp Voltage
Alexis
Leakage and Dynamic Glitch Power Minimization
Using Integer Linear Programming for Vm Assignment and Path Balancing
Yuanlin
Back Annotation in High Speed Asynchronous Design
Pankaj Golani and Peter
Session
Optimization of Reliability and Power Consumption in Systems on a Chip
Tajona
Performance Gains from Partitioning Embedded Applications
in Processor-FPGA SoCs
Michalis D. Galanis, Gregory Dimitroulakos, and
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands
for Low Power SOC Design
Ytci
Power Supply Selective Mapping for Accurate Timing Analysis
Mariagrazia
Session
Switching Sensitive Driver Circuit to Combat Dynamic Delay
in On-Chip Buses
Rosnan
andHannu Tenhunen
PSK Signalling on NoC Buses
Crescenza D'Alessandro,
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding
Ashutosh Chakraborty, Enrico Macii, and Massimo Poncino
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Giorgos Dimitrakopoulos and Dimitris Nikolos
Efficient Simulation of Power/Ground Networks with Package and Vias
Jin Shi, Yici
Xu
Session
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers
for Timing Performance Optimisation
Gregorio
Application of
in SCMOS Gates
Alejandro
Paulino Ruiz
Compact Static Power Model of Complex CMOS Gates
Jose L
Energy Consumption in RC Tree Circuits with Exponential Inputs:
An Analytical Model
Massimo Alioto, Gaetano Palumbo, and Massimo
Statistical Critical Path Analysis Considering Correlations
Yaping Than, Andrzej J. Strojwas, Mahesh Sharma, and David Newmark
Session
A CAD Platform for Sensor Interfaces in Low-Power Applications
Didier
An Integrated Environment for Embedded Hard
with Timing and Energy Constraints
Eduardo
Adilson Arcoverde, Gabriel Ahes Jr.,
and Arthur Bessa
Efficient Post-layout Power-Delay Curve Generation
Miodrag Vujkovic, David Wadkins, and
Power
Radu Zlatanovici and Borivoje
Switching-Activity Directed Clustering Algorithm
for Low Net-Power Implementation of FPGAs
Siobhán
Session
Logic-Level Fast Current Simulation for Digital CMOS Circuits
Paulino Ruiz
Alejandro
Design of Variable Input Delay Gates for Low Dynamic Power
Tezaswi Raja, Vishwani D. Agrawal, and Michael Bushnell
Table of Contents XHt
Two-Phase Clocking and a New Latch Design
for Low-Power Portable Applications
Flavio Carbognani, Felix
and Wolfgang
Power Dissipation Reduction During Synthesis of Two-Level Logic
Based on Probability of Input Vectors Changes
Ireneusz Brzpzowski andAndrzej
Session
Energy-Efficient Value-Based Selective Refresh for Embedded
K.
Design and Implementation of a Memory Generator
for Low-Energy Application-Specific Block-Enabled SRAMs
Prassanna
Static Noise Margin Analysis of Sub-threshold SRAM Cells
in Deep Sub-micron Technology
Armin Wellig
An Adaptive Technique for Reducing Leakage and Dynamic Power
in Register Files and Reorder Buffers
Shadi T. Khasawneh and Kanad Ghose
Parameter Variation Effects on Timing Characteristics
of High Performance Clocked Registers
William R. Roberts and Dimitrios Velenis
Poster Session
Low-Power Aspects of Nonlinear Signal Processing
Konstantina
Reducing Energy Consumption of Computer Display
by Camera-Based User Monitoring
Vastly G. Moshnyaga andEiji Morikawa
Controlling Peak Power Consumption During Scan Testing:
Power-Aware DfT and Test Set Perspectives
Nabu
and Christian Landrault
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic
François
and
XIV Table of Contents
Power Consumption Characterisation
of me Texas tostramentsTMS320VC5510 DSP
Miguel Casas-Sanchez, Jose Rizo-Morente, and Chris J. Bleakley
A Method to Design Compact Dual-rail Asynchronous Primitives
¿din Razqfindraibe, Michel Robert, Marc Renaudin, and Philippe Maurine
Enhanced GALS Techniques for Datapath Applications
Eckhard
Christian
Optimizing SHA-1 Hash Function for High Throughput
with a Partial Unrolling Study
U.E. Michail,
Poster Session
Area-Aware Pipeline Gating for Embedded Processors
Babak Salamat and
Fast Low-Power 64-Bit Modular Hybrid Adder
Stefania
Speed Indicators for Circuit Optimization
Alexandre
Synthesis of Hybrid CBL/CMOS Cell
Using Multiobjective Evolutionary Algorithms
Francisco
Power-Clock Gating in
Philip
and Doris Schmitt-Landsiedel
The Design
Based on Data Characteristics .
Yijun Im and Steve Furber
Efficient Clock
Daniel
and Antonio Uoris
Power
on Look-Up Table Architectures
Francisco-Javier Veredas
Poster Session
The Optimal Wire Order for Low Power CMOS
Paul
Table of Contents XV
Effect of Post-oxidation Annealing on the Electrical Properties
of Anodic Oxidized Films in Pure Water
BécharîaNadji
Temperature Dependency in UDSM Process
B. Lasbouygws, Robin Wilson,
Circuit Design Techniques
for On-Chip Power Supply Noise Monitoring System
Howard Chen and Louis Hsu
A Novel Approach to the Design of a Linearized Widely Tunable
Very Low Power and Low Noise Differential
Hamid
A New
in Current-Mode Logic Frequency Dividers
Marko
Special Session: Digital Hearing Aids:
Challenges and Solutions for Ultra Low Power
Digital Hearing Aids: Challenges and Solutions for Ultra Low Power
Wolfgang
Tutorial Hearing Aid Algorithms
Thomas Rohdenburg,
Optimization of Digital Audio Processing Algorithms Suitable
for Hearing Aids
Arne Schulz
Optimization of Modules for Digital Audio Processing
Thomas
and Frank
Invited Talks
Traveling the Wild Frontier of Ultra Low-Power Design
Jan Rabaey
DLV (Deep Low Voltage): Circuits and Devices
Sung Bae Park
Wireless Sensor Networks: A New Life Paradigm
Magdy Bayoumi
Cryptography: Circuits and Systems Approach
O. Koufopavlou, G. Selimis, N. Sklavos, and P. Kitsos
Author Index |
| any_adam_object | 1 |
| any_adam_object_boolean | 1 |
| building | Verbundindex |
| bvnumber | BV020843485 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.75 |
| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | SS 4800 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)61729887 (DE-599)BVBBV020843485 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 2005 Löwen gnd-content |
| genre_facet | Konferenzschrift 2005 Löwen |
| id | DE-604.BV020843485 |
| illustrated | Illustrated |
| index_date | 2024-07-02T13:17:30Z |
| indexdate | 2025-01-10T15:08:04Z |
| institution | BVB |
| institution_GND | (DE-588)10114200-6 |
| isbn | 9783540290131 3540290133 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-014165322 |
| oclc_num | 61729887 |
| open_access_boolean | |
| owner | DE-739 DE-91G DE-BY-TUM DE-706 |
| owner_facet | DE-739 DE-91G DE-BY-TUM DE-706 |
| physical | XV, 753 S. Ill., graph. Darst. |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings Vassilis Paliouras ... (eds.) Berlin [u.a.] Springer 2005 XV, 753 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 3728 Literaturangaben Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2005 Löwen gnd-content Entwurfsautomation (DE-588)4312536-0 s DE-604 Paliouras, Vassilis Sonstige oth PATMOS 15 2005 Löwen Sonstige (DE-588)10114200-6 oth Lecture notes in computer science 3728 (DE-604)BV000000707 3728 text/html http://deposit.dnb.de/cgi-bin/dokserv?id=2672123&prov=M&dok_var=1&dok_ext=htm Inhaltstext Digitalisierung UBPassau application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014165322&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings Lecture notes in computer science Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4312536-0 (DE-588)1071861417 |
| title | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings |
| title_auth | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings |
| title_exact_search | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings |
| title_exact_search_txtP | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings |
| title_full | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings Vassilis Paliouras ... (eds.) |
| title_fullStr | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings Vassilis Paliouras ... (eds.) |
| title_full_unstemmed | Integrated circuit and system design power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings Vassilis Paliouras ... (eds.) |
| title_short | Integrated circuit and system design |
| title_sort | integrated circuit and system design power and timing modeling optimization and simulation 15th international workshop patmos 2005 leuven belgium september 21 23 2005 proceedings |
| title_sub | power and timing modeling, optimization and simulation ; 15th international workshop, PATMOS 2005, Leuven, Belgium, September 21 - 23, 2005 ; proceedings |
| topic | Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Circuits intégrés à très grande échelle - Conception assistée par ordinateur - Congrès Conception assistée par ordinateur - Congrès Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation Konferenzschrift 2005 Löwen |
| url | http://deposit.dnb.de/cgi-bin/dokserv?id=2672123&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014165322&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000707 |
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