Digital electronics with VHDL: quartus II version
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, N.J. [u.a.]
Pearson Prentice Hall
2006
|
| Schlagworte: | |
| Online-Zugang: | Table of contents Inhaltsverzeichnis |
| Beschreibung: | XXII, 938 S. Ill., graph. Darst. 2 CD-ROM (12 cm) |
| ISBN: | 0131714902 |
Internformat
MARC
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| 003 | DE-604 | ||
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| 100 | 1 | |a Kleitz, William |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Digital electronics with VHDL |b quartus II version |c William Kleitz |
| 264 | 1 | |a Upper Saddle River, N.J. [u.a.] |b Pearson Prentice Hall |c 2006 | |
| 300 | |a XXII, 938 S. |b Ill., graph. Darst. |e 2 CD-ROM (12 cm) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Digital electronics |x Data processing | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitalschaltung |0 (DE-588)4012295-5 |2 gnd |9 rswk-swf |
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| 689 | 0 | 2 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | 3 | |a VHDL |0 (DE-588)4254792-1 |D s |
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| 856 | 4 | |u http://www.loc.gov/catdir/toc/ecip056/2005001249.html |3 Table of contents | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013528571&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
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Datensatz im Suchindex
| _version_ | 1804133777750884352 |
|---|---|
| adam_text | NUMBER SYSTEMS AND CODES 2 OUTLINE 2 OBJECTIVES 2 INTRODUCTION 3 1-1
DIGITAL VERSUS ANALOG 3 1-2 DIGITAL REPRESENTATIONS OF ANALOG QUANTITIES
3 1-3 DECIMAL NUMBERING SYSTEM (BASE 10) 6 1 -H BINARY NUMBERING SYSTEM
(BASE 2) 7 1-5 DECIMAL-TO-BINARY CONVERSION 9 1 -6 OCTAL NUMBERING
SYSTEM (BASE 8) I L 1-7 OCTAL CONVERSIONS 11 1-8 HEXADECIMAL NUMBERING
SYSTEM (BASE 16) 13 1-9 HEXADECIMAL CONVERSIONS 14 1-10
BHIARY-CODED-DECIMAL SYSTEM 16 1-11 COMPARISON OF NU MBERING SYSTEMS 16
1-12 THE ASCII CODE 16 1-13 APPLI CATI ONS OF THE NU MBER SYSTEMS 18
SUMMARY 21 GLOSSARY 22 PROBLEMS 23 SCHEMATIC INTERPRETATION PROBLEMS 24
MULTISIM EXERCISES 25 ANSWERS TO REVIEW QUESTIONS 26 CHAPTER 2-4
PARALLEL REPRESENTATION 32 2-5 SWITCHES IN ELECTRONIC CIRCUITS 35 2-6 A
RCLAY AS A SWITCH 36 2-7 A DIODE AS A SWITCH 39 2-8 A TRANSISTOR AS A
SWITCH 42 2-9 THE TTL INTEGRATED CIRCUIT 46 2-10 THE CMOS INTEGRATED
CIRCUIT 49 2-11 SURFACE-MOUNT DEVICES 50 SUMMARY 51 GLOSSARY 52 PROBLEMS
53 SEHEMATIC INTERPRETATION PROBLEMS 56 MULLISIMEXERCISCS 56 ANSWERS TO
REVIEW QUE.STIONS 57 CHAPTER J L BASIC LOGIC GATES OUTLINE 58 OBJECTIVES
58 LNTRODUCTION 59 3-1 THE AND GATE 59 3-2 THE OR GATE 61 3-3 TIMING
ANALYSIS 63 3-4 ENABLE AND DISABLE FUNCTIONS 65 3-5 USING IC LOGIC GATES
67 3-6 LNTRODUCTION TO TROUBLESHOOTING TECHNIQIICS 68 3-7 THE INVERTER
73 3-8 THE NAND GATE 74 3-9 THE NOR GATE 76 3-10 LOGIC GATE WAVEFORM
GENERATION 78 3-11 USING IC LOGIC GATES 84 3-12 SUMMARY OF THE BASIC
LOGIC GATES AND LEEE/IEC STANDARD SUMMARY 88 GLOSSARY 89 PROBLEMS 90
SEHEMATIC INTERPRETATION PROBLEMS 100 MULTISIM EXERCISES 101 ANSWERS TO
REVIEW QUESTIONS 103 CHAPTER ^| PROGRAMMABLE LOGIC DEVICES: CPLDS AND
FPG WITH VHDL DESIGN PLD DESIGN FLOW 105 PLD ARCHITECTURE 107 USING
PLDS TO SOLVE BASIC LOGIC DESIGNS 112 TUTORIAL FOR USING ALTERA S
QUARTUS II DESIGN AND SIMULATION SOFTWARE 118 CPLD APPLICATIONS 145
SUMMARY 149 GLOSSARY 150 PROBLEMS 151 CPLD PROBLEMS 152 CHAPTER J
BOOLEAN ALGEBRA AND REDUCTION TECHNIQUES 156 OUTLINE 156 OBJECTIVES 156
INTRODUCTION 157 5-1 COMBINATIONAL LOGIC 157 5-2 BOOLEAN ALGEBRA LAWS
AND RULES 161 5-3 SIMPLIFICATION OF COMBINATIONAL LOGIC CIRCUITS USING
BOOLEAN ALGEBRA 166 5-4 USING QUARTUS II TO DETERMINE SIMPLIFIED
EQUATIONS 170 5-5 DE MORGAN S THEOREM 176 5-6 ENTERING A TRUTH TABLE IN
VHDL USING A VECTOR SIGNAL 189 5-7 THE UNIVERSAL CAPABILITY OF NAND AND
NOR GATES 194 5-8 AND-OR-INVERT GATES FOR IMPIEMENTING SUM-OF-PRODUCTS
EXPRESSION 199 5-9 KARNAUGH MAPPING 203 5-10 SYSTEM DESIGN APPLICATIONS
209 SUMMARY 212 GLOSSARY 212 PROBLEMS 214 SCHEMATIC INTERPRETATION
PROBLEMS 226 MULTISIM EXERCISES 226 CPLD PROBLEMS 229 ANSWERS TO REVIEW
QUESTIONS 232 CHAPTER O EXCLUSIVE-OR AND EXCLUSIVE-NOR GATES 234 SUMMARY
249 GLOSSARY 249 PROBLEMS 250 SCHEMATIC INTERPRETATION PROBLEMS 253
MUELTISLM EXERCISES 253 CPLD PROBLEMS 254 ANSWERS TO REVIEW QUESTIONS
255 CHAPTER / ARITHMETIC OPERATIONS AND CIRCUITS OUTLINE 256 OBJECTIVES
256 INTRODUCTION 256 7-1 BINARY ARITHMETIC 257 7-2 TWOVCOMPLEMENT
REPRESENTATION 263 7-3 TWO S-COMPLEMENT ARITHMETIC 265 7-4 HEXADECIMAL
ARITHMETIC 267 7-5 BCD ARITHMETIC 270 7-6 ARITHMETIC CIRCUITS 271 7-7
FOUR-BIT FULJ-ADDER ICS 276 7-8 VHDL ADDERS USING INTEGER ARITHMETIC 279
7-9 SYSTEM DESIGN APPLICATIONS 281 7-10 ARITHMETIC/LOGII- UNITS 284 7-11
CPLD APPLICATIONS WITII VIIDL AND LPMS 287 SUMMARY 294 GLOSSARY 295
PROBLEMS 296 SCHEMATIC INTERPRETATION PROBLEMS 300 MULTISIM EXERCISES
301 CPLD PROBLEMS 30.1 ANSWERS TO REVIEW QUESTIONS 303 CHAPTER O CODE
CONVERTERS, IVLULTIPLEXERS, AND DEMULTIP OUTLINE 304 OBJECTIVES 304
INTRODUCTION 304 8-1 COMPARATORS 305 8-2 VHDL COMPARATOR USING
IF-THEN-ELSE 307 8-3 DECODINS 310 8-8 DEMULTIPLEXERS 342 8-9 SYSTEM
DESIGN APPLICATIONS 345 8-10 CPLD DESIGN APPLICATIONS USING LPMS 353
SUMMARY 357 GLOSSARY 357 PROBLEMS 358 SCHEMATIC INTERPRETATION PROBLEMS
365 MULTISIM EXERCISES 365 CPLD PROBLEMS 368 ANSWERS TO REVIEW
QUESTIONS 370 CHAP TER 9 LOGIC FAMILIES AND THEIR CHARACTERISTICS 372
OUTLINE 372 OBJECTIVES 372 INTRODUCTION 372 9-1 THE TTL FAMILY 373 9-2
TTLVOLTAGE AND CURRENT RATINGS 375 9-3 OTHER TTL CONSIDERATIONS 384 9-4
IMPROVED TTL SERIES 389 9-5 THE CMOS FAMILY 391 9-6 EMITTER-COUPLED
LOGIC 396 9-7 COMPARITIG LOGIC FAMILIES 398 9-8 INTERFACING LOGIC
FAMILIES 399 9-9 CPLD ELECTRICAL CHARACTERISTICS 406 SUMMARY 408
GLOSSARY 408 PROBLEMS 410 SCHEMATIC INTERPRETATION PROBLEMS 413
MULTISIM EXERCISES 414 CPLD PROBLEMS 414 ANSWERS TO REVIEW QUESTIONS
415 CHAPTER 10 FLIP-FLOPS AND REGISTERS 416 OUTLINE 416 OHIPRF IVF*Q
A F HDGE-TRIGGERED J-K FLIP-FLOP WITH VHDL MODEL 439 INTEGRAIED-CIRCUIT
J-K FIIP-FLOP (7476, 74LS76) 443 U.SING AN OCTAL D FLIP-FLOP IN A
MICROCONSROLLER APPLICA USING ALTERA S LPM FLIP-FLOP 452 SURNMARY 455
GLOSSARY 455 PROBLEMS 457 SCHEMALIC INTERPRETATION PROBLEMS 464
MULTISIM EXERDSES 464 CPLD PROBLEMS 465 ANSWERS TO REVIEW QUESLIONS 467
CHAPTER I I PRACTICAL CONSIDERATIONS FOR DIGITAL DESIGN OUTLINE 470
OBJECTIVES 470 INTRODUKTION 470 11-1 FLIP-FLOP TIME PARAMETERS 471 11-2
AUTOMATIC RESET 488 11-3 SCHMITT TRIGGER ICS 489 11-4 SWITCH DEBOUNCING
494 11-5 SIZING PULL-UP RESISTORS 498 11-6 PRACTICAL INPUT AND OUTPUT
CONSIDERATIONS 499 SURNMARY 506 GLOSSARY 507 PROBLEMS 509 SCHEMATIC
INTERPRETATION PROBLEMS 514 MULTISIM* 1 HXCIX.-I.SES 514 ANSWERS TO
REVIEW QUESLIONS 515 CHAPTER JL COUNTER CIRCUITS AND VHDL STATE
MACHINES OUTLINE 516 OBJECTIVES 516 INTRODUCTION 516 12-1 ANALYSIS
OFSEQUENTIAL CIRCUITS 518 12-2 RIPPLE COUNTERS: JK FFS AND VHDL
DESCRIPTION 521 12-3 DESIGN OF DIVIDE-BY-JV COUNTERS 527 12-4 RIPPLE
COUNTER ICS 536 12-5 SYSTEM DESIGN APPLICATIONS 542 12-6 SEVEN-SEGMENT
LED DISPLAY DECODERS: THE 7447 IC AND DESCRIPTION 549 10-7 10-8 10-9
10-10 12-10 VHDL AND LPM COUNTERS 573 12-11 IMPLEMENTING STATE MACHINES
IN VHDL 577 SUMMARY 589 GLOSSARY 590 PROBLEMS 592 SCHEMATIC
INTERPRETATION PROBLEMS 597 MULTISIM EXERCISES 599 CPLD PROBLEMS 599
ANSWERS TO REVIEW QUESTIONS 602 CHAPTER 13 604 SHIFT REGISTERS OUTLINE
604 OBJECTIVES 604 INTRODUCTION 604 13-1 SHIFT REGISTER BASICS 605 13-2
PARALLEL-TO-SERIAL CONVERSION 607 13-3 RECIRCULATING REGISTER 607 13-4
SERIAL-TO-PARALLEL CONVERSION 609 13-5 RING SHIFT COUNTER AND JOHNSON
SHIFT COUNTER 609 13-6 VHDL DESCRIPTION OF SHIFT REGISTERS 612 13-7
SHIFT REGISTER ICS 612 13-8 SYSTEM DESIGN APPLICATIONS FOR SHIFT
REGISTERS 624 13-9 DRIVING A STEPPER MOTOR WITH A SHIFT REGISTER 628
13-10 THREC-STATE BUFFERS, LAICHES, AND TRANSCEIVERS 632 13-11
USINGTHELPMSHIFT REGISTER AND 74194 MACROFUNCTION 635 13-12 USING VHDL
COMPONENTS AND INSTANTIATIONS 638 SUMMARY 642 GLOSSARY 643 PROBLEMS 644
SCHEMATIC INTERPRETATION PROBLEMS 651 MULTISIM EXERCISES 651 CPLD
PROBLEMS 652 ANSWERS TO REVIEW QUESTIONS 655 CHAPTER I M MULTIVIBRATORS
AND THE 555 TIMER 656 14-5 INTEGRATED-CIRCUIT MONOSTABLE MULTIVIBRATORS
666 14-6 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS 670 14-7 ASTABLE
OPERATION OF THE 555 IC TIMER 673 14-8 MONOSTABLE OPERATION OF THE 555
IC TIMER 678 14-9 CRYSTAL OSCIILATORS 68 I SUMMARY 683 GLOSSARY 683
PROBLEMS 684 SCHEMATIC INTERPRETATION PROBLEMS 687 MULTISJMEXERCISE.S
687 ANSWERS TO REVIEW QUESLIONS 688 CHAPTER 15 INTERFACING TO THE ANALOG
WORLD OUTLINE 690 OBJECTIVES 690 INTRODUCTION 690 15-1 DIGITAL AND
ANALOG REPRESENTATIONS 691 15-2 OPERATIONAL AMPLIFIER BASICS 692 15-3
BINARY-WEIGHTED D/A CONVERTERS 693 1 5-4 R/2R LADDER D/A CONVERTERS 694
15-5 INTEGRATED-CIRCUIT D/A CONVERTERS 697 15-6 TNTEGRATED-CIRCUIT DATA
CONVERTER SPECIFICATIONS 699 15-7 PARALLEL-ENCODED A/D CONVERTERS 701
15-8 COUNTER-RAMP A/D CONVERTERS 701 15-9 SUCCCSSIVE-APPROXIMATION A/D
CONVERSION 703 15-10 INTEGRATED-CIRCLIIT A/D CONVERTERS 706 15-11 DAT A
ACQUISITION SYSTEM APPLICATION 7II 15-12 TRANSDUCERS AND SIGNAL
CONDITIONING 714 SUMMARY 718 GLOSSARY 719 PROBLEMS 720 SCHEMATIC
INTERPRETATION PROBLEMS 724 MULTISTM EXERCISES 724 ANSWERS TO REVIEW
QUESTIONS 725 CHAPTER 1 O SEMICONDUCTOR, MAGNETIC, AND OPTICA! MEMORY
OUTLINE 726 OBJECTIVES 726 INTRODUCTION 726 16-4 READ-ONLY MEMORIES 743
16-5 MEMORY EXPANSION AND ADDRESS DECODING APPLICATIONS 750 16-6
MAGNETIC AND OPTICAL STORAGE 755 SUMMARY 759 GLOSSARY 760 PROBLEMS 761
SCHEMATIC INTERPRETATION PROBLEMS 764 MULTISIM EXERCISES 764 ANSWERS TO
REVIEW QUESTIONS 765 CHAPTER 17 MICROPROCESSOR FUNDAMENTALS 766 OUTLINE
766 OBJECTIVES 766 INTRODUCTION 766 17-1 INTRODUCTION TO SYSTEM
COMPONENTS AND BUSES 767 17-2 SOFTWARE CONTROL OF MICROPROCESSOR SYSTEMS
770 17-3 INTERNAL ARCHITECTURE OF A MICROPROCESSOR 771 17-4 INSTRUCTION
EXECUTION WITHIN A MICROPROCESSOR 772 17-5 HARDWARE REQUIREMENTS FOR
BASIC I/O PROGRAMMING 775 17-6 WRITING ASSEMBLY LANGUAGE AND MACHINE
LANGUAGE PROGRAMS 777 17-7 SURVEY OF MICROPROCESSORS AND MANUFACTURERS
780 SUMMARY OF INSTRUCTIONS 781 SUMMARY 781 GLOSSARY 782 PROBLEMS 783
SCHEMATIC INTERPRETATION PROBLEMS 785 ANSWERS TO REVIEW QUESTIONS 786
CHAPTER 18 THE 8051 MICROCONTROLLER 788 OUTLINE 788 OBJECTIVES 788
INTRODUCTION 789 18- 1 THE 8051 FAMILY OF MICROCONTROLLERS 789 18-2 8051
ARCHITECTURE 789 APPENDIX A WWW SITES 822 APPENDIX B MANUFACTURERS DATA
SHEETS 824 APPENDIX C EXPLANATJON OF THE IEEE/IEC STANDARD IBR H
(DEPENDENCY NOTATION! 876 APPENDIX D AN.SWERS T APPENDIX E VHDL LANGUAGE
REFERENEE 902 APPENDIX F REVIEW OF BASIC ELECTRICILY PRINCIPLE.S 908
APPENDIX G SEHEMALIC DIAGRAM.S LOR CHAPTER-END PROBLE APPENDIX H 8051
INSTRUCTION SET SIIMMARY 928 INDEX 934 SUPPI.EMENTARY INDEX OL ICS 938
|
| any_adam_object | 1 |
| author | Kleitz, William |
| author_facet | Kleitz, William |
| author_role | aut |
| author_sort | Kleitz, William |
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| building | Verbundindex |
| bvnumber | BV020823240 |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
| callnumber-raw | TK7868.D5 |
| callnumber-search | TK7868.D5 |
| callnumber-sort | TK 47868 D5 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 5405 |
| ctrlnum | (OCoLC)57549684 (DE-599)BVBBV020823240 |
| dewey-full | 621.381 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381 |
| dewey-search | 621.381 |
| dewey-sort | 3621.381 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV020823240 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:14:07Z |
| institution | BVB |
| isbn | 0131714902 |
| language | English |
| lccn | 2005001249 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013528571 |
| oclc_num | 57549684 |
| open_access_boolean | |
| owner | DE-859 DE-706 |
| owner_facet | DE-859 DE-706 |
| physical | XXII, 938 S. Ill., graph. Darst. 2 CD-ROM (12 cm) |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Pearson Prentice Hall |
| record_format | marc |
| spelling | Kleitz, William Verfasser aut Digital electronics with VHDL quartus II version William Kleitz Upper Saddle River, N.J. [u.a.] Pearson Prentice Hall 2006 XXII, 938 S. Ill., graph. Darst. 2 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung Digital electronics Data processing VHDL (Computer hardware description language) Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Digitalschaltung (DE-588)4012295-5 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 s Digitalschaltung (DE-588)4012295-5 s Schaltungsentwurf (DE-588)4179389-4 s VHDL (DE-588)4254792-1 s DE-604 http://www.loc.gov/catdir/toc/ecip056/2005001249.html Table of contents GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013528571&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Kleitz, William Digital electronics with VHDL quartus II version Datenverarbeitung Digital electronics Data processing VHDL (Computer hardware description language) Schaltungsentwurf (DE-588)4179389-4 gnd VHDL (DE-588)4254792-1 gnd Digitalschaltung (DE-588)4012295-5 gnd Digitalelektronik (DE-588)4260328-6 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4254792-1 (DE-588)4012295-5 (DE-588)4260328-6 |
| title | Digital electronics with VHDL quartus II version |
| title_auth | Digital electronics with VHDL quartus II version |
| title_exact_search | Digital electronics with VHDL quartus II version |
| title_full | Digital electronics with VHDL quartus II version William Kleitz |
| title_fullStr | Digital electronics with VHDL quartus II version William Kleitz |
| title_full_unstemmed | Digital electronics with VHDL quartus II version William Kleitz |
| title_short | Digital electronics with VHDL |
| title_sort | digital electronics with vhdl quartus ii version |
| title_sub | quartus II version |
| topic | Datenverarbeitung Digital electronics Data processing VHDL (Computer hardware description language) Schaltungsentwurf (DE-588)4179389-4 gnd VHDL (DE-588)4254792-1 gnd Digitalschaltung (DE-588)4012295-5 gnd Digitalelektronik (DE-588)4260328-6 gnd |
| topic_facet | Datenverarbeitung Digital electronics Data processing VHDL (Computer hardware description language) Schaltungsentwurf VHDL Digitalschaltung Digitalelektronik |
| url | http://www.loc.gov/catdir/toc/ecip056/2005001249.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013528571&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT kleitzwilliam digitalelectronicswithvhdlquartusiiversion |