Interconnection noise in VLSI circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston, Mass.
Kluwer
2004
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | XXI, 195 S. : Ill. |
| ISBN: | 1402077335 |
Internformat
MARC
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| 245 | 1 | 0 | |a Interconnection noise in VLSI circuits |c by Francesc Moll and Miquel Roca |
| 264 | 1 | |a Boston, Mass. |b Kluwer |c 2004 | |
| 300 | |a XXI, 195 S. : |b Ill. | ||
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| 650 | 4 | |a Integrated circuits, Very large scale integration | |
| 650 | 4 | |a Interconnects (Integrated circuit technology) | |
| 700 | 1 | |a Roca, Miquel |e Sonstige |4 oth | |
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Datensatz im Suchindex
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|---|---|
| adam_text | INTERCONNECTION NOISE IN VLSI CIRCUITS BY FRANCESC MOLL UNIVERSITAET
POLITECNICA DE CATALUNYA, BARCELONA, SPAIN AND MIQUEL ROCA UNIVERSITAET
ILLES BALEARS, PALMA DE MALLORCA, SPAIN KLUWER ACADEMIC PUBLISHERS
BOSTON / DORDRECHT / LONDON CONTENTS LIST OF FIGURES IX LIST OF TABLES
XVII PREFACE XIX ACKNOWLEDGMENTS XXI 1. MICROELECTRONIC INTERCONNECTIONS
1 1 SIGNAL TRANSMISSION IN INTERCONNECTS 1 1.1 THE PROBLEM WITH
INTERCONNECTIONS 2 1.2 PHYSICAL FACTORS IN INTERCONNECT DESIGN 4 2
ON-CHIP INTERCONNECTIONS 4 2.1 TECHNOLOGY 4 2.2 SCALING TRENDS 6 2.3
ELECTRICAL REFERENCE CONNECTION SCHEMES 6 3 PACKAGE LEVEL
INTERCONNECTIONS 7 3.1 TECHNOLOGY 7 3.2 SCALING TRENDS IN PACKAGING 8
3.3 POWER VOLTAGE DISTRIBUTION AND SWITCHING NOISE 8 2. INTERCONNECT
MODELING 11 1 PHYSICAL FOUNDATIONS FOR CIRCUIT MODEIS OF
INTERCONNECTIONS 12 1.1 TEMWAVES 13 1.2 QUASI-TEM MODEL 17 1.3
SIMPLIFICATIONS OF THE RLGC MODEL 18 1.4 VALIDITY OF THE QUASI-TEM
ASSUMPTION 20 2 LOSSLESS TRANSMISSION LINE MODEL 22 2.1 RESISTIVE DRIVER
MODEL 23 2.2 EFFECT OF SIGNAL RISE TIME 28 2.3 CMOS DRIVER WITH OPEN
CIRCUIT LOAD 30 INTERCONNECTION NOISE IN VLSI CIRCUITS 3 LOSSY
TRANSMISSION LINE MODEL 33 3.1 EFFECT OF SEMICONDUCTOR SUBSTRATE 34 3.2
EXAMPLE SIMULATIONS 38 4 OPTIMUM LINE MODEL SELECTION 40 4.1 EFFECT OF
INPUT RISE TIME 43 4.2 EFFECT OF DRIVER IMPEDANCE 44 4.3 EFFECT OF LINE
LENGTH 44 CROSSTALK EFFECTS IN DIGITAL CIRCUITS 47 1 SPURIOUS SIGNALS 48
1.1 SPURIOUS SIGNAL CHARACTERIZATION 48 1.2 PROPAGATION OF SPURIOUS
SIGNALS THROUGH VLSI DIGITAL CIRCUITS 56 1.3 MEASUREMENT OF SPURIOUS
SIGNALS 59 2 CROSSTALK INDUCED DELAY 65 2.1 EXPERIMENTAL MEASUREMENT
APPROACHES 66 2.2 EXPERIMENTAL RESULTS 71 3 ENERGY DISSIPATION DUE TO
CROSSTALK 73 3.1 ENERGY CALCULATION FOR A SINGLE TRANSITION 75 3.2
CONTRIBUTION OF DRIVER AND INTERCONNECT TO DISSIPATED ENERGY 78 3.3
TRANSITIONS IN BOTH NODES 82 3.4 DISCUSSION 84 4 CROSSTALK EFFECTS IN
LOGIC VLSI CIRCUITS 88 4.1 STATIC CIRCUITS 89 4.2 DYNAMIC CIRCUITS 90
PACKAGINGINTERCONNECTS 97 1 PACKAGING STRUCTURE 97 1.1 BODY FABRICATION
TECHNOLOGY 98 1.2 EXTERNAL CONNECTIONS 99 1.3 CHIP CONNECTION 101 2
LUMPED ELECTRICAL PARAMETER MODELING OF PACKAGES 103 2.1 CALCULATION OF
CIRCUIT PARAMETERS 103 2.2 CONCEPT OF PARTIAL INDUCTANCE 104 2.3 SKIN
EFFECT CALCULATION 105 2.4 RESISTANCE AND INDUCTANCE CALCULATION 105 3
CIRCUIT MODELING FROM MEASUREMENT 107 3.1 SETUP FOR MEASURING INDUCTANCE
108 CONTENTS VN 3.2 TIME DOMAIN MEASUREMENT METHODS 111 3.3 FREQUENCY
DOMAIN MEASUREMENT METHODS 115 4 POWER DISTRIBUTION MODELING FROM EM
SIMULATION 117 4.1 STIMULUS DEFINITION FOR EM SIMULATION 117 4.2 CIRCUIT
MODEL OBTAINED FROM EM SIMULATIONS 119 5 SIMULATIONS OF PACKAGE EFFECTS
122 5.1 EFFECT OFSSN 125 5.2 EFFECT OFCROSSTALK 127 5.3 DISCUSSION 130
5. TECHNIQUES FOR AVOIDING INTERCONNECTION NOISE 137 1 CROSSTALK
AVOIDANCE 137 1.1 TECHNOLOGY SOLUTIONS 138 1.2 INTERCONNECTION LAYOUT
140 1.3 DRIVERSIZING 149 1.4 TOLERANT CIRCUITS 150 2 SWITCHING NOISE
AVOIDANCE 152 2.1 PACKAGE TECHNOLOGY 154 2.2 USE OF DECOUPLING
CAPACITORS 154 2.3 PIN ASSIGNMENT 160 2.4 CIRCUIT TECHNIQUES 164 6.
NOISE DETECTION IN LOGIC CIRCUITS 171 1 THE NOISE DETECTION PROBLEM 171
2 BRIEF INTRODUCTION TO THE TESTING OF LOGIC CIRCUITS 172 2.1 ATPG FOR
STUCK-AT FAULTS 173 2.2 BACKTRACE AND BACKTRACK PROCEDURES IN PODEM 175
2.3 SSN DETECTION PROBLEM 176 2.4 CROSSTALK DETECTION PROBLEM 177 3
CROSSTALK-INDUCED SPURIOUS SIGNAL DETECTION 177 3.1 CROSSTALK FAULT
CONTROLLABILITY AND OBSERVABILITY 179 3.2 ATPG FOR CROSSTALK 180 3.3
RESULTS 182 4 OTHER TEST TECHNIQUES 184 4.1 ATPG WITH TIMING IMPLICATION
CONSIDERATIONS 184 4.2 DELAY FAULT TESTING 185 4.3 IDDX TEST APPROACHES
TO CROSSTALK DETECTION 186 4.4 DESIGN FOR TESTABILITY AND ON LINE
DETECTION 188 VLLL INTERCONNECTION NOISE IN VLSI CIRCUITS INDEX 191
ABOUT THE AUTHORS 195
|
| any_adam_object | 1 |
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| ctrlnum | (OCoLC)53971899 (DE-599)BVBBV020820884 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
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| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV020820884 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:14:03Z |
| institution | BVB |
| isbn | 1402077335 |
| language | English |
| lccn | 2003070071 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013526257 |
| oclc_num | 53971899 |
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| owner_facet | DE-91 DE-BY-TUM |
| physical | XXI, 195 S. : Ill. |
| publishDate | 2004 |
| publishDateSearch | 2004 |
| publishDateSort | 2004 |
| publisher | Kluwer |
| record_format | marc |
| spelling | Moll, Francesc Verfasser aut Interconnection noise in VLSI circuits by Francesc Moll and Miquel Roca Boston, Mass. Kluwer 2004 XXI, 195 S. : Ill. txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references and index Electronic circuits Noise Integrated circuits, Very large scale integration Interconnects (Integrated circuit technology) Roca, Miquel Sonstige oth GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013526257&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Moll, Francesc Interconnection noise in VLSI circuits Electronic circuits Noise Integrated circuits, Very large scale integration Interconnects (Integrated circuit technology) |
| title | Interconnection noise in VLSI circuits |
| title_auth | Interconnection noise in VLSI circuits |
| title_exact_search | Interconnection noise in VLSI circuits |
| title_full | Interconnection noise in VLSI circuits by Francesc Moll and Miquel Roca |
| title_fullStr | Interconnection noise in VLSI circuits by Francesc Moll and Miquel Roca |
| title_full_unstemmed | Interconnection noise in VLSI circuits by Francesc Moll and Miquel Roca |
| title_short | Interconnection noise in VLSI circuits |
| title_sort | interconnection noise in vlsi circuits |
| topic | Electronic circuits Noise Integrated circuits, Very large scale integration Interconnects (Integrated circuit technology) |
| topic_facet | Electronic circuits Noise Integrated circuits, Very large scale integration Interconnects (Integrated circuit technology) |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013526257&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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