VLSI-design of non-volatile memories:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2005
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XXVIII, 581 S. Ill., graph. Darst. |
| ISBN: | 354020198X |
Internformat
MARC
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| 100 | 1 | |a Campardo, Giovanni |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a VLSI-design of non-volatile memories |c Giovanni Campardo ; Rino Micheloni ; David Novosel |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2005 | |
| 300 | |a XXVIII, 581 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Literaturangaben | ||
| 650 | 4 | |a Integrated circuits |x Very large scale integration | |
| 650 | 0 | 7 | |a Nichtflüchtiger Speicher |0 (DE-588)4728810-3 |2 gnd |9 rswk-swf |
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| 689 | 0 | 1 | |a Nichtflüchtiger Speicher |0 (DE-588)4728810-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Micheloni, Rino |e Verfasser |4 aut | |
| 700 | 1 | |a Novosel, David |e Verfasser |4 aut | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013371392&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-013371392 | |
Datensatz im Suchindex
| _version_ | 1816865571995648000 |
|---|---|
| adam_text |
CONTENTS
FOREWORD:
NON-VOLATILE MEMORY TECHNOLOGY EVOLUTION XVII
SYSTEMS NEEDS FOR NON-VOLATILE STORAGE XVIII
NOR FLASH MEMORY XXI
NAND FLASH MEMORY XXIII
NEW MEMORY CONCEPTS XXV
CONCLUSIONS XXVIII
1 NON-VOLATILE MEMORY DESIGN 1
1.1 INTRODUCTION 1
1.2 MAIN FEATURES OF NON-VOLATILE MEMORIES 2
1.3 PROGRAM 3
1.4 ERASE 4
1.5 DISTRIBUTIONS AND CYCLES 4
1.6 READ MODE ARCHITECTURE 7
1.7 WRITE MODE ARCHITECTURE 8
1.8 ERASE MODE ARCHITECTURE 9
1.9 ELEMENTS OF RELIABILITY 10
1.10 INFLUENCE OF TEMPERATURE AND SUPPLY VOLTAGE 10
1.11 LAB ACTIVITIES 11
1.12 WORKING TOOLS 12
1.13 SHMOOPLOTS 14
1.14 TESTING 16
1.15 MEMORY PINS DESCRIPTION 16
BIBLIOGRAPHY 19
2 PROCESS ASPECTS 21
2.1 INTRODUCTION 21
2.2 MAIN STEPS OF FABRICATION FOR A CMOS PROCESS 21
BIBLIOGRAPHY 33
3 THE MOSFET TRANSISTOR AND THE MEMORY CELL 35
3.1 THE MOSFET TRANSISTOR 35
3.2 TRANSISTORS AVAILABLE 39
3.3 THE MEMORY CELL 44
3.4. READING CHARACTERISTICS 48
3.5 PROGRAMMING 50
3.6 PROGRAM ALGORITHM 57
X CONTENTS
3.7 ERASE OPERATION
3.7.1 ERASING AT CONSTANT VOLTAGE
61
3.7.2 CONSTANT CURRENT ERASE." ,
(
3.7.3 ERASING AT NEGATIVE GATE AND TRIPLE-WEVL ARRAY 67
3.8 ERASE ALGORITHM "'
BIBLIOGRAPHY . "
69
PASSIVE COMPONENTS.
4.1 MOS CAPACITORS
7I
4.2 CMOS TECHNOLOGY CAPACITORS.'.'.'.'.'.'.'.'.'.'.'.' L\
4.3 INTEGRATED RESISTORS
BIBLIOGRAPHY.
79
FUNDAMENTAL CIRCUIT BLOCKS
5.1 INTRODUCTION
5.2 NMOS AND CMOS INVE'RTER'S L\
5.3 THECASCODE
81
5.4 DIFFERENDALSTAGE .'.'.'.'.'.'
87
5.5 THE SOURCE FOLLOWER Q?
5.6 VOLTAGE REFERENCES \7
5.6.1 NMOS
%
5.6.2 CMOS
97
5.6.3 SELF-BIASED GENERATOR.'.' ]UEJ!
5.6.4 BAND-GAP REFERENCE VZ
5.7 CURRENT MIRRORS
5.8 NMOS AND CMOS SCHMITT'TRIGGER !!!Q
5.9 VOLTAGE LEVEL SHIFTER LATCH " ,,,
5.10 POWER ON RESET CIRCUITS. , .Z
5.11 ANALOG SWITCH.
I15
5.12 BOOTSTRAP '
L9
5.12.1 PUSH-PULL BOOTSTRAP'.'.'.'.' \LL
5.12.2 PUSH-PULL BOOTSTRAP WITH ANTI-GLITC'H P
S 1. N U
PUSH
-
PULLBOO
^APFORALARGELOAD.'.'.'.'.' HO
5.13 OSCILLATORS
,JU
5.14 CIRCUITS TO DETECT THIRD LEVEL SIGNALS \\[
5.15 VDD LOW DETECTOR [F
BIBLIOGRAPHY . '"
138
LAYOUT
6.1 CUSTOM LAYOUT
I41
6.2 A THREE-LNPUTS NAND \
A
\
6.3 A THREE-LNPUTS NOR
6.4 AN INTERDIGITIZED INVERTER AND'A'C'APA'C'I'TO'R'.'.'
U
L
6.5 AREA AND PERIMETER PARASITIC CAPACITANCES. \Z
6.6 AUTOMATIC LAYOUT.
BIBLIOGRAPHY.
147
149
CONTENTS XI
7 THE ORGANIZATION OF THE MEMORY ARRAY 151
7.1 INTRODUCTION: EPROM MEMORIES 151
7.2 FLASH MEMORY ORGANIZATION: THE SECTORS 151
7.3 AN ARRAY OF SECTORS 158
7.4 OTHER TYPES OF ARRAY 159
7.4.1 DINOR ARRAYS (DIVIDED BIT LINE NOR) 160
7.4.2 AND ARRAYS 162
7.4.3 NAND ARCHITECTURE 163
BIBLIOGRAPHY 165
8 THE INPUT BUFFER 167
8.1 A DISCUSSION ON INPUT AND OUTPUT LEVELS 167
8.2 INPUT BUFFERS 168
8.3 EXAMPLES OF INPUT BUFFERS 170
8.4 AUTOMATIC STAND-BY MODE 172
BIBLIOGRAPHY 174
9 DECODERS 175
9.1 INTRODUCTION 175
9.2 WORD LINE CAPACITANCE AND RESISTANCE 179
9.3 ROW DECODERS 184
9.4 NMOS ROW DECODER 190
9.5 CMOS ROW DECODERS 195
9.6 A DYNAMIC CMOS ROW DECODING 195
9.7 A SEMISTATIC CMOS ROW DECODER 197
9.8 ROW DECODERS FOR LOW SUPPLY VOLTAGE 199
9.9 ROW PRE-DECODER AT HIGH VOLTAGE 202
9.10 SECTOR DECODING 203
9.11 MEMORY SPACE FOR TEST: THE OTP ROWS 205
9.12 HIERARCHICAL ROW DECODING 206
9.12.1 READ & PROGRAM 207
9.12.2 ERASE 208
9.13 LOW SWITCHING CONSUMPTION ROW DECODER 211
9.14 COLUMN DECODERS 213
BIBLIOGRAPHY 215
10 BOOST 217
10.1 INTRODUCTION 217
10.2 BOOST TECHNIQUES 217
10.3 ONE-SHOT LOCAL BOOST 220
10.4 DOUBLE-BOOST ROW DECODER 224
10.5 THE ISSUEOF THE RECHARGE OT'C
B(K)ST
227
10.6 DOUBLE-PATH BOOST CIRCUITRY 230
10.7 BOOSTED VOLTAGES SWITCH 233
10.8 LEAKAGE RECOVERY CIRCUITS 236
BIBLIOGRAPHY 238
XII CONTENTS
11 SYNCHRONIZATION CIRCUITS 039
11.1 ATD ZZZZ"Z"Z'"Z 239
11.2 MULTIPLE ATD MANAGEMENT 241
11.3 LET'S CONNECT THE ATD TO THE BOOST CIRCUITRY 243
11.4 EQUALIZATION OF THE SENSE AMPLIFIER: SAEQ 245
11.4.1 WORD LINE OVERVOLTAGE: ONE SHOT BOOST 247
11.4.2 WORD LINE OVERVOLTASJE: CHARGE PUMP . 248
11.5 THE ENDREAD SIGNAL T .'""." 250
11.6 THE CELLS USED BY THE DUMMY SENSE AMPLIFIERS 25^
11.7 ATD - ENDREAD OVERLAP ".'""252
11.8 SEQUENTIAL READS 253
11.8.1 ASYNCHRONOUS PAGE MODE 255
11.8.2 THE SYNCHRONOUS BURST MODE 257
BIBLIOGRAPHY 9^7
12 READING CIRCUITS 269
12.1 THE INVERTER APPROACH 269
12.2 DIFFERENTIAL READ WITH UNBALANCED LOAD 273
12.3 DIFFERENTIAL READING WITH CURRENT OFFSET 277
12.4 SEMI-PARALLEL REFERENCE CURRENT 279
12.5 TECHNIQUES TO SPEED UP READ 283
12.5.1 EQUALIZATION 283
12.5.2 PRECHARGE 286
12.5.3 CLAMPING OF THE MAT AND REF NODES 286
12.6 DIFFERENTIAL READ WITH CURRENT MIRROR. 287
12.7 THE FLASH CELL 'ZZZZZ. 289
12.8 READING AT LOW VDD [['.'.'.'.'.'.'.'.'.' 290
12.9 AMPLIFIED I/V CONVERTER 293
12.10 AMPLIFIED SEMI-PARALLEL REFERENCE 294
12.11 SIZING OF THE MAIN MIRROR 296
12.12 DYNAMIC ANALYSIS OF THE SENSE AMPLIFIER 298
12.13 PRECHARGE OF THE OUTPUT STAGE OF THE COMPARATOR 301
12.14 ISSUES OF THE REFERENCE 302
12.14.1 EPROM-LIKE REFERENCE """^"""""""!""""I 302
12.14.2 MINI-MATRIX 393
12.15 MIRRORED REFERENCE CURRENT 304
12.16 THE VERIFY OPERATION 305
12.16.1 ERASE 30^
12.16.2 PROGRAM 30G
BIBLIOGRAPHY 3QC)
13 MULTILEVEL READ 3,3
13.1 MULTILEVEL STORAGE ""^.".".'"" 313
13.2 CURRENT SENSING METHOD 315
13.3 MULTILEVEL PROGRAMMING 3[G
13.4 CURRENT/VOLTAGE REFERENCE NETWORK 319
13.5 VOLTAGE SENSING METHOD 322
CONTENTS XIII
13.6 SAMPLE & HOLD SENSE AMPUTIER 325
13.7 CLOSED-LOOP VOLTAGE SENSING 329
13.8 HIERARCHICAL ROW DECODING FOR MULTIPLE SENSING LOOPS 332
13.9 A/D CONVERSION 335
13.10 LOW POWER COMPARATOR 338
BIBLIOGRAPHY 340
14 PROGRAM AND ERASE ALGORITHMS 343
14.1 MEMORY ARCHITECTURE FROM THE PROGRAM-ERASE
FUNCTIONALITY POINT OF VIEW 343
14.2 USER COMMAND TO PROGRAM AND ERASE 346
14.3 PROGRAM ALGORITHM FOR BI-LEVEL MEMORIES 347
14.4 PROGRAM ALGORITHM FOR MULTILEVEL MEMORIES 351
14.5 ERASE ALGORITHM 356
14.6 TEST ALGORITHMS 359
BIBLIOGRAPHY 360
15 CIRCUITS USED IN PROGRAM AND ERASE OPERATIONS 361
15.1 INTRODUCTION 361
15.2 DUAL VOLTAGE DEVICES 362
15.3 CHARGE PUMPS 364
15.4 DIFFERENT TYPES OF CHARGE PUMPS 370
15.4.1 DICKSON PUMP BASED ON BIPOLAR DIODES 371
15.4.2 DICKSON PUMP BASED ON TRANSI.STOR-BASED DIODES 371
15.4.3 CHARGE PUMP BASED ON PASS TRANSISTORS 373
15.4.4 VOLTAGE DOUBLER 376
15.4.5 VOLTAGE TRIPLER 379
15.5 HIGH VOLTAGE LIMITER 381
15.6 CHARGE PUMPS FOR NEGATIVE VOLTAGES 383
15.7 VOLTAGE REGULATION PRINCIPLES 384
15.8 GATE VOLTAGE REGULATION 384
15.8.1 CIRCUIT STRUCTURE 384
15.8.2 FREQUENCY COMPENSATION 388
15.8.3 POSITIVE POWER SUPPLY REJECTION RATIO (PSRR) 396
15.8.4 PROGRAM GATE VOLTAGE 397
15.9 DRAIN VOLTAGE REGULATION AND TEMPERATURE DEPENDENCE 401
BIBLIOGRAPHY 406
16 HIGH-VOLTAGE MANAGEMENT SYSTEM 409
16.1 INTRODUCTION 409
16.2 SECTORS BIASING 409
16.3 LOCAL SECTOR SWITCH 414
16.4 STAND-BY MANAGEMENT 417
16.5 HIGH-VOLTAGE MANAGEMENT 423
16.5.1 ARCHITECTURE OVERVIEW 423
16.5.2 HIGH-VOLTAGE READ PATH 423
16.5.3 HIGH-VOLTAGE PROGRAM PATH 425
XIV CONTENTS
16.5.4 HIGH-VOLTAGE ERASE PATH
16.6 MODULATION EFFECTS
427
16.6.1 PROGRAM DRAIN VOLTAGEMODUELAETIOEN'.'.'.' FZ
16.6.2 BODY VOLTAGE MODULATION.
4
*
16.6.3 SOURCE VOLTAGE MODULATION. '*
BIBHOGRAPHY . 435
440
17 PROGRAM AND ERASE CONTROLLER
17.1 FSM CONTROLLER .'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'
443
17.2 STD CELL IMPLEMENTATION OFTHE FSM. TF^
17.3 PLA IMPLEMENTATION OFTHE FSM
17.4 MICROCONTROLLER.
445
BIBLIOSRAPHY 447
454
18 REDUNDANCY AND ERROR CORRECTION CODES
18.1 REDUNDANCY
4
-"
18.2 REDUNDANCY & READ PATH
455
18.3 YIELD 457
18.4 UPROMCELLS.'.'.'".'.'.'.'.'.'.'.'.'.'.'"".'.'.'.'.'
459
18.4.1 READ CIRCUITRY FOR THE UPROMCELLS TTT
IS S TU L
S
O
PPLY CIRCULTRY F
RTHE UPROM
CELLS.'.'.'.'.' 4S
8.5 THE FIRST READ AFTER POWER ON RESET. TL
18.6 ERROR CORRECTION CODES
/IJ
18.6.1 ELEMENTS OFCODINGTHEOERY.'.'.'.'.'.'.' VIL
18.6.2 A MEMORY WITH ECC
BIBHOGRAPHY . 475
478
19 THE OUTPUT BUFFER
19.1 INTRODUCTION.
481
19.2 NMOS OUTPUT BUFFER
481
19.3 A CMOS SUPER OUTPUT BUFFER F
4
|9.4 THE "HIGH VOLTAGE TOLERANCE-FEUE'Z:: F
R
{
OLZNN^NV^
SI§NAL CIRCUIT,
'
Y BY CO
'*ATION ""
OT TNE OUTPUT BUFTERS.
BIBLIOIZRAPHY 493
501
TEST MODES
20.1 INTRODUCTION
503
20.2 AN OVERVIEW ON TEST MODES
503
20.3 DMA TEST. 503
20.4 FAST DMA .'".'".'.'"."".'
505
20.5 OXIDE INTEGRITY TEST
507
BIBHOGRAPHY . 507
509
ESD& LATCH-UP
21.1 NOTES ON BIPOLAR TRANSISTORS
5
"
21.2 LATCH-UP 511
516
CONTENTS XV
21.3 BIPOLAR TRANSISTORS USED IN FLASH MEMORIES 518
21.4 DISTRIBUTION OF POWER SUPPLIES AND ESD PROTECTION NETWORK 520
BIBLIOGRAPHY 523
22 FROM SPECIFICATION ANALYSIS TO FLOORPLAN DEFINITION 525
22.1 INTRODUCTION 525
22.2 MATRIX ORGANIZATION 525
22.3 MATRIX ROW DIMENSIONING 530
22.4 DIMENSIONING THE SECTORS 533
22.5 MEMORY CONFIGURATIONS 535
22.6 ORGANIZATION OF COLUMN DECODING 536
22.7 REDUNDANCY 538
22.8 FIRST CONSIDERATIONS ON READ MODE 540
22.9 ARCHITECTURE OF THE REFERENCE 542
22.10 READ PROBLEMS FOR A NON-STATIC MEMORY 543
22.11 ERASE AND PROGRAM CIRCUITS 544
22.12 PADPLACEMENT 547
22.13 CONTROL LOGIC AND RELATED CIRCUITRY 549
BIBLIOGRAPHY 550
23 PHOTOALBUM 551
23.1 INTRODUCTION 551
23.2 FIGURES INDEX 551
23.3 THE PHOTOS 552
SUBJECT INDEX 575 |
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| author | Campardo, Giovanni Micheloni, Rino Novosel, David |
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| id | DE-604.BV020050452 |
| illustrated | Illustrated |
| indexdate | 2024-11-27T09:00:32Z |
| institution | BVB |
| isbn | 354020198X |
| language | English |
| lccn | 004116726 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013371392 |
| oclc_num | 57333062 |
| open_access_boolean | |
| owner | DE-1043 DE-29T |
| owner_facet | DE-1043 DE-29T |
| physical | XXVIII, 581 S. Ill., graph. Darst. |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | Springer |
| record_format | marc |
| spelling | Campardo, Giovanni Verfasser aut VLSI-design of non-volatile memories Giovanni Campardo ; Rino Micheloni ; David Novosel Berlin [u.a.] Springer 2005 XXVIII, 581 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Integrated circuits Very large scale integration Nichtflüchtiger Speicher (DE-588)4728810-3 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Nichtflüchtiger Speicher (DE-588)4728810-3 s DE-604 Micheloni, Rino Verfasser aut Novosel, David Verfasser aut DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013371392&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Campardo, Giovanni Micheloni, Rino Novosel, David VLSI-design of non-volatile memories Integrated circuits Very large scale integration Nichtflüchtiger Speicher (DE-588)4728810-3 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4728810-3 (DE-588)4117388-0 |
| title | VLSI-design of non-volatile memories |
| title_auth | VLSI-design of non-volatile memories |
| title_exact_search | VLSI-design of non-volatile memories |
| title_full | VLSI-design of non-volatile memories Giovanni Campardo ; Rino Micheloni ; David Novosel |
| title_fullStr | VLSI-design of non-volatile memories Giovanni Campardo ; Rino Micheloni ; David Novosel |
| title_full_unstemmed | VLSI-design of non-volatile memories Giovanni Campardo ; Rino Micheloni ; David Novosel |
| title_short | VLSI-design of non-volatile memories |
| title_sort | vlsi design of non volatile memories |
| topic | Integrated circuits Very large scale integration Nichtflüchtiger Speicher (DE-588)4728810-3 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Integrated circuits Very large scale integration Nichtflüchtiger Speicher VLSI |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013371392&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT campardogiovanni vlsidesignofnonvolatilememories AT michelonirino vlsidesignofnonvolatilememories AT novoseldavid vlsidesignofnonvolatilememories |