Computer organization and architecture: designing for performance
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ
Pearson Education
2006
|
| Ausgabe: | 7. ed. |
| Schriftenreihe: | The William Stallings books on computer and data communications technology
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturverz. S. 751 - 762 |
| Beschreibung: | XIV, 778 S. graph. Darst. |
| ISBN: | 0131856448 |
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Datensatz im Suchindex
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|---|---|
| adam_text | Titel: Computer organization and architecture
Autor: Stallings, William
Jahr: 2006
Contents
Web Site for the Book iv
Preface xi
Chapter 0 Reader s Guide 1
0.1 Outline of the Book 2
0.2 Internet and Web Resources 2
PART ONE OVERVIEW 5
Chapter 1 Introduction 6
1.1 Organization and Architecture 7
1.2 Structure and Function 8
1.3 Why Study Computer Organization and Architecture? 15
Chapter 2 Computer Evolution and Performance 16
2.1 A Brief History of Computers 17
2.2 Designing for Performance 38
2.3 Pentium and PowerPC Evolution 45
2.4 Recommended Reading and Web Sites 48
2.5 Key Terms, Review Questions, and Problems 50
PART TWO THE COMPUTER SYSTEM 53
Chapter 3 A Top-Lcvel View of Computer Function
and Interconnection 55
3.1 Computer Components 57
3.2 Computer Function 59
3.3 Interconnection Structures 73
3.4 Bus Interconnection 75
3.5 PCI 84
3.6 Recommended Reading and Web Sites 94
3.7 Key Terms, Review Questions, and Problems 94
Appendix 3A Timing Diagrams 98
Chapter 4 Cache Memory 100
4.1 Computer Memory System Overview 101
4.2 Cache Memory Principles 108
4.3 Elements of Cache Design 111
4.4 Pentium 4 and PowerPC Cache Organizations 127
4.5 Recommended Reading 131
4.6 Key Terms, Review Questions, and Problems 132
Appendix 4A Performance Characteristics ofTwo-Level Memories 137
Chapter 5 Internal Memory 144
5.1 Semiconductor Main Memory 145
5.2 Error Correction 154
vi CONTENTS
5.3 Advanced DRAM Organization 159
5.4 Recommended Reading and Web Sites 164
5.5 Key Terms, Review Questions, and Problems 165
Chapter 6 External Memory 169
6.1 Magnetic Disk 170
6.2 RAID 179
6.3 Optical Memory 188
6.4 Magnetic Tape 194
6.5 Recommended Reading and Web Sites 196
6.6 Key Terms, Review Questions, and Problems 197
Chapter 7 Input/Output 200
7.1 External Devices 202
7.2 I/O Modules 206
7.3 Programmed I/O 209
7.4 Interrupt-Driven I/O 212
7.5 Direct Memory Access 221
7.6 I/O Channels and Processors 227
7.7 The External Interface: FireWire and InfiniBand 229
7.8 Recommended Reading and Web Sites 238
7.9 Key Terms, Review Questions, and Problems 239
Chapter 8 Operating System Support 243
8.1 Operating System Overview 244
8.2 Scheduling 255
8.3 Memory Management 262
8.4 Pentium II and PowerPC Memory Management 273
8.5 Recommended Reading and Web Sites 281
8.6 Key Terms, Review Questions, and Problems 282
PART THREE THE CENT RAL PROCESSING UNIT 286
Chapter 9 Computer Arithmetic 289
9.1 The Arithmetic and Logic Unit 290
9.2 Integer Representation 291
9.3 Integer Arithmetic 296
9.4 Floating-Point Representation 312
9.5 Floating-Point Arithmetic 317
9.6 Recommended Reading and Web Sites 328
9.7 Key Terms, Review Questions, and Problems 329
Chapter 10 Instruction Sets: Characteristics and Functions 334
10.1 Machine Instruction Characteristics 336
10.2 Types of Operands 342
10.3 Pentium and PowerPC Data Types 344
10.4 Types of Operations 347
10.5 Pentium and PowerPC: Operation Types 359
10.6 Assembly Language 369
CONTENTS vii
10.7 Recommended Reading 371
10.8 Key Terms, Review Questions, and Problems 371
Appendix 10A Stacks 377
Appendix 10B Little-, Big-, and Bi-Endian 381
Chapter 11 Instruction Sets: Addressing Modes and Formats 386
11.1 Addressing 387
11.2 Pentium and PowerPC Addressing Modes 394
11.3 Instruction Formats 399
11.4 Pentium and PowerPC] Instruction Formats 407
11.5 Recommended Reading 411
11.6 Key Terms, Review Questions, and Problems 411
Chapter 12 Processor Structure and Function 415
12.1 Processor Organization 416
12.2 Register Organization 418
12.3 Instruction Cycle 423
12.4 Instruction Pipelining 427
12.5 The Pentium Processor 441
12.6 The PowerPC Processor 449
12.7 Recommended Reading 455
12.8 Key Terms, Review Questions, and Problems 456
Chapter 13 Reduced Instruction Set Computers 460
13.1 Instruction Execution Characteristics 462
13.2 The Use of a Large Register File 467
13.3 Compiler-Based Register Optimization 472
13.4 Reduced Instruction Set Architecture 474
13.5 RISC Pipelining 480
13.6 MIPS R4000 483
13.7 SPARC 490
13.8 RISC versus CISC Controversy 495
13.9 Recommended Reading 496
13.10 KeyTerms, Review Questions, and Problems 497
Chapter 14 Instruction-Level Parallelism and Superscalar Processors 500
14.1 Overview 502
14.2 Design Issues 506
14.3 Pentium 515
14.4 PowerPC 521
14.5 Recommended Reading 529
14.6 KeyTerms, Review Questions, and Problems 530
Chapter 15 The IA-64 Architecture 535
15.1 Motivation 537
15.2 General Organization 538
15.3 Predication, Speculation, and Software Pipelining 540
15.4 IA-64 Instruction Set Architecture 556
viii CONTENTS
15.5 Itanium Organization 562
15.6 Recommended Reading and Web Sites 565
15.7 Key Terms, Review Questions, and Problems 566
PART FOUR THE CONTROL UNIT 569
Chapter 16 Control Unit Operation 571
16.1 Micro-Operations 573
16.2 Control of the Processor 579
16.3 Hardwired Implementation 591
16.4 Recommended Reading 594
16.5 Key Terms, Review Questions, and Problems 594
Chapter 17 Microprogrammed Control 596
17.1 Basic Concepts 597
17.2 Microinstruction Sequencing 606
17.3 Microinstruction Execution 612
17.4 TI 8800 624
17.5 Recommended Reading 634
17.6 Key Terms, Review Questions, and Problems 635
PARI FIV I- PARALLEL ORGANIZATION 637
Chapter 18 Parallel Processing 638
18.1 Multiple Processor Organizations 640
18.2 Symmetric Multiprocessors 642
18.3 Cache Coherence and the MESI Protocol 650
18.4 Multithreading and Chip Multiprocessors 656
18.5 (dusters 663
18.6 Nonuniform Memory Access 669
18.7 Vector Computation 673
18.8 Recommended Reading and Web Site 686
18.9 Key Terms, Review Questions, and Problems 687
Appendix A Number Systems 693
A.l The Decimal System 694
A.2 The Binary System 694
A.3 Converting between Binary and Decimal 695
A.4 Hexadecimal Notation 697
A.5 Problems 699
Appendix B Digital Logic 700
U. 1 Boolean Algebra 701
11.2 Gates 703
11.3 Combinational Circuits 705
11.4 Sequential Circuits 726
B.5 Recommended Reading and Web Site 735
B.6 Problems 735
Appendix C Projects for Teaching Computer
Organization and Architecture 738
C.l Research Projects 739
C.2 Simulation Projects 739
C.3 Reading/Report Assignments 740
Glossary 741
References 751
Index 763
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| spelling | Stallings, William 1945- Verfasser (DE-588)130436461 aut Computer organization and architecture designing for performance William Stallings 7. ed. Upper Saddle River, NJ Pearson Education 2006 XIV, 778 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier The William Stallings books on computer and data communications technology Literaturverz. S. 751 - 762 Architecture des ordinateurs ram Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 s DE-604 HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013328735&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
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| title | Computer organization and architecture designing for performance |
| title_auth | Computer organization and architecture designing for performance |
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| title_full | Computer organization and architecture designing for performance William Stallings |
| title_fullStr | Computer organization and architecture designing for performance William Stallings |
| title_full_unstemmed | Computer organization and architecture designing for performance William Stallings |
| title_short | Computer organization and architecture |
| title_sort | computer organization and architecture designing for performance |
| title_sub | designing for performance |
| topic | Architecture des ordinateurs ram Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Architecture des ordinateurs Computerarchitektur |
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