Chip design for submicron VLSI: CMOS layout and simulation
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Toronto, Ontario
Thomson
2006
|
| Schlagworte: | |
| Beschreibung: | XVI, 411 S. graph. Darst. 1 CD-ROM (12 cm) |
| ISBN: | 053446629X |
Internformat
MARC
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Datensatz im Suchindex
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| author | Uyemura, John Paul |
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| id | DE-604.BV019936768 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:08:44Z |
| institution | BVB |
| isbn | 053446629X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013224244 |
| oclc_num | 58958678 |
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| physical | XVI, 411 S. graph. Darst. 1 CD-ROM (12 cm) |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Thomson |
| record_format | marc |
| spelling | Uyemura, John Paul Verfasser aut Chip design for submicron VLSI CMOS layout and simulation John P. Uyemura Toronto, Ontario Thomson 2006 XVI, 411 S. graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Microwind Integrated circuits Very large scale integration Design and construction Metal oxide semiconductors, Complementary Design and construction CMOS (DE-588)4010319-5 gnd rswk-swf CMOS (DE-588)4010319-5 s DE-604 |
| spellingShingle | Uyemura, John Paul Chip design for submicron VLSI CMOS layout and simulation Microwind Integrated circuits Very large scale integration Design and construction Metal oxide semiconductors, Complementary Design and construction CMOS (DE-588)4010319-5 gnd |
| subject_GND | (DE-588)4010319-5 |
| title | Chip design for submicron VLSI CMOS layout and simulation |
| title_auth | Chip design for submicron VLSI CMOS layout and simulation |
| title_exact_search | Chip design for submicron VLSI CMOS layout and simulation |
| title_full | Chip design for submicron VLSI CMOS layout and simulation John P. Uyemura |
| title_fullStr | Chip design for submicron VLSI CMOS layout and simulation John P. Uyemura |
| title_full_unstemmed | Chip design for submicron VLSI CMOS layout and simulation John P. Uyemura |
| title_short | Chip design for submicron VLSI |
| title_sort | chip design for submicron vlsi cmos layout and simulation |
| title_sub | CMOS layout and simulation |
| topic | Microwind Integrated circuits Very large scale integration Design and construction Metal oxide semiconductors, Complementary Design and construction CMOS (DE-588)4010319-5 gnd |
| topic_facet | Microwind Integrated circuits Very large scale integration Design and construction Metal oxide semiconductors, Complementary Design and construction CMOS |
| work_keys_str_mv | AT uyemurajohnpaul chipdesignforsubmicronvlsicmoslayoutandsimulation |