Layout-basiertes Retiming für FPGAs:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | German |
| Veröffentlicht: |
2005
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| Schlagworte: | |
| Beschreibung: | München, Techn. Univ., Diss., 2005 |
| Beschreibung: | IV, 124 S. graph. Darst. |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV019867664 | ||
| 003 | DE-604 | ||
| 005 | 20060425 | ||
| 007 | t | ||
| 008 | 050701s2005 d||| m||| 00||| ger d | ||
| 035 | |a (OCoLC)255297869 | ||
| 035 | |a (DE-599)BVBBV019867664 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a ger | |
| 049 | |a DE-91 |a DE-12 | ||
| 100 | 1 | |a Seidl, Ulrich |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Layout-basiertes Retiming für FPGAs |c Ulrich Seidl |
| 264 | 1 | |c 2005 | |
| 300 | |a IV, 124 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a München, Techn. Univ., Diss., 2005 | ||
| 650 | 0 | 7 | |a Digitalschaltung |0 (DE-588)4012295-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logiksynthese |0 (DE-588)4348178-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Retiming |0 (DE-588)4760731-2 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | 1 | |a Digitalschaltung |0 (DE-588)4012295-5 |D s |
| 689 | 0 | 2 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | 3 | |a Logiksynthese |0 (DE-588)4348178-4 |D s |
| 689 | 0 | 4 | |a Retiming |0 (DE-588)4760731-2 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-013192038 | ||
Datensatz im Suchindex
| _version_ | 1804133390794883072 |
|---|---|
| any_adam_object | |
| author | Seidl, Ulrich |
| author_facet | Seidl, Ulrich |
| author_role | aut |
| author_sort | Seidl, Ulrich |
| author_variant | u s us |
| building | Verbundindex |
| bvnumber | BV019867664 |
| ctrlnum | (OCoLC)255297869 (DE-599)BVBBV019867664 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01399nam a2200397 c 4500</leader><controlfield tag="001">BV019867664</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20060425 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">050701s2005 d||| m||| 00||| ger d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)255297869</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV019867664</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">ger</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-12</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Seidl, Ulrich</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Layout-basiertes Retiming für FPGAs</subfield><subfield code="c">Ulrich Seidl</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2005</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">IV, 124 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">München, Techn. Univ., Diss., 2005</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitalschaltung</subfield><subfield code="0">(DE-588)4012295-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logiksynthese</subfield><subfield code="0">(DE-588)4348178-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Retiming</subfield><subfield code="0">(DE-588)4760731-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Digitalschaltung</subfield><subfield code="0">(DE-588)4012295-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="3"><subfield code="a">Logiksynthese</subfield><subfield code="0">(DE-588)4348178-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="4"><subfield code="a">Retiming</subfield><subfield code="0">(DE-588)4760731-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-013192038</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV019867664 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:07:57Z |
| institution | BVB |
| language | German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013192038 |
| oclc_num | 255297869 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-12 |
| owner_facet | DE-91 DE-BY-TUM DE-12 |
| physical | IV, 124 S. graph. Darst. |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| record_format | marc |
| spelling | Seidl, Ulrich Verfasser aut Layout-basiertes Retiming für FPGAs Ulrich Seidl 2005 IV, 124 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier München, Techn. Univ., Diss., 2005 Digitalschaltung (DE-588)4012295-5 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Logiksynthese (DE-588)4348178-4 gnd rswk-swf Retiming (DE-588)4760731-2 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Entwurfsautomation (DE-588)4312536-0 s Digitalschaltung (DE-588)4012295-5 s Field programmable gate array (DE-588)4347749-5 s Logiksynthese (DE-588)4348178-4 s Retiming (DE-588)4760731-2 s DE-604 |
| spellingShingle | Seidl, Ulrich Layout-basiertes Retiming für FPGAs Digitalschaltung (DE-588)4012295-5 gnd Field programmable gate array (DE-588)4347749-5 gnd Entwurfsautomation (DE-588)4312536-0 gnd Logiksynthese (DE-588)4348178-4 gnd Retiming (DE-588)4760731-2 gnd |
| subject_GND | (DE-588)4012295-5 (DE-588)4347749-5 (DE-588)4312536-0 (DE-588)4348178-4 (DE-588)4760731-2 (DE-588)4113937-9 |
| title | Layout-basiertes Retiming für FPGAs |
| title_auth | Layout-basiertes Retiming für FPGAs |
| title_exact_search | Layout-basiertes Retiming für FPGAs |
| title_full | Layout-basiertes Retiming für FPGAs Ulrich Seidl |
| title_fullStr | Layout-basiertes Retiming für FPGAs Ulrich Seidl |
| title_full_unstemmed | Layout-basiertes Retiming für FPGAs Ulrich Seidl |
| title_short | Layout-basiertes Retiming für FPGAs |
| title_sort | layout basiertes retiming fur fpgas |
| topic | Digitalschaltung (DE-588)4012295-5 gnd Field programmable gate array (DE-588)4347749-5 gnd Entwurfsautomation (DE-588)4312536-0 gnd Logiksynthese (DE-588)4348178-4 gnd Retiming (DE-588)4760731-2 gnd |
| topic_facet | Digitalschaltung Field programmable gate array Entwurfsautomation Logiksynthese Retiming Hochschulschrift |
| work_keys_str_mv | AT seidlulrich layoutbasiertesretimingfurfpgas |