Internformat
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV019838054 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 050608s2003 xxu |||| 00||| eng d | ||
| 020 | |a 8129700921 |9 81-297-0092-1 | ||
| 035 | |a (OCoLC)634436506 | ||
| 035 | |a (DE-599)BVBBV019838054 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 044 | |a xxu |c US | ||
| 049 | |a DE-858 | ||
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 100 | 1 | |a Palnitkar, Samir |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Verilog HDL |b a guide to digital design and synthesis |c Samir Palnitkar |
| 264 | 1 | |a Singapore |b Pearson |c 2003 | |
| 300 | |a 492 S.+ |e 1 CD-ROM (12 cm) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-013163005 | ||
Datensatz im Suchindex
| _version_ | 1804133347523297280 |
|---|---|
| any_adam_object | |
| author | Palnitkar, Samir |
| author_facet | Palnitkar, Samir |
| author_role | aut |
| author_sort | Palnitkar, Samir |
| author_variant | s p sp |
| building | Verbundindex |
| bvnumber | BV019838054 |
| classification_rvk | ST 250 |
| ctrlnum | (OCoLC)634436506 (DE-599)BVBBV019838054 |
| discipline | Informatik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00914nam a2200313zc 4500</leader><controlfield tag="001">BV019838054</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">050608s2003 xxu |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">8129700921</subfield><subfield code="9">81-297-0092-1</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)634436506</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV019838054</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxu</subfield><subfield code="c">US</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-858</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Palnitkar, Samir</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Verilog HDL</subfield><subfield code="b">a guide to digital design and synthesis</subfield><subfield code="c">Samir Palnitkar</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Singapore</subfield><subfield code="b">Pearson</subfield><subfield code="c">2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">492 S.+</subfield><subfield code="e">1 CD-ROM (12 cm)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-013163005</subfield></datafield></record></collection> |
| id | DE-604.BV019838054 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T20:07:16Z |
| institution | BVB |
| isbn | 8129700921 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013163005 |
| oclc_num | 634436506 |
| open_access_boolean | |
| owner | DE-858 |
| owner_facet | DE-858 |
| physical | 492 S.+ 1 CD-ROM (12 cm) |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Pearson |
| record_format | marc |
| spelling | Palnitkar, Samir Verfasser aut Verilog HDL a guide to digital design and synthesis Samir Palnitkar Singapore Pearson 2003 492 S.+ 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 |
| spellingShingle | Palnitkar, Samir Verilog HDL a guide to digital design and synthesis VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Verilog HDL a guide to digital design and synthesis |
| title_auth | Verilog HDL a guide to digital design and synthesis |
| title_exact_search | Verilog HDL a guide to digital design and synthesis |
| title_full | Verilog HDL a guide to digital design and synthesis Samir Palnitkar |
| title_fullStr | Verilog HDL a guide to digital design and synthesis Samir Palnitkar |
| title_full_unstemmed | Verilog HDL a guide to digital design and synthesis Samir Palnitkar |
| title_short | Verilog HDL |
| title_sort | verilog hdl a guide to digital design and synthesis |
| title_sub | a guide to digital design and synthesis |
| topic | VERILOG (DE-588)4268385-3 gnd |
| topic_facet | VERILOG |
| work_keys_str_mv | AT palnitkarsamir veriloghdlaguidetodigitaldesignandsynthesis |