Design automation for massively parallel processor arrays: transforming regular algorithms to reconfigurable hardware
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin
Köster
2005
|
| Ausgabe: | 1. Aufl. |
| Schlagworte: | |
| Beschreibung: | VIII, 254 S. graph. Darst. 210 mm x 148 mm |
| ISBN: | 389574557X |
Internformat
MARC
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| 020 | |a 389574557X |c Pb. : EUR 29.80 |9 3-89574-557-X | ||
| 024 | 3 | |a 9783895745577 | |
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| 100 | 1 | |a Bednara, Marcus |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Design automation for massively parallel processor arrays |b transforming regular algorithms to reconfigurable hardware |c Marcus Bednara |
| 250 | |a 1. Aufl. | ||
| 264 | 1 | |a Berlin |b Köster |c 2005 | |
| 300 | |a VIII, 254 S. |b graph. Darst. |c 210 mm x 148 mm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 502 | |a Zugl.: Erlangen-Nürnberg., Univ., Diss., 2004 | ||
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Massive Parallelität |0 (DE-588)4324752-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Systolisches Array |0 (DE-588)4212939-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-013161679 | ||
Datensatz im Suchindex
| _version_ | 1804133345529954304 |
|---|---|
| any_adam_object | |
| author | Bednara, Marcus |
| author_facet | Bednara, Marcus |
| author_role | aut |
| author_sort | Bednara, Marcus |
| author_variant | m b mb |
| building | Verbundindex |
| bvnumber | BV019836700 |
| classification_rvk | ST 190 |
| ctrlnum | (OCoLC)76740840 (DE-599)BVBBV019836700 |
| discipline | Informatik |
| edition | 1. Aufl. |
| format | Thesis Book |
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| genre_facet | Hochschulschrift |
| id | DE-604.BV019836700 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:07:14Z |
| institution | BVB |
| isbn | 389574557X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013161679 |
| oclc_num | 76740840 |
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| owner | DE-29 DE-29T DE-11 |
| owner_facet | DE-29 DE-29T DE-11 |
| physical | VIII, 254 S. graph. Darst. 210 mm x 148 mm |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | Köster |
| record_format | marc |
| spelling | Bednara, Marcus Verfasser aut Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware Marcus Bednara 1. Aufl. Berlin Köster 2005 VIII, 254 S. graph. Darst. 210 mm x 148 mm txt rdacontent n rdamedia nc rdacarrier Zugl.: Erlangen-Nürnberg., Univ., Diss., 2004 VHDL (DE-588)4254792-1 gnd rswk-swf Massive Parallelität (DE-588)4324752-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Systolisches Array (DE-588)4212939-4 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Entwurfsautomation (DE-588)4312536-0 s VLSI (DE-588)4117388-0 s Systolisches Array (DE-588)4212939-4 s Massive Parallelität (DE-588)4324752-0 s Field programmable gate array (DE-588)4347749-5 s VHDL (DE-588)4254792-1 s DE-604 |
| spellingShingle | Bednara, Marcus Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware VHDL (DE-588)4254792-1 gnd Massive Parallelität (DE-588)4324752-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd Systolisches Array (DE-588)4212939-4 gnd Field programmable gate array (DE-588)4347749-5 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4254792-1 (DE-588)4324752-0 (DE-588)4312536-0 (DE-588)4212939-4 (DE-588)4347749-5 (DE-588)4117388-0 (DE-588)4113937-9 |
| title | Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware |
| title_auth | Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware |
| title_exact_search | Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware |
| title_full | Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware Marcus Bednara |
| title_fullStr | Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware Marcus Bednara |
| title_full_unstemmed | Design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware Marcus Bednara |
| title_short | Design automation for massively parallel processor arrays |
| title_sort | design automation for massively parallel processor arrays transforming regular algorithms to reconfigurable hardware |
| title_sub | transforming regular algorithms to reconfigurable hardware |
| topic | VHDL (DE-588)4254792-1 gnd Massive Parallelität (DE-588)4324752-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd Systolisches Array (DE-588)4212939-4 gnd Field programmable gate array (DE-588)4347749-5 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | VHDL Massive Parallelität Entwurfsautomation Systolisches Array Field programmable gate array VLSI Hochschulschrift |
| work_keys_str_mv | AT bednaramarcus designautomationformassivelyparallelprocessorarraystransformingregularalgorithmstoreconfigurablehardware |