Essentials of computer architecture:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ
Pearson Prentice Hall
2005
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXIII, 369 S. graph. Darst. |
| ISBN: | 0131491792 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV019804159 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 050509s2005 d||| |||| 00||| eng d | ||
| 020 | |a 0131491792 |9 0-13-149179-2 | ||
| 035 | |a (OCoLC)56722938 | ||
| 035 | |a (DE-599)BVBBV019804159 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-20 |a DE-573 |a DE-473 |a DE-703 |a DE-739 |a DE-83 |a DE-188 |a DE-11 |a DE-523 | ||
| 050 | 0 | |a QA76.9.A73 | |
| 082 | 0 | |a 004.22 |2 22 | |
| 084 | |a ST 150 |0 (DE-625)143594: |2 rvk | ||
| 100 | 1 | |a Comer, Douglas |d 1949- |e Verfasser |0 (DE-588)12274926X |4 aut | |
| 245 | 1 | 0 | |a Essentials of computer architecture |c Douglas E. Comer |
| 264 | 1 | |a Upper Saddle River, NJ |b Pearson Prentice Hall |c 2005 | |
| 300 | |a XXIII, 369 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Computer architecture | |
| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Computerarchitektur |0 (DE-588)4048717-9 |D s |
| 689 | 0 | |5 DE-604 | |
| 856 | 4 | 2 | |m Digitalisierung UB Passau |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013129682&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-013129682 | ||
Datensatz im Suchindex
| _version_ | 1804133299043434496 |
|---|---|
| adam_text | Contents
Preface
xxi
Chapter
1
Introduction And Overview
1.1
The Importance Of Architecture
1
1.2
Learning The Essentials
1
1.3
Organization Of The Text
2
1.4
What We Will Omit
3
7.5
Terminology: Architecture And Design
1.6
Summary
3
PARTI Basics
Chapter
2
Fundamentals Of Digital Logic
2.1
Introduction
7
2.2
Electrical Terminology: Voltage And Current
7
2.3
The Transistor
8
2.4
Logic Gates
9
2.5
Symbols Used For Gates
10
2.6
Construction Of Gates From Transistors
11
2.7
Example Interconnection Of Gates
12
2.8
Multiple Gates Per Integrated Circuit
14
2.9
The Need For More Than Combinatorial Circuits
15
2.10
Circuits That Maintain State
15
2.77
Transition Diagrams
16
2.72
Binary Counters
17
2.7
J
Clocks And Sequences
18
2.14
The Important Concept Of Feedback
20
2.75
Starting A Sequence
22
2.16
Iteration In Software Vs. Replication In Hardware
22
2.77
Gate And Chip Minimization
23
2.18
Using Spare Gates
24
2.19
Power
Distribution And Heat
Dissipation
24
2.20
Timing
25
2.21
Physical Size And Process Technologies
26
2.22
Circuit Boards And Layers
27
2.23
Levels Of Abstraction
27
2.24
Summary
28
Chapter
3
Data And Program Representation
29
3.1
Introduction
29
3.2
Digital Logic And Abstraction
29
3.3
Bits And Bytes
30
3.4
Byte Size And Possible Values
30
5.5
Binary Arithmetic
31
3.6
Hexadecimal Notation
32
3.7
Notation For Hexadecimal And Binary Constants
33
3.8
Character Sets
34
3.9
Unicode
35
3.10
Unsigned Integers, Overflow, And Underflow
35
3.11
Numbering Bits And Bytes
36
3.12
Signed Integers
37
5.75
An Example Of Two s Complement Numbers
38
3.74
Sign Extension
39
5.75
Floatingpoint
40
3.76
Specia/
Уа/иеѕ
42
3.77
Range Of IEEE Floating Point Values
42
3.7
S Data
Aggregates
42
3.79
Program Representation
43
5.20
Summary
43
PART II Processors
Chapter
4
The Variety Of Processors And Computational Engines
47
4.7
Introduction
47
4.2 Von
Neumann Architecture
47
4.5
Definition Of A Processor
48
4.4
77ге
Range Of Processors
48
4.5
Hierarchical Structure And Computational Engines
49
4.6
Structure Of A Conventional Processor
51
4.7
Definition Of An Arithmetic Logic Unit
(ALU) 52
4.8
Processor
Categories And
Roles
52
4.9
Processor Technologies
54
4.10
Stored Programs
54
4.11
The Fetch-Execute Cycle
55
4.12
Clock Rate And Instruction Rate
56
4.13
Control: Getting Started And Stopping
57
4.14
Starting The Fetch-Execute Cycle
57
4.15
Summary
58
Chapter
5
Processor Types And Instruction Sets
61
5.7
Introduction
61
5.2
Mathematical Power, Convenience, And Cost
61
5.3
Instruction Set And Representation
62
5.4
Opcodes, Operands, And Results
63
5.5
Typical Instruction Format
63
5.6
Variable-Length Vs. Fixed-Length Instructions
63
5.7
General-Purpose Registers
64
5.8
Floating Point Registers And Register Identification
65
5.9
Programming With Registers
65
5.10
Register Banks
66
5.11
Complex And Reduced Instruction Sets
67
5.72
RISC Design And The Execution Pipeline
68
5.75
Pipelines And Instruction Stalls
69
5.74
Other Causes Of Pipeline Stalls
71
5.75
Consequences For Programmers
71
5.76
Programming, Stalls, And No-Op Instructions
72
5.77
Forwarding
72
5.78
Types Of Operations
13
5.19
Program Counter, Fetch-Execute, And Branching
73
5.20
Subroutine Calls, Arguments, And Register Windows
75
5.27
Аи
Example Instruction Set
76
5.22
Minimalistic Instruction Set
78
5.23
The Principle Of Orthogonality
79
5.24
Condition Codes And Conditional Branching
80
5.25
Summary
80
Chapter
6
Operand Addressing And Instruction Representation
83
6.7
Introduction
83
6.2
Zero,
0ие,
Two, Or
77irče
Address Designs
83
6.3
Zero Operands Per Instruction
84
6.4
One Operand Per Instruction
85
6.5
Two Operands Per Instruction
85
6.6
Three Operands Per Instruction
86
6.7
Operand Sources And Immediate Values
86
6.8
The
Von
Neumann Bottleneck
87
6.9
Explicit And Implicit Operand Encoding
88
6.70
Operands That Combine Multiple Values
89
6.
II Tradeoffs In The Choice Of Operands
90
6.12
Values In Memory And Indirect Reference
91
6.13
Operand Addressing Modes
92
6.14
Summary
93
Chapter
7
CPUs: Microcode, Protection, And Processor Modes
95
7.1
Introduction
95
7.2
A Central Processor
95
7.3
CPU Complexity
96
7.4
Modes Of Execution
97
7.5
Backward Compatibility
97
7.6
Changing Modes
98
7.7
Privilege And Protection
99
7.8
Multiple Levels Of Protection
99
7.9
Microcoded Instructions
100
7.10
Microcode Variations
102
7.11
The Advantage Of Microcode
102
7.12
Making Microcode Visible To Programmers
103
7.13
Vertical Microcode
103
7.14
Horizontal Microcode
104
7.75
Example Horizontal Microcode
105
7.76
A Horizontal Microcode Example
107
7.77
Operations That Require Multiple Cycles
108
7.7
S
Horizontal Microcode And Parallel Execution
109
7.79
Look-Ahead And High Performance Execution
110
7.20
Parallelism And Execution Order 111
7.27
Out-Of-Order Instruction Execution 111
7.22
Conditional Branches And Branch Prediction
112
7.23
Consequences For Programmers
113
7.24
Summary
113
Chapter
8
Assembly Languages And Programming Paradigm
115
8.1
Introduction
115
8.2
Characteristics Of A High-level Programming Language
115
8.3
Characteristics Of A Low-Level Programming Language
116
8.4
Assembly Language
117
8.5
Assembly Language Syntax And Opcodes
118
8.6
Operand Order
120
8.7
Register Names
121
8.8
Operand Types 111
8.9
Assembly Language Programming Paradigm And Idioms 111
8.10
Assembly Code For Conditional Execution
123
8.11
Assembly Code For A Conditional Alternative
114
8.12
Assembly Code For Definite Iteration
124
8.75
Assembly Code For Indefinite Iteration
125
8.14
Assembly Code For Procedure Invocation
125
8.75
Assembly Code For Parameterized Procedure Invocation
126
8.16
Consequence For Programmers
127
8.77
Assembly Code For Function Invocation
128
8.78
Interaction Between Assembly And High-Level Languages
128
8.79
Assembly Code For Variables And Storage
129
8.20
Two-Pass Assembler
130
8.27
Assembly Language Macros
131
8.22
Summary
134
PART III Memories
Chapter
9
Memory And Storage
137
9.1
Introduction
137
9.2
Definition
137
9.3
The Key Aspects Of Memory
138
9.4
Characteristics Of Memory Technologies
138
9.5
The Important Concept Of A Memory Hierarchy
140
9.6
Instruction And Data Store
140
9.7
The Fetch-Store Paradigm
141
9.8
Summary
141
Chapter
10
Physical Memory And Physical Addressing
143
10.1
Introduction
143
10.2
Characteristics Of Computer Memory
143
10.3
Static And Dynamic RAM Technologies
144
10.4
Measures Of Memory Technology
145
10.5
Density
146
10.6
Separation Of Read And Write Performance
146
70.7
Latency And Memory Controllers
146
10.8
Synchronized Memory Technologies
147
10.9
Multiple Data Rate Memory Technologies
148
70.70
Examples Of Memory Technologies
148
70.77
Memory Organization
148
70.72
Memory Access And Memory Bus
149
10.13
Memory Transfer Size
150
70.74
Physical Addresses And Words
150
70.75
Physical Memory Operations
150
70.76
Word Size And Other Data Types
151
70.77
An Extreme Case: Byte Addressing
151
10.18
Byte Addressing With Word Transfers
152
70.79
Using Powers Of Two
153
10.20
Byte Alignment And Programming
154
70.27
Memory Size And Address Space
154
70.22
Programming With Word Addressing
155
70.25
Measures Of Memory Size
155
70.24
Pointers And Data Structures
156
70.25
A Memory Dump
156
70.26
Indirection And Indirect Operands
158
7 0.2 7
Memory Banks And Interleaving
158
70.28
Content Addressable Memory
159
70.29
Ternary CAM
160
70.30
Summary
160
Chapter
11
Virtual Memory Technologies And Virtual Addressing
163
77.7
Introduction
163
77.2
Definition
163
77.
1
A Virtual Example: Byte Addressing
164
77.4
Virtual Memory Terminology
164
77.5
Аи
Interface To Multiple Physical Memory Systems
164
77.6
Address Translation Or Address Mapping
166
77.7
Avoiding Arithmetic Calculation
167
77.
S
Discontiguous Address Spaces
168
11.9
Other
Memory
Organizations
169
11.10
Motivation For Virtual Memory
169
11.11
Multiple Virtual Spaces And Multiprogramming
170
11.12
Multiple Levels Of Virtualization
171
11.13
Creating Virtual Spaces Dynamically
171
11.14
Base-Bound Registers 111
11.15
Changing The Virtual Space
172
11.16
Virtual Memory, Base-Bound, And Protection
173
11.17
Segmentation
174
11.18
Demand Paging
175
11.19
Hardware And Software For Demand Paging
175
11.20
Page Replacement
176
11.21
Paging Terminology And Data Structures
176
/7.22
Address Translation In A Paging System
177
11.23
Using Powers Of Two
178
11.24
Presence, Use, And Modified Bits
179
11.25
Page Table Storage
180
11.26
Paging Efficiency And A Translation Lookaside Buffer
181
11.27
Consequences For Programmers
182
11.28
Summary
183
Chapters Caches And Caching
185
12.1
Introduction
185
72.2
Definition
185
72.
J
Characteristics Of A Cache
186
72.4
The Importance Of Caching
187
72.5
Examples Of Caching
188
72.6
Cache Terminology
188
72.7
Best And Worst Case Cache Performance
189
72.5
Cache Performance On A Typical Sequence
190
72.9
Cacfte Replacement Policy
190
72.70
LRUReplacement
191
72.77
Multi-level Cache Hierarchy
191
72.72
Preloading Caches
192
7 2.7
J CflcÄes t/íďí/
Ш/г
Memory
192
72.74
TLBAsACache
193
72.75
Demand Paging As A Form Of Caching
193
72.76
Physical Memory Cache
194
72.77
Write Through And Write Back
194
72.78
Сас/ге
Coherence
195
12.19
LI, L2, and L3 Caches
196
72.20
Sizes Of LI, L2, And L3 Caches
197
12.21
Instruction And Data
Caches 197
12.22
Virtual Memory Caching And A Cache Flush
198
12.23
Implementation Of Memory Caching
199
12.24
Direct Mapping Memory Cache
200
12.25
Using Powers Of Two For Efficiency
201
12.26
Set Associative Memory Cache
202
72.27
Consequences For Programmers
203
12.28
Summary
204
PART IV I/O
Chapter
13
Input/Output Concepts And Terminology
207
13.1
Introduction
207
13.2
Input And Output Devices
207
13.3
Control Of An External Device
208
13.4
Data Transfer
209
13.5
Serial And Parallel Data Transfers
209
13.6
Self-Clocking Data
210
13.7
Full-Duplex And Half-Duplex Interaction
210
13.8
Interface Latency And Throughput
211
13.9
The Fundamental Idea Of Multiplexing
211
13.10
Multiple Devices Per External Interface
212
13.11
A Processor s View Of I/O
213
13.12
Summary
213
Chapter
14
Buses And Bus Architectures
215
14.1
Introduction
215
14.2
Definition Of A Bus
215
14.3
Processors, I/O Devices, And Buses
216
14.4
Proprietary And Standardized Buses
216
14.5
Shared Buses And An Access Protocol
217
14.6
Multiple Buses
217
14.7
A Parallel, Passive Mechanism
217
14.8
Physical Connections
217
14.9
Bus Interface
218
14.10
Address, Control, And Data Lines
219
74.11
The Fetch-Store Paradigm
220
14.12
Fetch-Store Over A Bus
220
74.75
The Width Of A Bus
220
14.14
Multiplexing
221
14.15
Bus Width And Size Of Data Items
222
14.16
Bus Address Space
223
14.17
Potential Errors
224
14.18
Address Configuration And Sockets
225
14.19
Many Buses Or One Bus
226
14.20
Using Fetch-Store With Devices
226
14.21
An Example Of Device Control Using Fetch-Store
226
14.22
Operation Of An Interface
227
14.23
Asymmetric Assignments
228
14.24
Unified Memory And Device Addressing
228
14.25
Holes In The Address Space
230
14.26
Address Map
230
74.27
Program Interface To A Bus
231
14.28
Bridging Between Two Buses
232
74.29
Main And Auxiliary Buses
232
14.30
Consequences For Programmers
234
14.31
Switching Fabrics
234
14.32
Summary
235
Chapter
15
Programmed And Interrupt-Driven I/O
237
75.7
Introduction
237
15.2
I/O Paradigms
237
15.3
Programmed I/O
238
15.4
Synchronization
238
75.5
Polling
239
75.6
Code For Polling
239
75.7
Control And Status Registers
241
75.8
Processor Use And Polling
241
75.9
FíVsí,
Second, And Third Generation Computers
242
75.70
Interrupt-Driven I/O
242
75.77
A Hardware Interrupt Mechanism
243
75.72
Interrupts And The Fetch-Execute Cycle
243
75.75
Handling An Interrupt
244
75.74
Interrupt Vectors
245
75.75
Initialization And Enabling And Disabling Interrupts
246
75.76
Preventing Interrupt Code From Being Interrupted
246
75.77
Multiple Levels Of Interrupts
246
75.78
Assignment Of Interrupt Vectors And Priorities
247
75.79
Dynamic Bus Connections And Pluggable Devices
248
75.20
The Advantage Of Interrupts
249
75.27
Smart Devices And Improved I/O Performance
249
15.22
Direct
Memory
Access
(DMA)
250
15.23
Buffer
Chaining
251
15.24
Scatter Read And Gather Write Operations
252
75.25
Operation Chaining
252
75.26
Summary
253
Chapter
16
A Programmer s View Of Devices, I/O, And Buffering
255
76.7
Introduction
255
76.2
Definition Of A Device Driver
256
76.
J
Device Independence, Encapsulation, And Hiding
256
16.4
Conceptual Parts Of A Device Driver
257
76.5
Two Types Of Devices
258
76.6
Example Flow Through A Device Driver
258
76.7
Queued Output Operations
259
16.8
Forcing An Interrupt
261
76.9
Queued Input Operations
261
76.70
Devices That Support Bi-Directional Transfer
262
76.77
Asynchronous Vs. Synchronous Programming Paradigm
263
76.72
Asynchrony, Smart Devices, And Mutual Exclusion
264
76.75
I/O As Viewed By An Application
264
16.14
Run-Time I/O Libraries
265
76.75
The Library/Operating System Dichotomy
266
16.16
I/O Operations The OS Supports
267
76.77
The Cost Of I/O Operations
268
16.18
Reducing The System Call Overhead
268
76.79
The Important Concept Of Buffering
269
76.20
Implementation of Buffering
270
76.27
Flushing A Buffer
271
76.22
Buffering On Input
272
16.23
Effectiveness Of Buffering
272
76.24
Buffering In An Operating System
273
76.25
Relation To Caching
274
76.26
An Example: The Unix Standard I/O Library
274
76.27
Summary
21
A
PART V Advanced Topics
Chapter
17
Parallelism
279
17.1
Introduction
279
17.2
Parallel And Pipelined Architectures
279
77.5
Characterizations Of Parallelism
280
17.4
Microscopic Vs. Macroscopic
280
17.5
Examples Of Microscopic Parallelism
281
17.6
Examples Of Macroscopic Parallelism
281
17.7
Symmetric Vs. Asymmetric
282
17.8
Fine-grain Vs. Coarse-grain Parallelism
282
17.9
Explicit Vs. Implicit Parallelism
283
17.10
Parallel Architectures
283
17.11
Types Of Parallel Architectures (Flynn Classification)
283
17.12
Single Instruction Single Data (SISD)
284
17.13
Single Instruction Multiple Data (SIMD)
284
17.14
Multiple Instructions Multiple Data (MIMD)
286
17.15
Communication, Coordination, And Contention
288
77.76
Performance Of Multiprocessors
290
77.77
Consequences For Programmers
292
7 7.7
S
Redundant Parallel Architectures
294
77.79
Distributed And Cluster Computers
295
77.20
Summary
296
Chapter
18
Pipelining
299
78.7
Introduction
299
18.2
The Concept Of Pipelining
299
18.3
Software Pipelining
301
18.4
Software Pipeline Performance And Overhead
302
18.5
Hardware Pipelining
303
75.6
How Hardware Pipelining Increases Performance
303
78.7
When Pipelining Can Be Used
306
18.8
The Conceptual Division Of Processing
307
18.9
Pipeline Architectures
307
78.70
Pipeline Setup, Stall, And Flush Times
308
78.77
Definition Of
Superpipeline
Architecture
308
78.72
Summary
309
Chapter
19
Assessing Performance
311
19.1
Introduction
311
19.2
Measuring Power And Performance
311
19.3
Measures Of Computational Power
312
19.4
Application Specific Instruction Counts
313
19.5
Instruction Mix
314
19.6
Standardized Benchmarks
315
19.7
I/O And Memory Bottlenecks
316
19.8
Boundary Between Hardware And Software
316
19.9
Choosing Items To Optimize
317
19.10
Amdahl
s
Law And Parallel Systems
317
19.11
Summary
318
Chapter
20
Architecture Examples And Hierarchy
319
20.7
Introduction
319
20.2
Architectural Levels
319
20.3
System-Level Architecture: A Personal Computer
320
20.4
Bus Interconnection And Bridging
321
20.5
Controller Chips And Physical Architecture
322
20.6
Virtual Buses
323
20.7
Connection Speeds
325
20.
б
Bridging Functionality And Virtual Buses
325
20.9
Board-Level Architecture
325
20.10
Chip-Level Architecture
327
20.
і і
Structure Of Functional Units On A Chip
328
20.72
Summary
329
20.75
Hierarchy Beyond Computer Architectures
329
Appendix
1
Lab Exercises For A Computer Architecture Course
331
A7.7 Introduction
331
A7.2 Digital Hardware For A Lab
332
A7.
J Solderless
Breadboard
332
A7.4
i/sing
A Solderless Breadboard
333
A7.5
Гєі/ш^
334
A7.6 Power And Ground Connections
334
A7.7
ІмЬ
Exercises
335
7
Introduction and account configuration
337
2
Digital Logic: Use of a breadboard
339
3
Digital Logic: Building an adder from gates
341
4
Digital Logic: Clocks and demultiplexing
343
5
Representation: Testing big endian vs. little endian
345
6
Representation: A hex dump program in
С ЪАП
7
Processors: Learn a RISC assembly language
349
8
Processors: Function that can be called from
С
351
9
Memory: row-major and column-major array storage
353
10
Input/Output: a buffered I/O library
355
11
A hex dump program in assembly language
357
Bibliography
359
Index
361
|
| any_adam_object | 1 |
| author | Comer, Douglas 1949- |
| author_GND | (DE-588)12274926X |
| author_facet | Comer, Douglas 1949- |
| author_role | aut |
| author_sort | Comer, Douglas 1949- |
| author_variant | d c dc |
| building | Verbundindex |
| bvnumber | BV019804159 |
| callnumber-first | Q - Science |
| callnumber-label | QA76 |
| callnumber-raw | QA76.9.A73 |
| callnumber-search | QA76.9.A73 |
| callnumber-sort | QA 276.9 A73 |
| callnumber-subject | QA - Mathematics |
| classification_rvk | ST 150 |
| ctrlnum | (OCoLC)56722938 (DE-599)BVBBV019804159 |
| dewey-full | 004.22 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.22 |
| dewey-search | 004.22 |
| dewey-sort | 14.22 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01357nam a2200349 c 4500</leader><controlfield tag="001">BV019804159</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">050509s2005 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0131491792</subfield><subfield code="9">0-13-149179-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)56722938</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV019804159</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-20</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-473</subfield><subfield code="a">DE-703</subfield><subfield code="a">DE-739</subfield><subfield code="a">DE-83</subfield><subfield code="a">DE-188</subfield><subfield code="a">DE-11</subfield><subfield code="a">DE-523</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">QA76.9.A73</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">004.22</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 150</subfield><subfield code="0">(DE-625)143594:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Comer, Douglas</subfield><subfield code="d">1949-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)12274926X</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Essentials of computer architecture</subfield><subfield code="c">Douglas E. Comer</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Upper Saddle River, NJ</subfield><subfield code="b">Pearson Prentice Hall</subfield><subfield code="c">2005</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXIII, 369 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer architecture</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung UB Passau</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013129682&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-013129682</subfield></datafield></record></collection> |
| id | DE-604.BV019804159 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:06:30Z |
| institution | BVB |
| isbn | 0131491792 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-013129682 |
| oclc_num | 56722938 |
| open_access_boolean | |
| owner | DE-20 DE-573 DE-473 DE-BY-UBG DE-703 DE-739 DE-83 DE-188 DE-11 DE-523 |
| owner_facet | DE-20 DE-573 DE-473 DE-BY-UBG DE-703 DE-739 DE-83 DE-188 DE-11 DE-523 |
| physical | XXIII, 369 S. graph. Darst. |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | Pearson Prentice Hall |
| record_format | marc |
| spelling | Comer, Douglas 1949- Verfasser (DE-588)12274926X aut Essentials of computer architecture Douglas E. Comer Upper Saddle River, NJ Pearson Prentice Hall 2005 XXIII, 369 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Computer architecture Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 s DE-604 Digitalisierung UB Passau application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013129682&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Comer, Douglas 1949- Essentials of computer architecture Computer architecture Computerarchitektur (DE-588)4048717-9 gnd |
| subject_GND | (DE-588)4048717-9 |
| title | Essentials of computer architecture |
| title_auth | Essentials of computer architecture |
| title_exact_search | Essentials of computer architecture |
| title_full | Essentials of computer architecture Douglas E. Comer |
| title_fullStr | Essentials of computer architecture Douglas E. Comer |
| title_full_unstemmed | Essentials of computer architecture Douglas E. Comer |
| title_short | Essentials of computer architecture |
| title_sort | essentials of computer architecture |
| topic | Computer architecture Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Computer architecture Computerarchitektur |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=013129682&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT comerdouglas essentialsofcomputerarchitecture |