Proceedings of the IEEE 1996 Custom Integrated Circuits Conference: Town and Country Hotel, San Diego, California, May 5 - 8, 1996
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| Sprache: | English |
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| Beschreibung: | 516 S Ill., graph. Darst. |
| ISBN: | 0780331176 0780331184 |
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| adam_text | Proceedings of the
IEEE 1996
CUSTOM INTEGRATED CIRCUITS
CONFERENCE
Fachbereichsbibliothek Informatik
Tl I Harm stadt
Town and Country Hotel May 5—8,1996
San Diego, California
The CICC ‘96 is sponsored by the IEEE Electron Devices Society with cooperation from the IEEE Solid State
Circuits Council Its goal is to provide a forum for manufacturers, circuit designers, CAD developers, and
users of ASICs to present and discuss exciting new developments, future trends, and innovative ideas
96CH35886
CONTENTS
TECHNICAL SESSIONS
SESSION 1—PRESIDIO ROOM
Monday Morning
8:00 WELCOME/OPENING REMARKS
Allen Barlow, General Chairman
Jake Buurma, Conference Chairman
8:10 CCIC 96 - TECHNICAL PROGRAM
Robert Cordell, Technical Program Chairman
8:20 KEYNOTE ADDRESS
Laying the Groundwork for the 21st Century Design
Environment, Wally Rhines, President and CEO, Mentor
Graphics
3 2 31
10:30 A Very High Performance and Manufacturable 3 3 V
0 35-pmCMOS Technology for ASICs, I Kizilyalli, S
Lytle, B Jones, E Martin, S Shive, A Brooks, M Thoma, R
Schanzer, J Sniegowski, D Wroge, R Key, J Kearney and K
Stiles, AT amp;T Bell Laboratories, Orlando, FL
3 3 35
10:55 TFSOI Complementary BiCMOS Technology for Low
Power RF Mixed-Mode Applications, W Huang, D Nog,
J Babcock, H Shin, P Welch, M Racanelli, J Ford and S
Cheng, Motorola Inc , Mesa, AZ
3 4 39
11:20 High Sensitivity Pixel Technology for a 1/4-inch PAL
430K pixel IT-CCD, A Tsukamoto, W Kamisaka, H Senda,
N Niisoe, H Aoki, T Otagaki, Y Shigeta, M Asaumi, Y
Miyata, Y Sano, T Kuriyama and S Terakawa, Matsushita
Electronics Corporation, Kyoto, Japan
SESSION 2 — PRESIDIO ROOM
Monday Morning
High Speed Datacom 3
Chair: Nick Van Bavel Co-Chair: German Gutierrez
2 1 5
10:05 Integrated Circuits for Data Transmission over
Twisted-Pair Channels (INVITED), D Johns, University of
Toronto, Toronto, Ontario, Canada and D Essig, Brooktree
Corporation, San Diego, CA
2 2 13
10:55 Timing Recovery in CMOS Using Nonlinear Spectral-
line Method, U Moon, A Mastrocola, J Alsayegh and S
Wemer, AT amp;T Bell Laboratories, Allentown, PA
2 3 17
11:20 A Mixed-Signal Decision-Feedback Equalizer that Uses
Parallelism, R Kajley, J Brown and P Hurst, University of
California, Davis, CA
2 4 21
11:45 A New CAM Macro for 622 Mbps ATM Cell Processing,
H Odagiri, N Takahashi, T Shidei, K Takeshita and Y
Kumagai, OKI Electric Industry Co , Ltd , Chiba, Japan
SESSION 3— FRIARS/PADRE/SIERRA ROOMS
Monday Morning
Process Technology and Manufacturing 25
Chair: Rene Penning de Vries Co-Chair: Michiel Beunder
3 1 27
10:05 Yield Loss Forecasting in the Early Phases of the VLSI
Design Process, H Heineken, J Khare and W Maly,
Carnegie Mellon University, Pittsburgh, PA
SESSION 4 — GOLDEN WEST ROOM
Monday Morning
Advances in Gate Arrays 43
Chair: John Wright Co-Chair: Jeffeiy Oppold
4 1 45
10:05 A Proven Methodology for Designing One-Million-Gate
ASICs (INVITED), A Rincon, M Trick, T Guzowski, IBM
Microelectronics, Essex Junction, VT
4 2 53
10:55 A High-Speed Low-Power 0 3pmCMOS Gate Array with
Variable Threshold Voltage (VT) Scheme, T Kuroda, T
Fujita, T Nagamatu, S Yoshioka, T Sei, K Matsuo, Y
Hamura, T Mori, M Murota, M Kakumu and T Sakurai,
Toshiba Corporation, Kawasaki, Japan
4 3 57
11:20 A Quarter-Micron SIMOX-CMOS LVTTL-Compatible
Gate Array with an Over 2,000 V ESD-Protection
Circuit, Y Ohtomo, T Mizusawa, K Nishimura, H Sawada
and M Ino, NTT LSI Laboratories, Kanagawa, Japan
4 4 61
11:45 A 1860kG CMOS Gate Array with GTL Input Flip-Flop
Circuits, K Tomobe, T Takahashi, M Kawashima, Y
Sonobe, T Kiyuna* and S Yamamoto**, Hitachi Ltd , Tokyo,
Japan, *Hitachi Computer Engineering Co , Ltd , Tokyo, Japan
and **Hitachi VLSI Engineering Co , Ltd , Tokyo, Japan
SESSION 5—CALIFORNIA ROOM
Monday Morning
DSP Computational Elements and Digital Filters 65
Chair: Fang Lu Co-Chair: Keisuke Okada
5 1 67
10:05 Floating Point Datapaths with On-Line Built-In Self
Speed TEST, Y Hagihara, S Inui, F Okamoto, M Nishida*,
T Nakamura** and H Yamada, NEC Corporation, Kanagawa,
Japan, *NEC Corporation, Tokyo, Japan and **NEC Kofu, Ltd ,
Yamanashi, Japan
115
5 2 71
10:30 A Complex Array Multiplier Using Distributed
Arithmetic, S He and M Torkelson, Lund University, Lund,
Sweden
5 3 75
10:55 A Pipelined Digital Differential Matched Filter FPGA
Implementation amp; VLSI Design, K Liu, W Lin and C
Wang, National Central University, Taiwan, Republic of China
5 4 79
11:20 Structured Design of a 288-tap FIR Filter by Optimized
Partial Product Tree Compression, J Choi, S Jeong, L
Jang and J Choi, LG Electronics Research Center, Seoul, Korea
SESSION 6— PRESIDIO ROOM
Monday Afternoon
Analog Circuit Techniques
Chair: David Rich
83
Co-Chair Terri Fiez
6 1 85
2:05 High-Precision, Programmable 1-10MHz Bandwidth, 0-
20dB Gain Communication Channel for Digital Video
Applications, P Siniscalchi, A Wyszynski* and D Choi,
Texas Instruments, Inc , Dallas, TX and *Cirrus Logic, Inc,
Plano, TX
6 2 89
2:30 A Highly Linear CMOS Gm-C Bandpass Filter for Video
Applications, Z Chang, D Haspeslagh, J Boxho and D
Macq, Alcatel Bell, Antwerp, Belgium
6 3 93
2:55 A BiCMOS Programmable Continuous-Time Filter
Using Voltage-Companding, G van Ruymbeke, C Enz, F
Krummenacher and M Declercq, Swiss Federal Institute of
Technology, Lausanne, Switzerland
6 4 97
3:20 An Improved Current Source for Low Voltage
Applications, F You, S Embabi, J Duque-Carrillo* and E
Sanchez-Sinencio, Texas A amp;M University, College Station, TX
and *University of Extremadura, Badajoz, Spain
6 5 101
3:45 A100 dB, 480 MHz OTA in 0 7 pm CMOS for Sampled-
Data Applications, T Burger and Q Huang, Swiss Federal
Institute of Technology, Zurich, Switzerland
6 6
4:10
105
A CMOS 4-bit MDAC with Self-Calibrated 14-bit
Linearity for High-Resolution Pipelined A/D
Converters, J Goes, J Vital and J Franca, Instituto Superior
Tecnico, Lisboa, Portugal
SESSION 7— FRIARS/PADRE/SIERRA ROOMS
Monday Afternoon
Low Power Circuit Design Techniques
and Implementations
Chair: Michael Brassington
109
Co-Chair: Doug Garrity
7 1
2:05
111
Power Management Technique for 1-V LSIs Using
Embedded Processor, S Shigematsu, S Mutoh and Y
Matsuya, NTT LSI Laboratories, Atsugi-shi, Japan
7 2 115
2:30 Implementing and Evaluating Adiabatic Arithmetic
Units, M Knapp, P Kindlmann and M Papaefthymiou, Yale
University, New Haven, CT
7 3
2:55 A 0 9V, 4K SRAM for Embedded Applications, J
Caravella, Motorola, Inc , Tempe, AZ
7 4
3:20
119
123
7 5
3:45
A 2 7V CMOS Single Chip Baseband Processor for
CT2/CT2+ Cordless Telephones, C Crippa, G Nicollini, P
Confalonieri, S Pemici, A Mecchia, P Rizzo, F Adduci, E
Viani, I Bietti, A Nagari amp; C Dallavalle, SGS-
Thomson/Microelect , Milano, Italy, A Leblond, Dassault
Automat, et Telecomm , Plaisir, France amp; P Busserolle,
Dassault Electronique, St Cloud, France
127
A Micropower Safety 1C for Rechargeable Lithium
Batteries, T Stockstad and T Petty, Motorola, Inc , Tempe,
AZ and R Yee, Colorado Springs, CO
7 6 131
4:10 Micro Power Protection Chip for Rechargeable
Lithium-ion Batteries, G Smith, National Semiconductor
Corporation, Tucson, AZ
SESSION 8— GOLDEN WEST ROOM
Monday Afternoon
Advances in Programmable Logic
Chair: John Turner
8 1
2:05
8 2
2:55
135
Co-Chair: Dangsh Tavana
137
An FPGA for Multi-Chip Reconfigurable Logic
(INVITED), R Amerson, R Carter, W Culbertson, P Kuekes
and G Snider, Hewlett-Packard Laboratories, Palo Alto, CA
144
Memory/Logic Interconnect Flexibility in FPGAs with
Large Embedded Memory Arrays, S Wilton, J Rose and
Z Vranesic, University of Toronto, Toronto, Ontario, Canada
8 3
3:20 A Self Clocked FPGA for General Purpose Logic
Emulation, D How, Stanford University, Stanford, CA
8 4
3:45
8 5
4:10
148
152
Time-Multiplexed Routing Resources for FPGA
Design, C Lin, D Chang, Y Wu* and M Marek-Sadowska,
University of California, Santa Barbara, CA and *Chinese
University of Hong Kong, Shatin, Hong Kong
156
Non-Orthogonal Decoding: An Architectural Element
for Reprogrammable Interconnect or Logic, A
Srinivasan, Aptix Corporation, San Jose, CA
SESSION 9—CALIFORNIA ROOM
Monday Afternoon
Innovations in Physical Design
Chair: Frank Szorc
161
Co-Chair: Sachin Sapatnekar
9 1
2:05 A Stable Partitioning Algorithm for VLSI Circuits, J
Chemg and S Chen, National Taiwan University, Taiwan,
Republic of China
163
9 2 167
2:30 Standard Cell Interconnect Length Prediction from
Structural Circuit Attributes, H Heineken and W Maly,
Carnegie Mellon University, Pittsburgh, PA
9 3 171
2:55 A New Rip-up and Reroute Algorithm for Very Large
Scale Gate Arrays, H Shirota, S Shibatani and M Terai,
Mitsubishi Electric Corporation, Hyogo, Japan
9 4 175
3:20 Analog Routing for Manufacturability, K Lampaert, G
Gielen, W Sansen, Katholieke Universiteit, Heverlee, Belgium
9 5 179
3:45 Exact Multi-Layer Topological Planar Routing, O
Coudert, Synopsys, Inc , Mountain View, CA and C Shi,
University of Iowa, Iowa City, IA
11 1 215
8:35 Exploring the Power Dimension (INVITED), J Rabaey,
Dept, of EECS, University of California at Berkeley
11 2 221
9:25 A Monte-Carlo Approach for the Accurate and Efficient
Estimation of Average Transition Probabilities in
Sequential Logic Circuits, G Stamoulis, Intel Corporation,
Santa Clara, CA
11 3 225
9:50 Nonparametric Estimation of Average Power
Dissipation in CMOS VLSI Circuits, L-P Yuan, C-C Teng,
and S-M Kang, University of Illinois, Urbana, IL
11 4 229
10:15 Maximum Power Estimation for Sequential Circuits
Using a Test Generation Based Technique, C Wang, K
Roy and T Chou, Purdue University, West Lafayette, IN
SESSION 10—PRESIDIO ROOM
Tuesday Morning
RF Communications Circuits 183
Chair: Don Green Co-Chair: Rick Carley
10 1 185
8:35 Modeling, Characterization and Design of Monolithic
Inductors for Silicon RFICs, J Long, University of Toronto,
Toronto, Ontario, Canada and M Copeland, Carleton University,
Ottawa, Ontario, Canada
11 5 233
10:40 Combined ac and Transient Power Distribution
Analysis, X Yang, The University of Texas, Austin, TX, B
Krauter, IBM Corporation, Austin, TX and L Pileggi, Carnegie
Mellon University, Pittsburgh, PA
SESSION 12—GOLDEN WEST ROOM
Tuesday Morning
New Architectures in Programmable Logic 237
Chair: Telle Whitney Co-Chair: Danesh Tavana
10 2 189
9:00 1 8 GHz Tunable Filter in Si Technology, S Pipilos,
National Technical University of Athens, Zographou, Greece, Y
Tsividis, Columbia University, New York, NY and J Fenk,
Siemens AG, Munich, Germany
10 3 193
9:25 A 2 5GHz Monolithic Silicon Image Reject Filter, J
Macedo and M Copeland, Carleton University, Ottawa, Ontario,
Canada and P Schvan, Bell-Northern Research Ltd , Ottawa,
Ontario, Canada
10 4 197
9:50 A1 GHz CMOS Upconversion Mixer, P Kinget and M
Steyaert, Katholieke Universiteit Leuven, Leuven, Belgium
10 5 201
10:15 Linearized High Efficiency Class E Power Amplifier for
Wireless Communications, T Sowlati, Y Greshishchev
and C Salama, University of Toronto, Toronto, Ontario, Canada
and G Rabjohn and J Sitch, Bell Northern Research, Ottawa,
Ontario, Canada
10 6 205
10:40 A Bipolar Sampled-Data Bandpass Delta-Sigma A/D
Modulator, T Varelas, S Bazarjani and W Snelgrove,
Carleton University, Ottawa, Ontario, Canada
10 7 209
11:05 A 900 MHz CMOS Frequency-Hopped Spread-
Spectrum RF Transmitter 1C, A Rofougaran, G Chang, J
Rael, M Rofougaran, S Khorram, M Ku, E Roth, A Abidi and
H Samueli, University of California, Los Angeles, CA
12 1 239
8:35 A High Density FLASH Memory FPGA Family, R Lipp,
R Freeman and T Saxe, Zycad Corporation, Fremont, CA
12 2 243
9:00 An SRAM-Based FPGA Architecture, S Gould, B Worth,
K Clinton, E Millham, F Keyser, R Palmer, S Hartman and T
Zittritsch, IBM Microelectronics, Essex Junction, VT
12 3 247
9:25 A New Generation of ORCA FPGA with Enhanced
Features and Performance, T Ngai, S Singh, B Britton,
W Leung, H Nguyen, G Powell, R Albu, W Andrews, J He
and C Spivak, AT amp;T Microelectronics, Allentown, PA
12 4 251
9:50 A High Density Embedded Array Programmable Logic
Architecture, S Reddy, R Cliff, D Jefferson, C Lane, C
Sung, B Wang, J Huang, W Chang, T Cope, C McClintock,
W Leong, B Ahanin and J Turner, ALTERA Corporation, San
Jose, CA
12 5 255
10:15 The Architecture and Test Structures of the XC8100
FPGA Family, B Fawcett, E Goetting, D Schultz, D Parlour,
S Frake, P Costello, R Eccles, B Leone, D Marquez, S
Stokes, M Palczewski, W Peterson, T Gannon, W Hart, K
Look, M Voogel, G West, V Tong, A Chang, D Chung, W
Hsieh and W Carter, Xilinx Inc , San Jose, CA
SESSION 13—CALIFORNIA ROOM
Tuesday Morning
SESSION 11 — FRIARS/PADRE/SIERRA
ROOMS Tuesday Morning
Power Estimation and Analysis 213
Chair: Dundar Dumlugol Co-Chair: Kartikeya Mayaram
Memories, I/Os and Read Channels 259
Chair: Iain Mackie Co-Chair: Brian Fitzgerald
13 1 261
8:35 A 35 Gbit/s Throughput 64 kbit CMOS Buffer SRAM, J
Alowersson and P Andersson, Lund University, Lund, Sweden
311
I
13 2 265
9:00 High-speed/High-band Width Design Methodologies
for on Chip DRAM Core Multimedia System LSIs, T
Tsuruda, M Kobayashi*, M Tsukude, T Yamagata and K
Arimoto, Mitsubishi Corporation, Hyogo, Japan and *Daioh
Electric Corporation
13 3 269
9:25 Performance Evaluation of a Microprocessor with On-
Chip DRAM and High Bandwidth Internal Bus, S Iwata,
T Shimuzi, J Korematu, K Dosaka, H Tsubota and K Saitoh,
Mitsubishi Electric Corporation, Hyogo, Japan
13 4 273
9:50 A 336-kbit Content Addressable Memory for Highly
Parallel Image Processing, T Ogura, M Nakanishi*, T
Baba*, Y Nakabayashi* and R Kasai, NTT LSI Laboratories,
Kanagawa, Japan and *NTT Electronics Technology,
Kanagawa, Japan
13 5 277
10:15 Forming Damped LRC Parasitic Circuits in
Simultaneously Switched CMOS Output Buffers, T
Gabara, W Fischer, J Harrington* and W Troutman, AT amp;T
Bell Laboratories, Murray Hill, NJ and *AT amp;T Bell
Laboratories, Allentown, PA
13 6 281
10:40 Capacitive Coupling and Quantized Feedback Applied
to Conventional CMOS Technology, T Gabara and W
Fischer, AT amp;T Bell Laboratories, Murray Hill, NJ
13 7 285
11:05 A Single Chip HDD PRML Channel, T Ahn, G Chen, B
Hua, C Kim, D Knee, A Kondo, B Kuo, I Lan, M Ng, F
Shen, N Yeh and J Young, Samsung Semiconductor, Inc , San
Jose, CA
SESSION 14—PRESIDIO ROOM
Tuesday Afternoon
Sensor Application and Interface Circuits 289
Chair: Larry Starr Co-Chair: Sterling Whitaker
14 1 291
2:05 A Low Noise Readout Detector Circuit for Nano-
Ampere Sensor Applications, D Thelen, University of
New Mexico, Albuquerque, NM and D Chu, Sandia National
Laboratories, Albuquerque, NM
14 2 295
2:30 An Intracorporal Telemetry for Strain Gage
Transducer, J Begueret, R Benbrahim, Z Li, F Rhodes and
J Dom, IXL-Laboratoire de Microelectronique, Talence, France
14 3 299
2:55 A BiFET Automatic Gain Control Amplifier for Hearing
Aids, F Sykes and S Armstrong, GENNUM Corporation,
Burlington, Ontario, Canada
14 4 303
3:20 A128 x 128 Pixel CMOS Area Image Sensor with
Multiplexed Pixel Level A/D Conversion, D Yang, B
Fowler and A Gamal, Stanford University, Stanford, CA
14 5 307
3:45 Readout Electronics with Calibration and On-Line Test
for Resistive Sensor Bridges, O Machul, D
Hammerschmidt, W Brodkherde and B Hosticka, Fraunhofer
Institute of Microelectronic Circuits and Systems, Duisburg,
Germany
14 6
4:10 An Angular Rate Sensor Interface IC, S Zarabadi, P
Castillo-Borelly and J Johnson, Delco Electronics Corporation,
Kokomo, IN
14 7 315
4:35 A Micromachined Fully Differential Lateral
Accelerometer, M Lemkin and B Boser, University of
California, Berkeley, CA
SESSION 15— FRIARS/PADRE/SIERRA ROOMS
Tuesday Afternoon
Device Modeling and Analog Simulation 319
Chair: Chandu Visweswariah Co-Chair: Karti Mayaram
15 1 321
2:05 An Investigation on the Robustness, Accuracy and
Simulation Performance of a Physics-Based Deep-
Submicronmeter BSIM Model for Analog/Digital Circuit
Simulation, Y Cheng, M Jeng*, Z Liu**, K Chen, M Chan,
C Hu and P Ko***, University of California, Berkeley, CA,
*Cadence Design System, **BTA Technology Inc and ***Hong
Kong University of Science and Technology, Hong Kong
15 2 325
2:30 An EEPROM Compact Circuit Model, P Klein, K
Hoffmann and O Kowarik, University of Bundeswehr Munich,
Neubiberg, Germany
15 3 329
2:55 An Efficient Approach to Device Parameter Extraction
for Statistical 1C Modeling, M Qu, National Semiconductor
Corporation, Santa Clara, CA and M Styblinski, Texas A amp;M
University, College Station, TX
15 4 333
3:20 Impact of Transistor Mismatch on the Speed-
Accuracy-Power Trade-Off of Analog CMOS Circuits,
P Kinget and M Steyaert, Katholieke Universiteit Leuven,
Leuven, Belgium
15 5 337
3:45 Optimal Design of Opamps for Oversampled
Converters, F Wang and R Harjani, University of Minnesota,
Minneapolis, MN
15 6 341
4:10 Fast and Accurate Delay Estimation for Use in Timing
Driven Layout for FPGAs with Segmented Channels,
S Kaptanoglu, Actel Corporation, Sunnyvale, CA
15 7 345
4:35 A New Technique for the Efficient Solution of Singular
Circuits, J Roychowdhury, AT amp;T Bell Laboratories, Murray
Hill, NJ
SESSION 16—GOLDEN WEST ROOM
Tuesday Afternoon
Video, Image and Speech Digital Signal Processing 349
Chair: Takayasu Sakurai Co-Chair: Michael Thom
16 1 351
2:05 VLSI Implementation of Hierarchical Motion Estimator
for MPEG2 MP@HL, T Onoye, G Fujita and I Shirakawa,
Osaka University, Osaka, Japan, K Matsumura, KCS Co , Ltd ,
Osaka, Japan, H Ariyoshi, Ehime University, Ehime, Japan and
S Tsukiyama, Chuo University, Tokyo, Japan
16 2 355
2:30 A Cascadable 200 GOPS Motion Estimation Chip for
HDTV Applications, J Berns and T Noll, University of
Technology RWTH, Aachen, Germany
16 3 359
2:55 A DSP for DCT-Based and Wavelet-Based Video
CODECs for Consumer Applications, K Okamoto, T
Jinbo, T Araki, Y lizuka*, H Nakajima*, M Takahata*, H
Inoue**, S Kurohmaru**, T Yonezawa** and K Aono,
Matsushita Electric Industrial Co , Ltd , Osaka, Japan,
*Matsushita Electronics Corp , Kanagawa, Japan, **Matsushita
Electric Industr Co , Fukuoka, Japan
16 4 363
3:20 Control and Synchronization Scheme for Parallel
Image Processing RAM with 128 Processor Elements
and 16-Mb DRAM, Y Yabe, T Kimura, Y Aimoto, H
Heiuchi, Y Nakazawa, T Koga, Y Fujita, M Hamada, T
Tanigawa, H Nobusawa, and K Koyama, NEC Corporation,
Kanagawa, Japan
16 5 367
3:45 A 36 MHz CMOS Fixed-point G 728 Low Delay CELP
Integrated Decoder-Encoder, W Soon, S Goyal, L Hsu
and Y Wee, Siemens Components Pte Ltd , Singapore,
Republic of Singapore
16 6 371
4:10 A 1 8V 36mW DSP for the Half-Rate Speech CODEC, T
Shiraishi, K Kawamoto, K Ishikawa, H Sato, F Asai, E
Teraoka, T Kengaku, H Takata, T Tokuda, K; Nishida and K
Saitoh, Mitsubishi Electric Corporation, Hyogo, Japan
SESSION 17—CALIFORNIA ROOM
Tuesday Afternoon
Critical Design Methods for the Late 90s 375
Chair: Paul Billig Co-Chair: Neill Mullinger
17 1 377
2:05 A Brief Introduction to Formal Methods, P Black, K
Hall, M Jones, T Larson, and P Windley, Brigham Young
University, Provo, UT
17 2 381
2:30 Practical Analysis of Cyclic Combinational Circuits, A
Srinivasan, Mentor Graphics Corporation, San Jose, CA and S
Malik, Princeton University, Princeton, NJ
17 3 385
2:55 SubWave: A Methodology for Modeling Digital
Substrate Noise Injection in Mixed-Signal ICs, P
Miliozzi, L Carloni, E Charbon* and A Sangiovanni-
Vincintelli, University of California, Berkeley, CA and
*Cadence Design Systems, Santa Clara, CA
17 4 389
3:20 Forward Power Annotation on Physical Layout Floor-
Plan, R Zafalon, C Guardiani, M Rossi, R Rambaldi, SGS-
Thomson Microelectronics, Agrate, Italy
17 5 393
3:45 Efficient Power Analysis of Combinational Circuits,
S Krishnamoorthy and A Khouja, Synopsys Inc , Mountain
View, CA
17 6 397
4:10 Low Energy Memory Component Design for Cost-
Sensitive High Performance Embedded Systems, C
Gebotys, University of Waterloo, Waterloo, Ontario, Canada
17 7 401
4:35 Exploiting Locality for Low-Power Design, R Mehra, L
Guerra and J Rabaey, University of California, Berkeley, CA
SESSION 18—GOLDEN WEST ROOM
Tuesday Evening
8:00 Evening Panel 405
Deep Submicron Chip Design—What Business Issues
will Dominate?
SESSION 19 —CALIFORNIA ROOM
Tuesday Evening
8:00 Evening Panel 407
Technical Challenges in One-Million Gate Chip
Designs
SESSION 20— PRESIDIO ROOM
Wednesday Morning
Data Converters 409
Chair: Yusuf Haque Co-Chair: Masao Hotta
20 1 411
8:35 A1 95V, 0 34mW 12-bit Sigma-Delta Modulator
Stabilized by Local Feedback Loops, S Au and B Leung,
University of Waterloo, Waterloo, Ontario, Canada
20 2 415
9:00 A 5V Single-Chip Delta-Sigma Audio A/D Converter
with llldB Dynamic-Range, I Fujimori and K Koyama,
Asahi-Kasei Microsystems, Kanagawa, Japan and D Träger, F
Tam and L Longo, Oasis Design Inc , Austin, TX
20 3 419
9:25 A10-bit, 100 MS/s CMOS A/D Converter, K Kim, N
Kusayanagi and A Abidi, University of California, Los Angeles,
CA
20 4 423
9:50 An 8-Bit 50+ Msamples/s Pipelined A/D Converter with
an Area and Power Efficient Architecture, K Nagaraj, H
Fetterman, R Shariatdoust, J Anidjar, S Lewis*, J Alsayegh
and R Renninger, AT amp;T Bell Laboratories, Allentown, PA and
*University of California, Davis, CA
20 5 427
10:15 A CMOS 12-bit 4MHz Pipelined A/D Converter with
Commutative Feedback Capacitor, J Yang and H Lee,
Massachusetts Institute of Technology, Cambridge, MA
20 6 431
10:40 A High Yield 12-bit 250-MS/s CMOS D/A Converter, J
Bastos, M Steyaert and W Sansen, Katholieke Universiteit
Leuven, Heverlee, Belgium
SESSION 21— FRIARS/PADRE/SIERRA ROOMS
Wednesday Morning
Simulations and Modeling of RF Circuits 435
Chair: Brian Antao Co-Chair: George Stamoulis
21 1 437
8:35 Fast Simulation Algorithms for RF Circuits (INVITED),
R Telichevesky and K Kundert, Cadence Design Systems, San
Jose, CA, I Elfadel and J White, Massachusetts Institute of
Technology, Cambridge, MA
483
21 2 445
9:25 Parasitic Characterization of Radio-Frequency (RF)
Circuits Using Mixed-Mode Simulation, J Jang, E Kan,
L So and R Dutton, Stanford University, Stanford, CA, T
Johansson and T Amborg, Ericsson Microsistems, Kista,
Sweden
21 3 449
9:50 Receiver Characterization Using Periodic Small-Signal
Analysis, R Telichevesky and K Kundert, Cadence Design
Systems, San Jose, CA and J White, Massachusetts Institute of
Technology, Cambridge, MA
453
Simulation and Modeling of Phase Noise in Open-Loop
Oscillators, A Demir and A Sangiovanni-Vincintelli,
University of California, Berkeley, CA
457
Dispersive Coupled Transmission Line Simulation
Using an Adaptive Block Lanczos Algorithm, T Nguyen
and J Li, Motorola Inc , Austin, TX and Z Bai, University of
Kentucky, Lexington, KY
21 6 461
11:05 Efficient Frequency Domain Analysis of Large
Nonlinear Analog Circuits, P, Feldmann, B Melville and D
Long, AT amp;T Bell Laboratories, Murray Hill, NJ
21 4
10:15
21 5
10:40
SESSION 22—GOLDEN WEST ROOM
Wednesday Morning
Improvements in Test and Reliability 465
Chair: Linda Milor Co-Chair: Robert Aitken
22 1 467
8:35 IDDQ Testing in Low Power Supply CMOS Circuits, C
Tong and M Wen, Colorado State University, Fort Collins, CO
and S Su, Hewlett-Packard Company, Fort Collins, CO
22 2 471
9:00 A CMOS Mixed-Signal Integrated Circuit Having a
Reduced Vector Set and Closed-Loop Analog Test
Architecture, A Chavan, D Stringfellow, S Mallarapu and R
Ardeishar, Delco Electronics Corporation, Kokomo, IN
22 3 475
9:25 L2RFM—Local Layout Realistic Faults Mapping
Scheme for Analogue Integrated Circuits, M Ohletz,
Universität Hannover, Hannover, Germany
22 4 479
9:50 Fast Thermal Analysis for CMOS VLSIC Reliability, Y-
K Cheng and S-M Kang, University of Illinois, Urbana, IL
22 5
10:15
483
Over an Order of Magnitude DRAM Test Time
Reduction by Charge Offset, M Hashimoto, I Uchida* and
S Hatakoshi, Texas Instruments Japan Ltd , Ibaraki, Japan and
♦Texas Instruments Japan Ltd , Oita, Japan
22 6 487
10:40 Scan Paths Through Functional Logic, C Lin, M Marek-
Sadowska and K Cheng, University of California, Santa
Barbara, CA and M Lee, Fujitsu Laboratories of America, Santa
Clara, CA
SESSION 23—CALIFORNIA ROOM
Wednesday Morning
Ceil and Macro Generation/Optimization 491
Chair: Jim Lipman Co-Chair: Hidetoshi Onodera
23 1 493
8:35 Optimization of Standard Cell Libraries for Low Power,
High Speed, or Minimal Area Designs, C Fisher, R
Blankenship, J Jensen, T Rossman and K Svilich, Cascade
Design Automation, Bellevue, WA
23 2 497
9:00 Efficiently Embedding Expertise in High-Density
Process-Portable Standard Cell Generators, J Duh and
T Matheson, Mentor Graphics Corporation, Warren, NJ and E
Hepler, VLSI Concepts Inc and Villanova University, Malvern,
PA
23 3 501
9:25 Efficient Standard Cell Generation When Diffusion
Strapping is Required, B Guan and C Sechen, University of
Washington, Seattle, WA
23 4 505
9:50 Efficient Area Minimization for Dynamic CMOS
Circuits, B Basaran and R Rutenbar, Carnegie Mellon
University, Pittsburgh, PA
23 5 509
10:15 Gate-Array Library Design Using Local Interconnect, L
Wissel, D Stout and N Buck, IBM Microelectronics, Essex
Junction, VT
23 6 513
10:40 Exploring Multiplier Architecture and Layout for Low
Power, P Meier, R Rutenbar and L Carley, Carnegie Mellon
|
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| building | Verbundindex |
| bvnumber | BV019624704 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
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| callnumber-sort | TK 47874 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4952 |
| ctrlnum | (OCoLC)35147931 (DE-599)BVBBV019624704 |
| dewey-full | 621.38173 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.38173 |
| dewey-search | 621.38173 |
| dewey-sort | 3621.38173 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 1996 San Diego Calif. gnd-content |
| genre_facet | Konferenzschrift 1996 San Diego Calif. |
| id | DE-604.BV019624704 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T20:01:36Z |
| institution | BVB |
| institution_GND | (DE-588)5193246-5 |
| isbn | 0780331176 0780331184 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-012953997 |
| oclc_num | 35147931 |
| open_access_boolean | |
| owner | DE-29T DE-83 |
| owner_facet | DE-29T DE-83 |
| physical | 516 S Ill., graph. Darst. |
| publishDate | 1996 |
| publishDateSearch | 1996 |
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| publisher | IEEE Order Dept. |
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| spelling | Custom Integrated Circuits Conference 18 1996 San Diego, Calif. Verfasser (DE-588)5193246-5 aut Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 Piscataway, NJ IEEE Order Dept. 1996 516 S Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Circuitos integrados (congressos) larpcal Circuits intégrés - Congrès ram Circuits intégrés à la demande - Congrès ram Réseaux neuronaux - Congrès ram Integrated circuits Congresses Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1996 San Diego Calif. gnd-content Integrierte Schaltung (DE-588)4027242-4 s Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012953997&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 Circuitos integrados (congressos) larpcal Circuits intégrés - Congrès ram Circuits intégrés à la demande - Congrès ram Réseaux neuronaux - Congrès ram Integrated circuits Congresses Integrierte Schaltung (DE-588)4027242-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4122250-7 (DE-588)1071861417 |
| title | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 |
| title_auth | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 |
| title_exact_search | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 |
| title_full | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 |
| title_fullStr | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 |
| title_full_unstemmed | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference Town and Country Hotel, San Diego, California, May 5 - 8, 1996 |
| title_short | Proceedings of the IEEE 1996 Custom Integrated Circuits Conference |
| title_sort | proceedings of the ieee 1996 custom integrated circuits conference town and country hotel san diego california may 5 8 1996 |
| title_sub | Town and Country Hotel, San Diego, California, May 5 - 8, 1996 |
| topic | Circuitos integrados (congressos) larpcal Circuits intégrés - Congrès ram Circuits intégrés à la demande - Congrès ram Réseaux neuronaux - Congrès ram Integrated circuits Congresses Integrierte Schaltung (DE-588)4027242-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd |
| topic_facet | Circuitos integrados (congressos) Circuits intégrés - Congrès Circuits intégrés à la demande - Congrès Réseaux neuronaux - Congrès Integrated circuits Congresses Integrierte Schaltung Kundenspezifische Schaltung Konferenzschrift 1996 San Diego Calif. |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012953997&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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