Field programmable logic and applications: 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings
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| Format: | Tagungsbericht Buch |
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| Sprache: | English |
| Veröffentlicht: |
Berlin u.a.
Springer
2004
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| Schriftenreihe: | Lecture Notes in Computer Science
3203 |
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXIX, 1198 S. Ill., graph. Darst. |
| ISBN: | 3540229892 |
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| 245 | 1 | 0 | |a Field programmable logic and applications |b 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings |c Jürgen Becker ... (eds.) |
| 246 | 1 | 3 | |a FPL 2004 |
| 246 | 1 | 3 | |a Fiel-programmable logic and applcations |
| 264 | 1 | |a Berlin u.a. |b Springer |c 2004 | |
| 300 | |a XXIX, 1198 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 490 | 1 | |a Lecture Notes in Computer Science |v 3203 | |
| 650 | 7 | |a Application |2 rasuqam | |
| 650 | 7 | |a Circuit reconfigurable |2 rasuqam | |
| 650 | 7 | |a Configuration |2 rasuqam | |
| 650 | 7 | |a Cryptographie (Informatique) |2 rasuqam | |
| 650 | 4 | |a Logique à réseau programmable - Congrès | |
| 650 | 7 | |a Logique à réseau programmable |2 rasuqam | |
| 650 | 7 | |a Processeur de signal numérique |2 rasuqam | |
| 650 | 7 | |a Réseau logique programmable par l'utilisateur |2 rasuqam | |
| 650 | 4 | |a Réseaux logiques programmables par l'utilisateur - Congrès | |
| 650 | 4 | |a Field programmable gate arrays |v Congresses | |
| 650 | 4 | |a Programmable array logic |v Congresses | |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
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| 711 | 2 | |a FPL |n 14 |d 2004 |c Antwerpen |j Sonstige |0 (DE-588)10086227-5 |4 oth | |
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Datensatz im Suchindex
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TABLE OF CONTENTS
PLENARY KEYNOTES
FPGAS AND THE ERA OF FIELD PROGRAMMABILITY
.
1
W. ROELANDTS
RECONFIGURABLE SYSTEMS EMERGE
.
2
N. TREDENNICK, B. SHIMAMOTO
SYSTEM-LEVEL DESIGN TOOLS CAN PROVIDE LOW COST SOLUTIONS
IN FPGAS: TRUE OR FALSE?
.
12
M. DICKINSON
ORGANIC AND BIOLOGY COMPUTING
HARDWARE ACCELERATED NOVEL PROTEIN IDENTIFICATION
.
13
A. ALEX, J. ROSE, R. ISSERLIN-WEINBERGER, C. HOGUE
LARGE SCALE PROTEIN SEQUENCE ALIGNMENT
USING FPGA REPROGRAMMABLE LOGIC DEVICES
.
23
S. DYDEL, P. BA*LA
SECURITY AND CRYPTOGRAPHY 1
A KEY MANAGEMENT ARCHITECTURE
FOR SECURING OFF-CHIP DATA TRANSFERS
.
33
J. GRAF, P. ATHANAS
FPGA IMPLEMENTATION OF BIOMETRIC AUTHENTICATION SYSTEM
BASED ON HAND GEOMETRY
.
43
C. L´OPEZ-ONGIL, R. SANCHEZ-REILLO, J. LIU-JIMENEZ, F. CASADO,
L. S´ANCHEZ, L. ENTRENA
PLATFORM BASED DESIGN
SOFTSONIC: A CUSTOMISABLE MODULAR PLATFORM FOR VIDEO APPLICATIONS
.
54
T. RISSA, P.Y.K. CHEUNG, W. LUK
DEPLOYING HARDWARE PLATFORMS FOR SOC VALIDATION:
AN INDUSTRIAL CASE STUDY
.
64
A. BIGOT, F. CHARPENTIER, H. KRUPNOVA, I. SANS
XIV TABLE OF CONTENTS
ALGORITHMS AND ARCHITECTURES
ALGORITHMS AND ARCHITECTURES FOR USE IN FPGA IMPLEMENTATIONS
OF IDENTITY BASED ENCRYPTION SCHEMES
.
74
T. KERINS, E. POPOVICI, W. MARNANE
POWER ANALYSIS ATTACKS AGAINST FPGA IMPLEMENTATIONS OF THE DES
.
84
F.-X. STANDAERT, S.B.
¨
ORS, J.-J. QUISQUATER, B. PRENEEL
ACCELERATION APPLICATION 1
MONTE CARLO RADIATIVE HEAT TRANSFER SIMULATION
ON A RECONFIGURABLE COMPUTER
.
95
M. GOKHALE, J. FRIGO, C. AHRENS, J.L. TRIPP, R. MINNICH
STOCHASTIC SIMULATION FOR BIOCHEMICAL REACTIONS ON FPGA
.
105
M. YOSHIMI, Y. OSANA, T. FUKUSHIMA, H. AMANO
ARCHITECTURE 1
DYNAMIC ADAPTIVE RUNTIME ROUTING TECHNIQUES
IN MULTIGRAIN RECONFIGURABLE HARDWARE ARCHITECTURES
.
115
A. THOMAS, J. BECKER
INTERCONNECTING HETEROGENEOUS NODES
IN AN ADAPTIVE COMPUTING MACHINE
.
125
F. FURTEK, E. HOGENAUER, J. SCHEUERMANN
IMPROVING FPGA PERFORMANCE AND AREA
USING AN ADAPTIVE LOGIC MODULE
.
135
M. HUTTON, J. SCHLEICHER, D. LEWIS, B. PEDERSEN, R. YUAN,
S. KAPTANOGLU, G. BAECKLER, B. RATCHEV, K. PADALIA,
M. BOURGEAULT, A. LEE, H. KIM, R. SAINI
A DUAL-V
DD
LOW POWER FPGA ARCHITECTURE
.
145
A. GAYASEN, K. LEE, N. VIJAYKRISHNAN, M. KANDEMIR, M.J. IRWIN,
T. TUAN
PHYSICAL DESIGN 1
SIMULTANEOUS TIMING DRIVEN CLUSTERING AND PLACEMENT FOR FPGAS
.
158
G. CHEN, J. CONG
RUN-TIME-CONSCIOUS AUTOMATIC TIMING-DRIVEN
FPGA LAYOUT SYNTHESIS
.
168
J. ANDERSON, S. NAG, K. CHAUDHARY, S. KALMAN, C. MADABHUSHI,
P. CHENG
TABLE OF CONTENTS XV
COMPACT BUFFERED ROUTING ARCHITECTURE
.
179
A. LODI, R. GIANSANTE, C. CHIESA, L. CICCARELLI, F. CAMPI,
M. TOMA
ON OPTIMAL IRREGULAR SWITCH BOX DESIGNS
.
189
H. FAN, Y.-L. WU, C.-C. CHEUNG, J. LIU
ARITHMETIC 1
DUAL FIXED-POINT:
AN EFFICIENT ALTERNATIVE TO FLOATING-POINT COMPUTATION
.
200
C.T. EWE, P.Y.K. CHEUNG, G.A. CONSTANTINIDES
COMPARATIVE STUDY OF SRT-DIVIDERS IN FPGA
.
209
G. SUTTER, G. BIOUL, J.-P. DESCHAMPS
SECOND ORDER FUNCTION APPROXIMATION
USING A SINGLE MULTIPLICATION ON FPGAS
.
221
J. DETREY, F. DE DINECHIN
EFFICIENT MODULAR DIVISION IMPLEMENTATION
(ECC OVER GF(P) AFFINE COORDINATES APPLICATION)
.
231
G. MEURICE DE DORMALE, P. BULENS, J.-J. QUISQUATER
MULTITASKING
A LOW FRAGMENTATION HEURISTIC FOR TASK PLACEMENT
IN 2D RTR HW MANAGEMENT
.
241
J. TABERO, J. SEPTI´EN, H. MECHA, D. MOZOS
THE PARTITION INTO HYPERCONTEXTS PROBLEM
FOR HYPERRECONFIGURABLE ARCHITECTURES
.
251
S. LANGE, M. MIDDENDORF
CIRCUIT TECHNOLOGY
A HIGH-DENSITY OPTICALLY RECONFIGURABLE GATE ARRAY
USING DYNAMIC METHOD
.
261
M. WATANABE, F. KOBAYASHI
EVOLVABLE HARDWARE FOR SIGNAL SEPARATION AND NOISE CANCELLATION
USING ANALOG RECONFIGURABLE DEVICE
.
270
D. KEYMEULEN, R. ZEBULUM, A. STOICA, V. DUONG, M.I. FERGUSON
XVI TABLE OF CONTENTS
MEMORY 1
IMPLEMENTING HIGH-SPEED DOUBLE-DATA RATE (DDR)
SDRAM CONTROLLERS ON FPGA
.
279
E. PICATOSTE-OLLOQUI, F. CARDELLS-TORMO, J. SEMPERE-AGULLO,
A. HERMS-BERENGUER
LOGIC MODULES WITH SHARED SRAM TABLES
FOR FIELD-PROGRAMMABLE GATE ARRAYS
.
289
F. KOCAN, J. MEYER
NETWORK PROCESSING
A MODULAR SYSTEM FOR FPGA-BASED TCP FLOW PROCESSING
IN HIGH-SPEED NETWORKS
.
301
D.V. SCHUEHLER, J.W. LOCKWOOD
AUTOMATIC SYNTHESIS OF EFFICIENT INTRUSION DETECTION SYSTEMS
ON FPGAS
.
311
Z.K. BAKER, V.K. PRASANNA
TESTING
BIST BASED INTERCONNECT FAULT LOCATION FOR FPGAS
.
322
N. CAMPREGHER, P.Y.K. CHEUNG, M. VASILKO
FPGAS BIST EVALUATION
.
333
A. PARREIRA, J.P. TEIXEIRA, M.B. SANTOS
APPLICATIONS
SOLVING SAT WITH A CONTEXT-SWITCHING VIRTUAL CLAUSE PIPELINE
AND AN FPGA EMBEDDED PROCESSOR
.
344
C.J. TAVARES, C. BUNGARDEAN, G.M. MATOS, J.T. DE SOUSA
EVALUATING FAULT EMULATION ON FPGA
.
354
P. ELLERVEE, J. RAIK, V. TIHHOMIROV, K. TAMMEM¨AE
ARITHMETIC 2
AUTOMATING OPTIMIZED TABLE-WITH-POLYNOMIAL FUNCTION EVALUATION
FOR FPGAS
.
364
D.-U. LEE, O. MENCER, D.J. PEARCE, W. LUK
MULTIPLE RESTRICTED MULTIPLICATION
.
374
N. SIDAHAO, G.A. CONSTANTINIDES, P.Y.K. CHEUNG
TABLE OF CONTENTS XVII
SIGNAL PROCESSING 1
AREA*TIME OPTIMIZED HOGENAUER CHANNELIZER DESIGN
USING FPL DEVICES
.
384
U. MEYER-B¨ASE, S. RAO, J. RAM´*REZ, A. GARC´*A
A STEERABLE COMPLEX WAVELET CONSTRUCTION AND ITS IMPLEMENTATION
ON FPGA
.
394
C.-S. BOUGANIS, P.Y.K. CHEUNG, J. NG, A.A. BHARATH
COMPUTATIONAL MODELS AND COMPILER
PROGRAMMABLE LOGIC HAS MORE COMPUTATIONAL POWER
THAN FIXED LOGIC
.
404
G. BREBNER
JHDLBITS: THE MERGING OF TWO WORLDS
.
414
A. POETTER, J. HUNTER, C. PATTERSON, P. ATHANAS, B. NELSON,
N. STEINER
A SYSTEM LEVEL RESOURCE ESTIMATION TOOL FOR FPGAS
.
424
C. SHI, J. HWANG, S. MCMILLAN, A. ROOT, V. SINGH
THE POWERPC BACKEND MOLEN COMPILER
.
434
E. MOSCU PANAINTE, K. BERTELS, S. VASSILIADIS
DYNAMIC RECONFIGURATION 1
AN INTEGRATED ONLINE SCHEDULING AND PLACEMENT METHODOLOGY
.
444
M. HANDA, R. VEMURI
ON-DEMAND FPGA RUN-TIME SYSTEM FOR DYNAMICAL RECONFIGURATION
WITH ADAPTIVE PRIORITIES
.
454
M. ULLMANN, M. H¨UBNER, B. GRIMM, J. BECKER
TECHNIQUES FOR VIRTUAL HARDWARE ON A DYNAMICALLY RECONFIGURABLE
PROCESSOR * AN APPROACH TO TOUGH CASES *
.
464
H. AMANO, T. INUO, H. KAMI, T. FUJII, M. SUZUKI
THROUGHPUT AND RECONFIGURATION TIME TRADE-OFFS:
FROM STATIC TO DYNAMIC RECONFIGURATION IN DEDICATED IMAGE FILTERS
.
474
M.R. BOSCHETTI, S. BAMPI, I.S. SILVA
NETWORK AND OPTIMIZATION ALGORITHMS
OVER 10GBPS STRING MATCHING MECHANISM
FOR MULTI-STREAM PACKET SCANNING SYSTEMS
.
484
Y. SUGAWARA, M. INABA, K. HIRAKI
XVIII TABLE OF CONTENTS
HARDWARE DESIGN OF A FPGA-BASED SYNCHRONIZER FOR HIPERLAN/2
.
494
M.J. CANET, F. VICEDO, V.A.J. VALLS, E.R. DE LIMA
THREE-DIMENSIONAL DYNAMIC PROGRAMMING FOR HOMOLOGY SEARCH
.
505
Y. YAMAGUCHI, T. MARUYAMA, A. KONAGAYA
AN INSTANCE-SPECIFIC HARDWARE ALGORITHM
FOR FINDING A MAXIMUM CLIQUE
.
516
S. WAKABAYASHI, K. KIKUCHI
SYSTEM-ON-CHIP 1
IP GENERATION FOR AN FPGA-BASED
AUDIO DAC SIGMA-DELTA CONVERTER
.
526
R. LUDEWIG, O. SOFFKE, P. ZIPF, M. GLESNER, K.P. PUN,
K.H. TSOI, K.H. LEE, P. LEONG
AUTOMATIC CREATION OF RECONFIGURABLE PALS/PLAS FOR SOC
.
536
M. HOLLAND, S. HAUCK
HIGH SPEED DESIGN
A KEY AGILE 17.4 GBIT/SEC CAMELLIA IMPLEMENTATION
.
546
D. DENNING, J. IRVINE, M. DEVLIN
HIGH PERFORMANCE TRUE RANDOM NUMBER GENERATOR
IN ALTERA STRATIX FPLDS
.
555
V. FISCHER, M. DRUTAROVSK´Y, M.
*
SIMKA, N. BOCHARD
SECURITY AND CRYPTOGRAPHY 2
A UNIVERSAL AND EFFICIENT AES CO-PROCESSOR
FOR FIELD PROGRAMMABLE LOGIC ARRAYS
.
565
N. PRAMSTALLER, J. WOLKERSTORFER
EXPLORING AREA/DELAY TRADEOFFS IN AN AES FPGA IMPLEMENTATION
.
575
J. ZAMBRENO, D. NGUYEN, A. CHOUDHARY
ARCHITECTURES 2
RECONFIGURABLE INSTRUCTION SET EXTENSION FOR ENABLING ECC
ON AN 8-BIT PROCESSOR
.
586
S. KUMAR, C. PAAR
TABLE OF CONTENTS XIX
MEMORY 2
DYNAMIC PREFETCHING IN THE VIRTUAL MEMORY WINDOW
OF PORTABLE RECONFIGURABLE COPROCESSORS
.
596
M. VULETIC, L. POZZI, P. IENNE
STORAGE ALLOCATION FOR DIVERSE FPGA MEMORY SPECIFICATIONS
.
606
D. DAGHER, I. OUAISS
IMAGE PROCESSING 1
REAL TIME OPTICAL FLOW PROCESSING SYSTEM
.
617
J. D´*AZ, E. ROS, S. MOTA, R. CARRILLO, R. AGIS
METHODS AND TOOLS FOR HIGH-RESOLUTION IMAGING
.
627
T. TODMAN, W. LUK
NETWORK-ON-CHIP
NETWORK-ON-CHIP FOR RECONFIGURABLE SYSTEMS:
FROM HIGH-LEVEL DESIGN DOWN TO IMPLEMENTATION
.
637
T.A. BARTIC, D. DESMET, J.-Y. MIGNOLET, T. MARESCAUX, D. VERKEST,
S. VERNALDE, R. LAUWEREINS
A RECONFIGURABLE RECURRENT BITONIC SORTING NETWORK
FOR CONCURRENTLY ACCESSIBLE DATA
.
648
C. LAYER, H.-J. PFLEIDERER
POWER AWARE DESIGN 1
A FRAMEWORK FOR ENERGY EFFICIENT DESIGN OF MULTI-RATE APPLICATIONS
USING HYBRID RECONFIGURABLE SYSTEMS
.
658
S. MOHANTY, V.K. PRASANNA
AN EFFICIENT BATTERY-AWARE TASK SCHEDULING METHODOLOGY
FOR PORTABLE RC PLATFORMS
.
669
J. KHAN, R. VEMURI
IP-BASED DESIGN
HW/SW CO-DESIGN BY AUTOMATIC EMBEDDING OF COMPLEX IP CORES
.
679
H. LANGE, A. KOCH
INCREASING PIPELINED IP CORE UTILIZATION IN PROCESS NETWORKS
USING EXPLORATION
.
690
C. ZISSULESCU, B. KIENHUIS, E. DEPRETTERE
DISTRIBUTION OF BITSTREAM-LEVEL IP CORES
FOR FUNCTIONAL EVALUATION USING FPGAS
.
700
R. SIRIPOKARPIROM
XX TABLE OF CONTENTS
SOC AND RTOS: MANAGING IPS AND TASKS COMMUNICATIONS
.
710
A. SEGARD, F. VERDIER
POWER AWARE DESIGN 2
THE IMPACT OF PIPELINING ON ENERGY PER OPERATION
IN FIELD-PROGRAMMABLE GATE ARRAYS
.
719
S.J.E. WILTON, S.-S. ANG, W. LUK
A METHODOLOGY FOR ENERGY EFFICIENT FPGA DESIGNS
USING MALLEABLE ALGORITHMS
.
729
J. OU, V.K. PRASANNA
POWER-DRIVEN DESIGN PARTITIONING
.
740
R. MUKHERJEE, S.O. MEMIK
POWER CONSUMPTION REDUCTION THROUGH DYNAMIC RECONFIGURATION
.
751
M.G. LORENZ, L. MENGIBAR, M.G. VALDERAS, L. ENTRENA
COPROCESSING ARCHITECTURES
THE XPP ARCHITECTURE AND ITS CO-SIMULATION
WITHIN THE SIMULINK ENVIRONMENT
.
761
M. PETROV, T. MURGAN, F. MAY, M. VORBACH, P. ZIPF, M. GLESNER
AN FPGA BASED COPROCESSOR FOR THE CLASSIFICATION
OF TISSUE PATTERNS IN PROSTATIC CANCER
.
771
M.A. TAHIR, A. BOURIDANE, F. KURUGOLLU
INCREASING ILP OF RISC MICROPROCESSORS
THROUGH CONTROL-FLOW BASED RECONFIGURATION
.
781
S. K¨OHLER, J. BRAUNES, T. PREUSSER, M. ZABEL, R.G. SPALLEK
USING OF FPGA COPROCESSOR FOR IMPROVING THE EXECUTION SPEED
OF THE PATTERN RECOGNITION ALGORITHM FOR ATLAS *
HIGH ENERGY PHYSICS EXPERIMENT
.
791
C. HINKELBEIN, A. KHOMICH, A. KUGEL, R. M¨ANNER, M. M¨ULLER
EMBEDDED TUTORIALS
PARTIAL AND DYNAMICALLY RECONFIGURATION OF XILINX VIRTEX-II FPGAS
.
801
B. BLODGET, C. BOBDA, M. HUEBNER, A. NIYONKURU
SYSTEMC FOR THE DESIGN AND MODELING OF PROGRAMMABLE SYSTEMS
.
811
A. DONLIN, A. BRAUN, A. ROSE
AN EVOLVABLE HARDWARE TUTORIAL
.
821
J. TORRESEN
TABLE OF CONTENTS XXI
DYNAMIC RECONFIGURATION 2
A RUNTIME ENVIRONMENT
FOR RECONFIGURABLE HARDWARE OPERATING SYSTEMS
.
831
H. WALDER, M. PLATZNER
A DYNAMICALLY RECONFIGURABLE
ASYNCHRONOUS FPGA ARCHITECTURE
.
836
X. JIA, J. RAJAGOPALAN, R. VEMURI
HARDWARE SUPPORT FOR DYNAMIC RECONFIGURATION IN RECONFIGURABLE
SOC ARCHITECTURES
.
842
B. GRIESE, E. VONNAHME, M. PORRMANN, U. R¨UCKERT
PHYSICAL DESIGN 2
OPTIMAL ROUTING-CONSCIOUS DYNAMIC PLACEMENT
FOR RECONFIGURABLE DEVICES
.
847
A. AHMADINIA, C. BOBDA, S.P. FEKETE, J. TEICH, J.C. VAN DER VEEN
OPTIMIZING THE PERFORMANCE OF THE SIMULATED ANNEALING
BASED PLACEMENT ALGORITHMS FOR ISLAND-STYLE FPGAS
.
852
A. DANILIN, S. SAWITZKI
AUTOMATING THE LAYOUT OF RECONFIGURABLE SUBSYSTEMS
VIA TEMPLATE REDUCTION
.
857
S. PHILLIPS, A. SHARMA, S. HAUCK
ACCELERATION APPLICATION 2
FPGA ACCELERATION OF RIGID MOLECULE INTERACTIONS
.
862
T. VAN COURT, Y. GU, M. HERBORDT
MAPPING DSP APPLICATIONS TO A HIGH-PERFORMANCE RECONFIGURABLE
COARSE-GRAIN DATA-PATH
.
868
M.D. GALANIS, G. THEODORIDIS, S. TRAGOUDAS, D. SOUDRIS,
C.E. GOUTIS
EXPLORING POTENTIAL BENEFITS OF 3D FPGA INTEGRATION
.
874
C. ABABEI, P. MAIDEE, K. BAZARGAN
SYSTEM LEVEL DESIGN
SYSTEM-LEVEL MODELING OF DYNAMICALLY RECONFIGURABLE CO-PROCESSORS
.
881
Y. QU, K. TIENSYRJ¨A, K. MASSELOS
A DEVELOPMENT SUPPORT SYSTEM FOR APPLICATIONS THAT USE
DYNAMICALLY RECONFIGURABLE HARDWARE
.
886
J. CANAS FERREIRA, J. SILVA MATOS
XXII TABLE OF CONTENTS
PHYSICAL INTERCONNECT
INTERCONNECT-AWARE MAPPING OF APPLICATIONS
TO COARSE-GRAIN RECONFIGURABLE ARCHITECTURES
.
891
N. BANSAL, S. GUPTA, N. DUTT, A. NICOLAU, R. GUPTA
ANALYSIS OF A HYBRID INTERCONNECT ARCHITECTURE
FOR DYNAMICALLY RECONFIGURABLE FPGAS
.
900
R. HUANG, M. HANDA, R. VEMURI
COMPUTATIONAL MODELS
MAPPING BASIC RECURSIVE STRUCTURES
TO RUNTIME RECONFIGURABLE HARDWARE
.
906
H. ELGINDY, G. FERIZIS
IMPLEMENTATION OF THE EXTENDED EUCLIDEAN ALGORITHM
FOR THE TATE PAIRING ON FPGA
.
911
T. ITO, Y. SHIBATA, K. OGURI
ACCELERATION APPLICATIONS 3
JAVA TECHNOLOGY IN AN FPGA
.
917
M. SCHOEBERL
HARDWARE/SOFTWARE IMPLEMENTATION OF FPGA-TARGETED
MATRIX-ORIENTED SAT SOLVERS
.
922
V. SKLYAROV, I. SKLIAROVA, B. PIMENTEL, J. ARRAIS
THE CHESS MONSTER HYDRA
.
927
C. DONNINGER, U. LORENZ
ARITHMETIC 3
FPGA-EFFICIENT HYBRID LUT/CORDIC ARCHITECTURE
.
933
I. JANISZEWSKI, H. MEUTH, B. HOPPE
A MULTIPLEXER-BASED CONCEPT FOR RECONFIGURABLE MULTIPLIER ARRAYS
.
938
O.A. PF¨ANDER, R. HACKER, H.-J. PFLEIDERER
DESIGN AND IMPLEMENTATION OF A CFAR PROCESSOR
FOR TARGET DETECTION
.
943
C. TORRES-HUITZIL, R. CUMPLIDO-PARRA, S. L´OPEZ-ESTRADA
SIGNAL PROCESSING 2
A PARALLEL FFT ARCHITECTURE FOR FPGAS
.
948
J. PALMER, B. NELSON
TABLE OF CONTENTS XXIII
FPGA CUSTOM DSP FOR ECG SIGNAL ANALYSIS AND COMPRESSION
.
954
M.M. PEIR´O, F. BALLESTER, G. PAYA, J. BELENGUER, R. COLOM,
R. GADEA
FPGA IMPLEMENTATION OF ADAPTIVE MULTIUSER DETECTOR
FOR DS-CDMA SYSTEMS
.
959
Q.-T. HO, D. MASSICOTTE
SYSTEM-ON-CHIP 2
SIMULATION PLATFORM FOR ARCHITECTURAL VERIFICATION AND
PERFORMANCE ANALYSIS IN CORE-BASED SOC DESIGN
.
965
U. BIDARTE, A. ASTARLOA, J.L. MART´*N, J. ANDREU
A LOW POWER FPAA FOR WIDE BAND APPLICATIONS
.
970
E. SCH¨ULER, L. CARRO
AUTOMATED METHOD TO GENERATE BITSTREAM INTELLECTUAL PROPERTY
CORES FOR VIRTEX FPGAS
.
975
E.L. HORTA, J.W. LOCKWOOD
IMAGE PROCESSING 2
REAL-TIME COMPUTATION OF THE GENERALIZED HOUGH TRANSFORM
.
980
T. MARUYAMA
MINIMUM SUM OF ABSOLUTE DIFFERENCES IMPLEMENTATION
IN A SINGLE FPGA DEVICE
.
986
J. OLIVARES, J. HORMIGO, J. VILLALBA, I. BENAVIDES
DESIGN AND EFFICIENT FPGA IMPLEMENTATION OF AN RGB
TO YCRCB COLOR SPACE CONVERTER USING DISTRIBUTED ARITHMETIC
.
991
F. BENSAALI, A. AMIRA
CRYPTOGRAPHY AND COMPRESSION
HIGH THROUGHPUT SERPENT ENCRYPTION IMPLEMENTATION
.
996
J. L´AZARO, A. ASTARLOA, J. ARIAS, U. BIDARTE, C. CUADRADO
IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOSYSTEMS OVER GF(2
N
)
IN OPTIMAL NORMAL BASIS ON A RECONFIGURABLE COMPUTER
.
1001
S. BAJRACHARYA, C. SHU, K. GAJ, T. EL-GHAZAWI
WAVELET-BASED IMAGE COMPRESSION
ON THE RECONFIGURABLE COMPUTER ACE-V
.
1006
H. G¨ADKE, A. KOCH
XXIV TABLE OF CONTENTS
NETWORK APPLICATIONS AND ARCHITECTURES
A RECONFIGURABLE COMMUNICATION PROCESSOR COMPATIBLE
WITH DIFFERENT INDUSTRIAL FIELDBUSES
.
1011
M.D. VALD´ES, M.
´
ANGEL DOM´*NGUEZ, M.J. MOURE,
C. QUINT´ANS
MULTITHREADING IN A HYPER-PROGRAMMABLE PLATFORM
FOR NETWORKED SYSTEMS
.
1017
P. JAMES-ROXBY, G. BREBNER
AN ENVIRONMENT FOR EXPLORING DATA-DRIVEN ARCHITECTURES
.
1022
R. FERREIRA, J.M.P. CARDOSO, H.C. NETO
FPGA IMPLEMENTATION OF A NOVEL ALL DIGITAL PLL ARCHITECTURE
FOR PCR RELATED MEASUREMENTS IN DVB-T
.
1027
C. MANNINO, H. RABAH, C. TANOUGAST, Y. BERVILLER, M. JANIAUT,
S. WEBER
NETWORK ON CHIP AND ADAPTIVE ARCHITECTURES
A DYNAMIC NOC APPROACH FOR COMMUNICATION
IN RECONFIGURABLE DEVICES
.
1032
C. BOBDA, M. MAJER, D. KOCH, A. AHMADINIA, J. TEICH
SCALABLE APPLICATION-DEPENDENT NETWORK ON CHIP ADAPTIVITY
FOR DYNAMICAL RECONFIGURABLE REAL-TIME SYSTEMS
.
1037
M. HUEBNER, M. ULLMANN, L. BRAUN, A. KLAUSMANN, J. BECKER
FIPRE: AN IMPLEMENTATION MODEL
TO ENABLE SELF-RECONFIGURABLE APPLICATIONS
.
1042
L. M¨OLLER, N. CALAZANS, F. MORAES, E. BRI*AO, E. CARVALHO,
D. CAMOZZATO
A STRUCTURED METHODOLOGY FOR SYSTEM-ON-AN-FPGA DESIGN
.
1047
P. SEDCOLE, P.Y.K. CHEUNG, G.A. CONSTANTINIDES, W. LUK
DEBUGGING AND TEST
SECURE LOGIC SYNTHESIS
.
1052
K. TIRI, I. VERBAUWHEDE
HARDWARE AND SOFTWARE DEBUGGING OF FPGA BASED
MICROPROCESSOR SYSTEMS THROUGH DEBUG LOGIC INSERTION
.
1057
M.G. VALDERAS, E. DEL TORRE, F. ARIZA, T. RIESGO
TABLE OF CONTENTS XXV
THE IMPLEMENTATION OF A FPGA HARDWARE DEBUGGER SYSTEM
WITH MINIMAL SYSTEM OVERHEAD
.
1062
J. TOMBS, M.A.A. ECHAN´OVE, F. MU*NOZ, V. BAENA, A. TORRALBA,
A. FERNANDEZ-LE´ON, F. TORTOSA
OPTIMIZATION OF TESTABILITY OF SEQUENTIAL CIRCUITS IMPLEMENTED
IN FPGAS WITH EMBEDDED MEMORY
.
1067
A. KRASNIEWSKI
ORGANIC AND BIOLOGY COMPUTING (POSTER)
FPGA IMPLEMENTATION OF A NEUROMIMETIC COCHLEA
FOR A BIONIC BAT HEAD
.
1073
C. CLARKE, L. QIANG, H. PEREMANS,
´
A. HERN´ANDEZ
FPGA-BASED COMPUTATION FOR MAXIMUM LIKELIHOOD
PHYLOGENETIC TREE EVALUATION
.
1076
T.S.T. MAK, K.P. LAM
PROCESSING REPETITIVE SEQUENCE STRUCTURES WITH MISMATCHES
AT STREAMING RATE
.
1080
A.A. CONTI, T. VAN COURT, M.C. HERBORDT
ARTIFICIAL NEURAL NETWORKS PROCESSOR *
A HARDWARE IMPLEMENTATION USING A FPGA
.
1084
XXVI TABLE OF CONTENTS
MAPPING AND COMPILERS (POSTER)
OBJECT ORIENTED PROGRAMMING PARADIGMS FOR THE VHDL
.
1107
J. BORGOSZ
USING RECONFIGURABLE HARDWARE THROUGH WEB SERVICES
IN DISTRIBUTED APPLICATIONS
.
1110
I. GONZALEZ, J. SANCHEZ-PASTOR, J.L. HERNANDEZ-ARDIETA,
F.J. GOMEZ-ARRIBAS, J. MARTINEZ
DATA REUSE IN CONFIGURABLE ARCHITECTURES WITH RAM BLOCKS
.
1113
N. BARADARAN, J. PARK, P.C. DINIZ
A NOVEL FPGA CONFIGURATION BITSTREAM GENERATION ALGORITHM
AND TOOL DEVELOPMENT
.
1116
K. SIOZIOS, G. KOUTROUMPEZIS, K. TATAS, D. SOUDRIS,
A. THANAILAKIS
AAA AND SYNDEX-IC: A METHODOLOGY AND A SOFTWARE FRAMEWORK
FOR THE IMPLEMENTATION OF REAL-TIME APPLICATIONS
ONTO RECONFIGURABLE CIRCUITS
.
1119
P. NIANG, T. GRANDPIERRE, M. AKIL, Y. SOREL
ARCHITECTURES (POSTER)
A SELF-RECONFIGURATION FRAMEWORK FOR MULTIPROCESSOR CSOPCS
.
1124
A. ASTARLOA, J. L´AZARO, U. BIDARTE, J.L. MART´*N,
A. ZULOAGA
A VIRTUAL FILE SYSTEM FOR DYNAMICALLY RECONFIGURABLE FPGAS
.
1127
A. DONLIN, P. LYSAGHT, B. BLODGET, G. TROEGER
VIRTUALIZING THE DIMENSIONS
OF A COARSE-GRAINED RECONFIGURABLE ARRAY
.
1130
T. RISTIM¨AKI, J. NURMI
DESIGN AND IMPLEMENTATION OF THE MEMORY SCHEDULER
FOR THE PC-BASED ROUTER
.
1133
T. MAREK, M. NOVOTN´Y, L. CRHA
ALGORITHMS AND IP (POSTER)
ANALOG SIGNAL PROCESSING RECONFIGURATION FOR SYSTEMS-ON-CHIP
USING A FIXED ANALOG CELL APPROACH
.
1136
E.E. FABRIS, L. CARRO, S. BAMPI
INTELLECTUAL PROPERTY PROTECTION FOR RNS CIRCUITS ON FPGAS
.
1139
L. PARRILLA, E. CASTILLO, A. GARC´*A, A. LLORIS
TABLE OF CONTENTS XXVII
FPGA IMPLEMENTATION OF A TOOL BREAKAGE DETECTION ALGORITHM
IN CNC MILLING MACHINES
.
1142
R. DEJ. ROMERO-TRONCOSO, G.H. RUIZ
IMPLEMENTATION OF A 3-D SWITCHING MEDIAN FILTERING SCHEME
WITH AN ADAPTIVE LUM-BASED NOISE DETECTOR
.
1146
M. DRUTAROVSK´Y, V. FISCHER
USING LOGARITHMIC ARITHMETIC
TO IMPLEMENT THE RECURSIVE LEAST SQUARES (QR) ALGORITHM IN FPGA
.
1149
J. SCHIER, A. HE*RM´ANEK
IMAGE PROCESSING (POSTER)
FPGA IMPLEMENTATION OF A VISION-BASED
MOTION ESTIMATION ALGORITHM FOR AN UNDERWATER ROBOT
.
1152
V. ILA, R. GARCIA, F. CHAROT, J. BATLLE
REAL-TIME DETECTION OF MOVING OBJECTS
.
1155
H. NIITSUMA, T. MARUYAMA
REAL-TIME VISUAL MOTION DETECTION OF OVERTAKING CARS
FOR DRIVING ASSISTANCE USING FPGAS
.
1158
S. MOTA, E. ROS, J. D´*AZ, E.M. ORTIGOSA, R. AGIS,
R. CARRILLO
VERSATILE IMAGING ARCHITECTURE BASED ON A SYSTEM ON CHIP
.
1162
P. CHALIMBAUD, F. BERRY
A HARDWARE IMPLEMENTATION OF A CONTENT BASED
IMAGE RETRIEVAL ALGORITHM
.
1165
C. SKARPATHIOTIS, K.R. DIMOND
PHD FORUM (POSTER)
OPTIMIZATION ALGORITHMS
FOR DYNAMIC RECONFIGURABLE EMBEDDED SYSTEMS
.
1168
A. AHMADINIA
LOW POWER RECONFIGURABLE DEVICES
.
1169
A. GAYASEN
CODE RE-ORDERING FOR A CLASS OF RECONFIGURABLE MICROPROCESSORS
.
1170
B.F. VEALE, J.K. ANTONIO, M.P. TULL
DESIGN SPACE EXPLORATION
FOR DISTRIBUTED HARDWARE RECONFIGURABLE SYSTEMS
.
1171
C. HAUBELT
XXVIII TABLE OF CONTENTS
TPR: THREE-D PLACE AND ROUTE FOR FPGAS
.
1172
C. ABABEI
IMPLEMENTING GRAPHICS SHADERS USING FPGAS
.
1173
D.B. THOMAS, W. LUK
PREEMPTIVE HARDWARE TASK MANAGEMENT
.
1174
D. KOCH
AUTOMATED SPECULATION AND PARALLELISM
IN HIGH PERFORMANCE NETWORK APPLICATIONS
.
1175
G. SCHELLE, D. GRUNWALD
AUTOMATED MAPPING OF COARSE-GRAIN PIPELINED APPLICATIONS
TO FPGA SYSTEMS
.
1176
H.E. ZIEGLER
A SPECIFIC SCHEDULING FLOW
FOR DYNAMICALLY RECONFIGURABLE HARDWARE
.
1178
J. RESANO
DESIGN AND EVALUATION OF AN FPGA ARCHITECTURE
FOR SOFTWARE PROTECTION
.
1180
J. ZAMBRENO
SCALABLE DEFECT TOLERANCE BEYOND THE SIA ROADMAP
.
1181
M. MISHRA
RUN-TIME RECONFIGURATION MANAGEMENT
FOR ADAPTIVE HIGH-PERFORMANCE COMPUTING SYSTEMS
.
1183
M. TAHER, T. EL-GHAZAWI
OPTIMIZED FIELD PROGRAMMABLE GATE ARRAY BASED
FUNCTION EVALUATION
.
1184
N. SIDAHAO
MEMMAP-PD: PERFORMANCE DRIVEN TECHNOLOGY MAPPING ALGORITHM
FOR FPGAS WITH EMBEDDED MEMORY BLOCKS
.
1185
R. MANIMEGALAI, A. MANOJKUMAR, B. JAYARAM, V. KAMAKOTI
A SYSTEM ON CHIP DESIGN FRAMEWORK
FOR PRIME NUMBER VALIDATION USING RECONFIGURABLE HARDWARE
.
1186
R.C.C. CHEUNG
ON COMPUTING MAXIMUM LIKELIHOOD PHYLOGENY USING FPGA
.
1188
T.S.T. MAK, K.P. LAM
MINIMISING RECONFIGURATION OVERHEADS IN EMBEDDED APPLICATIONS
.
1189
U. MALIK
TABLE OF CONTENTS XXIX
APPLICATION SPECIFIC SMALL-SCALE RECONFIGURABILITY
.
1190
V.V. KUMAR
EFFICIENT FPGA-BASED SECURITY KERNELS
.
1191
Z.K. BAKER
AUTHOR INDEX
.
1193 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV019532774 |
| callnumber-first | Q - Science |
| callnumber-label | QA75 |
| callnumber-raw | QA75 TK7895.G36 |
| callnumber-search | QA75 TK7895.G36 |
| callnumber-sort | QA 275 |
| callnumber-subject | QA - Mathematics |
| classification_rvk | SS 4800 |
| classification_tum | ELT 360f |
| ctrlnum | (OCoLC)56477675 (DE-599)BVBBV019532774 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| id | DE-604.BV019532774 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:07:56Z |
| institution | BVB |
| institution_GND | (DE-588)10086227-5 |
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| physical | XXIX, 1198 S. Ill., graph. Darst. |
| publishDate | 2004 |
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| publisher | Springer |
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| series | Lecture Notes in Computer Science |
| series2 | Lecture Notes in Computer Science |
| spelling | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings Jürgen Becker ... (eds.) FPL 2004 Fiel-programmable logic and applcations Berlin u.a. Springer 2004 XXIX, 1198 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture Notes in Computer Science 3203 Application rasuqam Circuit reconfigurable rasuqam Configuration rasuqam Cryptographie (Informatique) rasuqam Logique à réseau programmable - Congrès Logique à réseau programmable rasuqam Processeur de signal numérique rasuqam Réseau logique programmable par l'utilisateur rasuqam Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array (DE-588)4347749-5 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Rekonfiguration (DE-588)4306238-6 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2004 Antwerpen gnd-content Field programmable gate array (DE-588)4347749-5 s DE-604 Rekonfiguration (DE-588)4306238-6 s System-on-Chip (DE-588)4740357-3 s Becker, Jürgen Sonstige oth FPL 14 2004 Antwerpen Sonstige (DE-588)10086227-5 oth Lecture Notes in Computer Science 3203 (DE-604)BV000000607 3203 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012906078&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings Lecture Notes in Computer Science Application rasuqam Circuit reconfigurable rasuqam Configuration rasuqam Cryptographie (Informatique) rasuqam Logique à réseau programmable - Congrès Logique à réseau programmable rasuqam Processeur de signal numérique rasuqam Réseau logique programmable par l'utilisateur rasuqam Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array (DE-588)4347749-5 gnd System-on-Chip (DE-588)4740357-3 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4740357-3 (DE-588)4306238-6 (DE-588)1071861417 |
| title | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings |
| title_alt | FPL 2004 Fiel-programmable logic and applcations |
| title_auth | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings |
| title_exact_search | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings |
| title_full | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings Jürgen Becker ... (eds.) |
| title_fullStr | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings Jürgen Becker ... (eds.) |
| title_full_unstemmed | Field programmable logic and applications 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings Jürgen Becker ... (eds.) |
| title_short | Field programmable logic and applications |
| title_sort | field programmable logic and applications 14th international conference fpl 2004 antwerp belgium august 30 september 1 2004 proceedings |
| title_sub | 14th International Conference , FPL 2004, Antwerp, Belgium, August 30 - September 1, 2004 ; proceedings |
| topic | Application rasuqam Circuit reconfigurable rasuqam Configuration rasuqam Cryptographie (Informatique) rasuqam Logique à réseau programmable - Congrès Logique à réseau programmable rasuqam Processeur de signal numérique rasuqam Réseau logique programmable par l'utilisateur rasuqam Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array (DE-588)4347749-5 gnd System-on-Chip (DE-588)4740357-3 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| topic_facet | Application Circuit reconfigurable Configuration Cryptographie (Informatique) Logique à réseau programmable - Congrès Logique à réseau programmable Processeur de signal numérique Réseau logique programmable par l'utilisateur Réseaux logiques programmables par l'utilisateur - Congrès Field programmable gate arrays Congresses Programmable array logic Congresses Field programmable gate array System-on-Chip Rekonfiguration Konferenzschrift 2004 Antwerpen |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012906078&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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