Verfügbarkeit: Microelectronic circuits

Microelectronic circuits:

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Bibliographische Detailangaben
1. Verfasser:	Sedra, Adel S. (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	New York Oxford Univ. Press 2004
Ausgabe:	5. ed.
Schriftenreihe:	The Oxford series in electrical and computer engineering
Schlagworte:	Electronic circuits Integrated circuits Elektronische Schaltung Integrierte Schaltung Mikroelektronik Einführung
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	Getr. Zählung Ill., graph. Darst. 1 CD-ROM (12 cm)
ISBN:	0195142519

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Datensatz im Suchindex

_version_	1804132790022701056
adam_text	FIFTH EDITION MICROELECTRONIC CIRCUITS ADEL S. SEDRA UNIVERSITY OF WATERLOO KENNETH C. SMITH UNIVERSITY OF TORONTO NEW YORK OXFORD OXFORD UNIVERSITY PRESS 2004 CONDENSED TABLE OF CONTENTS PREFACE XXIII PART I DEVICES AND BASIC CIRCUITS 2 1 INTRODUCTION TO ELECTRONICS 5 2 OPERATIONAL AMPLIFIERS 63 3 DIODES 139 4 MOS FIELD-EFFECT TRANSISTORS (MOSFETS) 235 5 BIPOLAR JUNCTION TRANSISTORS (BJTS) 377 ANALOG AND DIGITAL INTEGRATED PART II CIRCUITS 542 6 SINGIE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS 545 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS 687 8 FEEDBACK 791 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS 871 10 DIGITAL CMOS LOGIC CIRCUITS 949 PART III SELECTED TOPICS 1010 11 MEMORY AND ADVANCED DIGITAL CIRCUITS 1013 12 FILTERS AND TUNED AMPLIFIERS 7083 13 SIGNAL GENERATORS AND WAVEFORM-SHAPING CIRCUITS 1165 14 OUTPUT STAGES AND POWER AMPLIFIERS 1229 APPENDIXES A VLSI FABRICATION TECHNOLOGY A-1 B TWO-PORT NETWORK PARAMETERS B-1 C SOME USEFUL NETWORK THEOREMS C-1 D SINGLE-TIME-CONSTANT CIRCUITS D-1 E S-DOMAIN ANALYSIS: POLES, ZEROS, AND BODE PLOTS E-1 F BIBLIOGRAPHY F-1 G STANDARD RESISTANCE VALUES AND UNIT PREFIXES G-1 H ANSWERS TO SELECTED PROBLEMS H-1 INDEX IN-1 PREFACE XXIII ** PART I DEVICES AND BASIC CIRCUITS 2 1 INTRODUCTION TO ELECTRONICS 5 INTRODUCTION 5 1.1 SIGNALS 6 1.2 FREQUENCY SPECTRUM OF SIGNALS 7 1.3 ANALOG AND DIGITAL SIGNALS 10 1.4 AMPLIFIERS 13 1.4.1 SIGNAL AMPLIFICATION 13 1.4.2 AMPLIFIER CIRCUIT SYMBOL 14 1.4.3 VOLTAGEGAIN 14 1.4.4 POWER GAIN AND CURRENT GAIN 15 1.4.5 EXPRESSING GAIN IN DECIBELS 15 1.4.6 THE AMPLIFIER POWER SUPPLIES 16 1.4.7 AMPLIFIER SATURATION 18 1.4.8 NONLINEAR TRANSFER CHARACTERISTICS AND BIASING 19 1.4.9 SYMBOL CONVENTION 22 1.5 CIRCUIT MODELS FOR AMPLIFIERS 23 1.5.1 VOLTAGE AMPLIFIERS 23 1.5.2 CASCADED AMPLIFIERS 25 1.5.3 OTHER AMPLIFIER TYPES 27 1.5.4 RELATIONSHIPS BETWEEN THE FOUR AMPLIFIER MODELS 27 1.6 FREQUENCY RESPONSE OF AMPLIFIERS 37 1.6.1 MEASURING THE AMPLIFIER FREQUENCY RESPONSE 31 1.6.2 AMPLIFIER BANDWIDTH 32 1.6.3 EVALUATING THE FREQUENCY RESPONSE OF AMPLIFIERS 35 1.6.4 SINGLE-TIME-CONSTANT NETWORKS 33 1.6.5 CLASSIFICATION OF AMPLIFIERS BASED ON FREQUENCY RESPONSE 38 1.7 DIGITAL LOGIC INVERTERS 40 1.7.1 FUNCTION OF THE INVERTER 40 1.7.2 THE VOLTAGE TRANSFER CHARACTERISTIC (VTC) 41 1.7.3 NOISE MARGINS 42 1.7.4 THE IDEAL VTC 43 1.7.5 INVERTER IMPLEMENTATION 43 1.7.6 POWER DISSIPATION 45 1.1.1 PROPAGATION DELAY 46 1.8 CIRCUIT SIMULATION USING SPICE 49 SUMMARY 50 PROBLEMS 51 DETAILED TABLE OF CONTENTS VII 2 OPERATIONAL AMPLIFIERS 63 INTRODUCTION 63 2.1 THE IDEAL OP AMP 64 2.1.1 THE OP-AMP TERMINALS 64 2.1.2 FUNCTION AND CHARACTERISTICS OF THE IDEAL OP AMP 65 2.1.3 DIFFERENTIAL AND COMMON-MODE SIGNALS 67 2.2 THE INVERTING CONFIGURATION 68 2.2.1 THE CLOESED-LOOP GAIN 69 2.2.2 EFFECT OF FINITE OPEN-LOOP GAIN 71 2.2.3 INPUT AND OUTPUT RESISTANCES 72 2.2.4 AN IMPORTANT APPLICATIONTHE WEIGHTED SUMMER 75 2.3 THE NONINVERTING CONFIGURATION 77 2.3.1 THE CLOSED-LOOP GAIN 77 2.3.2 CHARACTERISTICS OF THE NONINVERTING CONFIGURATION 78 2.3.3 EFFECT OF FINITE OPEN-LOOP GAIN 78 2.3.4 THE VOLTAGE FOLLOWER 79 2.4 DIFFERENCE AMPLIFIERS 81 2.4.1 A SINGLE OP-AMP DIFFERENCE AMPLIFIER 82 2.4.2 A SUPERIOR CIRCUITTHE INSTRUMENTATION AMPLIFIER 85 2.5 EFFECT OF FINITE OPEN-LOOP GAIN AND BANDWIDTH ON CIRCUIT PERFORMANCE 89 2.5.1 FREQUENCY DEPENDENCE OF THE OPEN-LOOP GAIN 89 2.5.2 FREQUENCY RESPONSE OF CLOSED-LOOP AMPLIFIERS 91 2.6 LARGE-SIGNAL OPERATION OF OP AMPS 94 2.6.1 OUTPUT VOLTAGE SATURATION 94 2.6.2 OUTPUT CURRENT LIMITS 94 2.6.3 SLEWRATE 95 2.6.4 FULL-POWER BANDWIDTH 97 2.7 DC IMPERFECTIONS 98 2.7.1 OFFSET VOLTAGE 98 2.7.2 INPUT BIAS AND OFFSET CURRENTS 102 2.8 INTEGRATORS AND DIFFERENTIATORS 105 2.8.1 THE INVERTING CONFIGURATION WITH GENERAL IMPEDANCES 105 2.8.2 THE INVERTING INTEGRATOR 707 2.8.3 THE OP-AMP DIFFERENTIATOR 772 2.9 THE SPICE OP-AMP MODEL AND SIMULATION EXAMPLES 774 2.9.1 LINEAR MACROMODEL 775 2.9.2 NONLINEAR MACROMODEL 779 SUMMARY 722 PROBLEMS 723 3 DIODES 139 INTRODUCTION 139 3.1 THE IDEAL DIODE 140 3.1.1 CURRENT-VOLTAGE CHARACTERISTIC 140 3.1.2 A SIMPLE APPLICATION: THE RECTIFIER 747 3.1.3 ANOTHER APPLICATION: DIODE LOGIC GATES 144 DETAILED TABLE OF CONTENTS 3.2 TERMINAL CHARACTERISTICS OF JUNCTION DIODES 147 3.2.1 THE FORWARD-BIAS REGION 148 3.2.2 THE REVERSE-BIAS REGION 152 3.2.3 THE BREAKDOWN REGION 152 3.3 MODELING THE DIODE FORWARD CHARACTERISTIC 153 3.3.1 THE EXPONENTIAL MODEL 153 3.3.2 GRAPHICAL ANALYSIS USING THE EXPONENTIAL MODEL 154 3.3.3 ITERATIVE ANALYSIS USING THE EXPONENTIAL MODEL 154 3.3.4 THE NEEDFOR RAPID ANALYSIS 155 3.3.5 THE PIECEWISE-LINEAR MODEL 155 3.3.6 THE CONSTANT-VOLTAGE-DROP MODEL 157 3.3.7 THE IDEAL-DIODE MODEL 158 3.3.8 THE SMALL-SIGNAL MODEL 159 3.3.9 USE OF THE DIODE FORWARD DROP IN VOLTAGE REGULATION 163 3.3.10 SUMMARY 165 3.4 OPERATION IN THE REVERSE BREAKDOWN REGION* ZENER DIODES 167 3.4.1 SPECIFYING AND MODELING THE ZENER DIODE 167 3.4.2 USE OF THE ZENER AS A SHUNT REGULATOR 168 3.4.3 TEMPERATURE EFFECTS 170 3.4.4 A FINAL REMARK 171 3.5 RECTIFIER CIRCUITS 171 3.5.1 THE HALF-WAVE RECTIFIER 172 3.5.2 THE FUELL-WAVE RECTIFIER 174 3.5.3 THE BRIDGE RECTIFIER 176 3.5.4 THE RECTIFIER WITH A FILTER CAPACITOR* THE PEAK RECTIFIER 177 3.5.5 PRECISION HALF-WAVE RECTIFIER* THE SUPER DIODE 183 3.6 LIMITING AND CLAMPING CIRCUITS 184 3.6.1 LIMITER CIRCUITS 184 3.6.2 THE CLAMPED CAPACITOR OR DC RESTORER 187 3.6.3 THE VOLTAGE DOUBLER 189 3.7 PHYSICAL OPERATION OF DIODES 190 3.7.1 BASIC SEMICONDUCTOR CONCEPTS 190 3.7.2 THE PN JUNCTION UNDER OPEN-CIRCUIT CONDITIONS 196 3.7.3 THE/W JUNCTION UNDER REVERSE-BIAS CONDITIONS 199 3.7.4 THE PN JUNCTION IN THE BREAKDOWN REGION 203 3.7.5 THE PN JUNCTION UNDER FORWARD-BIAS CONDITIONS 204 3.7.6 SUMMARY 208 3.8 SPECIAL DIODE TYPES 209 3.8.1 THE SCHOTTKY-BARRIER DIODE (SBD) 210 3.8.2 VARACTORS 210 3.8.3 PHOTODIODES 210 3.8.4 LIGHT-EMITTING DIODES (LEDS) 211 3.9 THE SPICE DIODE MODEL AND SIMULATION EXAMPLES 212 3.9.1 THE DIODE MODEL 212 3.9.2 THE ZENER DIODE MODEL 213 SUMMARY 217 PROBLEMS 218 DETAILED TABLE OF CONTENTS FCY IX 4 MOS FIELD-EFFECT TRANSISTORS (MOSFETS) 235 INTRODUCTION 235 4.1 DEVICE STRUCTURE AND PHYSICAL OPERATION 236 4.1.1 DEVICE STRUCTURE 236 4.1.2 OPERATION WITH NO GATE VOLTAGE 238 4.1.3 CREATING A CHANNEL FOR CURRENT FLOW 238 4.1.4 APPLYING A SMALL V DS 239 4.1.5 OPERATION AS V DS IS INCREASED 241 4.1.6 DERIVATION OF THE I D -V DS RELATIONSHIP 243 4.1.7 THE P-CHANNEL MOSFET 247 4.1.8 COMPLEMENTARY MOS OR CMOS 247 4.1.9 OPERATING THE MOS TRANSISTOR IN THE SUBTHRESHOLD REGION 248 4.2 CURRENT-VOLTAGE CHARACTERISTICS 248 4.2.1 CIRCUIT SYMBOL 248 4.2.2 THE I D -V DS CHARACTERISTICS 249 4.2.3 FINITE OUTPUT RESISTANCE IN SATURATION 253 4.2.4 CHARACTERISTICS OF THE P-CHANNEL MOSFET 256 4.2.5 THE ROLE OF THE SUBSTRATETHE BODY EFFECT 258 4.2.6 TEMPERATURE EFFECTS 259 4.2.7 BREAKDOWN AND INPUT PROTECTION 259 4.2.8 SUMMARY 260 4.3 MOSFET CIRCUITS AT DC 262 4.4 THE MOSFET AS AN AMPLIFIER AND AS A SWITCH 270 A.A. 1 LARGE-SIGNAL OPERATIONTHE TRANSFER CHARACTERISTIC 271 4.4.2 GRAPHICAL DERIVATION OF THE TRANSFER CHARACTERISTIC 273 4.4.3 OPERATION AS A SWITCH 274 4.4.4 OPERATION AS A LINEAR AMPLIFIER 274 4.4.5 ANALYTICAL EXPRESSIONS FOR THE TRANSFER CHARACTERISTIC 275 4.4.6 A FINAL REMARK ON BIASING 280 4.5 BIASING IN MOS AMPLIFIER CIRCUITS 280 4.5.1 BIASING BY FIXING V GS 280 4.5.2 BIASING BY FIXING V G AND CONNECTING A RESISTANCE IN THE SOURCE 281 4.5.3 BIASING USING A DRAIN-TO-GATE FEEDBACK RESISTOR 284 4.5.4 BIASING USING A CONSTANT-CURRENT SOURCE 285 4.5.5 A FINAL REMARK 287 4.6 SMALL-SIGNAL OPERATION AND MODELS 287 4.6.1 THE DC BIAS POINT 287 4.6.2 THE SIGNAL CURRENT IN THE DRAIN TERMINAL 288 4.6.3 THE VOLTAGE GAIN 289 4.6.4 SEPARATING THE DC ANALYSIS AND THE SIGNAL ANALYSIS 290 4.6.5 SMALL-SIGNAL EQUIVALENT-CIRCUIT MODELS 290 4.6.6 THE TRANSCONDUCTANCE G M 292 4.6.7 THE T EQUIVALENT-CIRCUIT MODEL 295 4.6.8 MODELING THE BODY EFFECT 296 4.6.9 SUMMARY 297 4.1 SINGLE-STAGE MOS AMPLIFIERS 299 4.7.1 THE BASIC STRUCTURE 299 4.7.2 CHARACTERIZING AMPLIFIERS 301 4.7.3 THE COMMON-SOURCE (CS) AMPLIFIER 306 4.7.4 THE COMMON-SOURCE AMPLIFIER WITH A SOURCE RESISTANCE 309 DETAILED TABLE OF CONTENTS 4.7.5 THE COMMON-GATE (CG) AMPLIFIER 311 4.7.6 THE COMMON-DRAIN OR SOURCE-FOLLOWER AMPLIFIER 315 4.7.7 SUMMARY AND COMPARISONS 318 4.8 THE MOSFET INTERNAL CAPACITANCES AND HIGH-FREQUENCY MODEL 320 4.8.1 THE GATE CAPACITIVE EFFECT 321 4.8.2 THE JUNCTION CAPACITANCES 322 4.8.3 THE HIGH-FREQUENCY MOSFET MODEL 322 4.8.4 THE MOSFET UNITY-GAIN FREQUENCY (F R ) 324 4.8.5 SUMMARY 325 4.9 FREQUENCY RESPONSE OF THE CS AMPLIFIER 326 4.9.1 THE THREE FREQUENCY BANDS 326 4.9.2 THE HIGH-FREQUENCY RESPONSE 328 4.9.3 THE LOW-FREQUENCY RESPONSE 332 4.9 .4 A FINAL REMARK 336 4.10 THE CMOS DIGITAL LOGIC INVERTER 336 4.10.1 CIRCUIT OPERATION 337 4.10.2 THE VOLTAGE TRANSFER CHARACTERISTIC 339 4.10.3 DYNAMIC OPERATION 342 4.10.4 CURRENT FLOW AND POWER DISSIPATION 345 4.10.5 SUMMARY 346 4.11 THE DEPLETION-TYPE MOSFET 346 4.12 THE SPICE MOSFET MODEL AND SIMULATION EXAMPLE 351 4.12.1 MOSFET MODELS 351 4.12.2 MOSFET MODEL PARAMETERS 352 SUMMARY 359 PROBLEMS 360 5 BIPOLAR JUNCTION TRANSISTORS (BJTS) 377 INTRODUCTION 377 5.1 DEVICE STRUCTURE AND PHYSICAL OPERATION 378 5.1.1 SIMPLIFIED STRUCTURE AND MODES OF OPERATION 378 5.1.2 OPERATION OF THE NPN TRANSISTOR IN THE ACTIVE MODE 380 5.1.3 STRUCTURE OF ACTUAL TRANSISTORS 386 5.1.4 THE EBERS-MOLL (EM) MODEL 387 5.1.5 OPERATION IN THE SATURATION MODE 390 5.1.6 THE PNP TRANSISTOR 391 5.2 CURRENT-VOLTAGE CHARACTERISTICS 392 5.2.1 CIRCUIT SYMBOLS AND CONVENTIONS 392 5.2.2 GRAPHICAL REPRESENTATION OF TRANSISTOR CHARACTERISTICS 397 5.2.3 DEPENDENCE OF I C ON THE COLLECTOR VOLTAGETHE EARLY EFFECT 399 5.2.4 THE COMMON-EMITTER CHARACTERISTICS 401 5.2.5 TRANSISTOR BREAKDOWN 406 5.2.6 SUMMARY 407 5.3 THE BJT AS AN AMPLIFIER AND AS A SWITCH 407 5.3.1 LARGE-SIGNAL OPERATIONTHE TRANSFER CHARACTERISTIC 410 5.3.2 AMPLIFIER GAIN 412 5.3.3 GRAPHICAL ANALYSIS 415 5.3.4 OPERATION AS A SWITCH 419 5.4 BJT CIRCUITS AT DC 421 DETAILED TABLE OF CONTENTS 5.5 BIASING IN BJT AMPLIFIER CIRCUITS 436 5.5.1 THE CLASSICAL DISCRETE-CIRCUIT BIAS ARRANGEMENT 436 5.5.2 A TWO-POWER-SUPPLY VERSION OF THE CLASSICAL BIAS ARRANGEMENT 440 5.5.3 BIASING USING A COLLECTOR-TO-BASE FEEDBACK RESISTOR 441 5.5.4 BIASING USING A CONSTANT-CURRENT SOURCE 442 5.6 SMALL-SIGNAL OPERATION AND MODELS 443 5.6.1 THE COLLECTOR CURRENT AND THE TRANSCONDUCTANCE 443 5.6.2 THE BASE CURRENT AND THE INPUT RESISTANCE AT THE BASE 445 5.6.3 THE EMITTER CURRENT AND THE INPUT RESISTANCE AT THE EMITTER 446 5.6.4 VOLTAGE GAIN 447 5.6.5 SEPARATING THE SIGNAL AND THE DC QUANTITIES 448 5.6.6 THE HYBRID-7R MODEL 448 5.6.7 THE T MODEL 449 5.6.8 APPLICATION OF THE SMALL-SIGNAL EQUIVALENT CIRCUITS 450 5.6.9 PERFORMING SMALL-SIGNAL ANALYSIS DIRECTLY ON THE CIRCUIT DIAGRAM 457 5.6.10 AUGMENTING THE SMALL-SIGNAL MODELS TO ACCOUNT FOR THE EARLY EFFECT 457 5.6.11 SUMMARY 458 5.7 SINGLE-STAGE BJT AMPLIFIERS 460 5.7.1 THE BASIC STRUCTURE 460 5.7.2 CHARACTERIZING BJT AMPLIFIERS 461 5.7.3 THE COMMON-EMITTER (CE) AMPLIFIER 467 5.7.4 THE COMMON-EMITTER AMPLIFIER WITH AN EMITTER RESISTANCE 470 5.7.5 THE COMMON-BASE (CB) AMPLIFIER 475 5.7.6 THE COMMON-COLLECTOR (CC) AMPLIFIER OR EMITTER FOLLOWER 478 5.7.7 SUMMARY AND COMPARISONS 483 5.8 THE BJT INTERNAL CAPACITANCES AND HIGH-FREQUENCY MODEL 485 5.8.1 THE BASE-CHARGING OR DIFFUSION CAPACITANCE C DE 486 5.8.2 THE BASE-EMITTER JUNCTION CAPACITANCE C JE 486 5.8.3 THE COLLECTOR-BASE JUNCTION CAPACITANCE C SS 487 5.8.4 THE HIGH-FREQUENCY HYBRID-W MODEL 487 5.8.5 THE CUTOFF FREQUENCY 487 5.8.6 SUMMARY 490 5.9 FREQUENCY RESPONSE OF THE COMMON-EMITTER AMPLIFIER 491 5.9.1 THE THREE FREQUENCY BANDS 491 5.9.2 THE HIGH-FREQUENCY RESPONSE 492 5.9.3 THE LOW-FREQUENCY RESPONSE 497 5.9.4 A FINAL REMARK 503 5.10 THE BASIC BJT DIGITAL LOGIC INVERTER 503 5.10.1 THE VOLTAGE TRANSFER CHARACTERISTIC 504 5.10.2 SATURATED VERSUS NONSATURATED BJT DIGITAL CIRCUITS 505 5.11 THE SPICE BJT MODEL AND SIMULATION EXAMPLES 507 5.11.1 THE SPICE EBERS-MOLL MODEL OF THE BJT 507 5.11.2 THE SPICE GUMMEL-POON MODEL OF THE BJT 509 5.11.3 THE SPICE BJT MODEL PARAMETERS 510 5.11.4 THE BJT MODEL PARAMETERS BF AND BR IN SPICE 510 DETAILED TABLE OF CONTENTS SUMMARY 516 PROBLEMS 517 __ ANALOG AND DIGITAL INTEGRATED * PART II CIRCUITS 542 6 SINGLE-STAGE INTEGRATED-CIRCUIT AMPLIFIERS 545 INTRODUCTION 545 6.1 IC DESIGN PHILOSOPHY 546 6.2 COMPARISONOFTHEMOSFETANDTHEBJT 547 6.2.1 TYPICAL VALUES OF MOSFET PARAMETERS 547 6.2.2 TYPICAL VALUES OF IC BJT PARAMETERS 548 6.2.3 COMPARISON OF IMPORTANT CHARACTERISTICS 550 6.2.4 COMBINING MOS AND BIPOLAR TRANSISTORSBICMOS CIRCUITS 561 6.2.5 VALIDITY OF THE SQUARE-LAW MOSFET MODEL 562 6.3 IC BIASINGCURRENT SOURCES, CURRENT MIRRORS, AND CURRENT-STEERING CIRCUITS 562 6.3.1 THE BASIC MOSFET CURRENT SOURCE 562 6.3.2 MOS CURRENT-STEERING CIRCUITS 565 6.3.3 BJT CIRCUITS 567 6.4 HIGH-FREQUENCY RESPONSEGENERAL CONSIDERATIONS 571 6.4.1 THE HIGH-FREQUENCY GAIN FUNCTION 572 6.4.2 DETERMINING THE 3-DB FREQUENCY/ W 573 6.4.3 USING OPEN-CIRCUIT TIME CONSTANTS FOR THE APPROXIMATE DETERMINATION OFF H 575 6.4.4 MILLER S THEOREM 578 6.5 THE COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS WITH ACTIVE LOADS 582 6.5.1 THE COMMON-SOURCE CIRCUIT 582 6.5.2 CMOS IMPLEMENTATION OF THE COMMON-SOURCE AMPLIFIER 583 6.5.3 THE COMMON-EMITTER CIRCUIT 588 6.6 HIGH-FREQUENCY RESPONSE OF THE CS AND CE AMPLIFIERS 588 6.6.1 ANALYSIS USING MILLER S THEOREM 589 6.6.2 ANALYSIS USING OPEN-CIRCUIT TIME CONSTANTS 590 6.6.3 EXACT ANALYSIS 591 6.6.4 ADAPTING THE FORMULAS FOR THE CASE OF THE CE AMPLIFIER 595 6.6.5 THE SITUATION WHEN R, IG IS LOW 597 6.7 THE COMMON-GATE AND COMMON-BASE AMPLIFIERS WITH ACTIVE LOADS 600 6.7.1 THE COMMON-GATE AMPLIFIER 600 6.7.2 THE COMMON-BASE AMPLIFIER 610 6.7.3 A CONCLUDING REMARK 613 6.8 THE CASCODE AMPLIFIER 613 6.8.1 THE MOS CASCODE 614 6.8.2 FREQUENCY RESPONSE OF THE MOS CASCODE 618 6.8.3 THE BJT CASCODE 623 6.8.4 A CASCODE CURRENT SOURCE 625 6.8.5 DOUBLE CASCODING 626 6.8.6 THE FOLDED CASCODE 627 6.8.7 BICMOS CASCODES 628 DETAILED TABLE OF CONTENTS !_: X 6.9 THE CS AND CE AMPLIFIERS WITH SOURCE (EMITTER) DEGENERATION 629 6.9.1 THE CS AMPLIFIER WITH A SOURCE RESISTANCE 629 6.9.2 THE CE AMPLIFIER WITH AN EMITTER RESISTANCE 633 6.10 THE SOURCE AND EMITTER FOLLOWERS 635 6.10.1 THE SOURCE FOLLOWER 635 6.10.2 FREQUENCY RESPONSE OF THE SOURCE FOLLOWER 637 6.10.3 THE EMITTER FOLLOWER 639 6.11 SOME USEFUL TRANSISTOR PAIRINGS 641 ~~ 6.11.1 THE CD - CS, CC-CE AND CD-CE CONFIGURATIONS 641 6.11.2 THE DARLINGTON CONFIGURATION 645 6.11.3 THE CC-CB AND CD-CG CONFIGURATIONS 646 6.12 CURRENT-MIRROR CIRCUITS WITH IMPROVED PERFORMANCE 649 6.12.1 CASCODE MOS MIRRORS 649 6.12.2 A BIPOLAR MIRROR WITH BASE-CURRENT COMPENSATION 650 6.12.3 THE WILSON CURRENT MIRROR 651 6.12.4 THE WILSON MOS MIRROR 652 6.12.5 THE WIDLAR CURRENT SOURCE 653 6.13 SPICE SIMULATION EXAMPLES 656 SUMMARY 665 PROBLEMS 666 7 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS 687 INTRODUCTION 687 7.1 THE MOS DIFFERENTIAL PAIR 688 7.1.1 OPERATION WITH A COMMON-MODE INPUT VOLTAGE 689 7.1.2 OPERATION WITH A DIFFERENTIAL INPUT VOLTAGE 691 7.1.3 LARGE-SIGNAL OPERATION 693 7.2 SMALL-SIGNAL OPERATION OF THE MOS DIFFERENTIAL PAIR 696 7.2.1 DIFFERENTIAL GAIN 697 7.2.2 COMMON-MODE GAIN AND COMMON-MODE REJECTION RATIO (CMRR) 700 7.3 THE BJT DIFFERENTIAL PAIR 704 7.3.1 BASIC OPERATION 704 7.3.2 LARGE-SIGNAL OPERATION 707 7.3.3 SMALL-SIGNAL OPERATION 709 7.4 OTHER NONIDEAL CHARACTERISTICS OF THE DIFFERENTIAL AMPLIFIER 720 7.4.1 INPUT OFFSET VOLTAGE OF THE MOS DIFFERENTIAL PAIR 720 7.4.2 INPUT OFFSET VOLTAGE OF THE BIPOLAR DIFFERENTIAL PAIR 723 7.4.3 INPUT BIAS AND OFFSET CURRENTS OF THE BIPOLAR PAIR 725 1.4.4 INPUT COMMON-MODE RANGE 726 7.4.5 A CONCLUDING REMARK 726 7.5 THE DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD 727 7.5.1 DIFFERENTIAL-TO-SINGLE-ENDEDCONVERSION 727 7.5.2 THE ACTIVE-LOADED MOS DIFFERENTIAL PAIR 728 7.5.3 DIFFERENTIAL GAIN OF THE ACTIVE-LOADED MOS PAIR 729 7.5.4 COMMON-MODE GAIN AND CMRR 732 7.5.5 THE BIPOLAR DIFFERENTIAL PAIR WITH ACTIVE LOAD 733 XIV J- : DETAILED TABLE OF CONTENTS 7.6 FREQUENCY RESPONSE OF THE DIFFERENTIAL AMPLIFIER 740 7.6.1 ANALYSIS OF THE RESISTIVELY LOADED MOS AMPLIFIER 740 7.6.2 ANALYSIS OF THE ACTIVE-LOADED MOS AMPLIFIER 744 1.1 MULTISTAGE AMPLIFIERS 749 7.7.1 A TWO-STAGE CMOS OP AMP 749 7.7.2 A BIPOLAR OP AMP 758 7.8 SPICE SIMULATION EXAMPLE 767 SUMMARY 773 PROBLEMS 775 8 FEEDBACK 791 INTRODUCTION 791 8.1 THE GENERAL FEEDBACK STRUCTURE 792 8.2 SOME PROPERTIES OF NEGATIVE FEEDBACK 795 8.2.1 GAIN DESENSITIVITY 795 8.2.2 BANDWIDTH EXTENSION 795 8.2.3 NOISE REDUCTION 796 8.2.4 REDUCTION IN NONLINEAR DISTORTION 797 8.3 THE FOUR BASIC FEEDBACK TOPOLOGIES 798 8.3.1 VOLTAGE AMPLIFIERS 799 8.3.2 CURRENT AMPLIFIERS 799 8.3.3 TRANSCONDUCTANCE AMPLIFIERS 801 8.3.4 TRANSRESISTANCE AMPLIFIERS #02 8.4 THE SERIES-SHUNT FEEDBACK AMPLIFIER 802 8.4.1 THE IDEAL SITUATION 802 8.4.2 THE PRACTICAL SITUATION 804 8.4.3 SUMMARY 07 8.5 THE SERIES-SERIES FEEDBACK AMPLIFIER 811 8.5.1 THE IDEAL CASE 811 8.5.2 THE PRACTICAL CASE 812 8.5.3 SUMMARY 814 8.6 THE SHUNT-SHUNT AND SHUNT-SERIES FEEDBACK AMPLIFIERS 818 8.6.1 THE SHUNT-SHUNT CONFIGURATION 819 8.6.2 AN IMPORTANT NOTE 23 8.6.3 THE SHUNT-SERIES CONFIGURATION 823 8.6.4 SUMMARY OF RESULTS 831 8.7 DETERMINING THE LOOP GAIN 831 8.7.1 AN ALTERNATIVE APPROACH FOR FINDING ASS 831 8.7.2 EQUIVALENCE OF CIRCUITS FROM A FEEDBACK-LOOP POINT OF VIEW 833 8.8 THE STABILITY PROBLEM 834 8.8.1 TRANSFER FUNCTION OF THE FEEDBACK AMPLIFIER 834 8.8.2 THE NYQUIST PLOT 835 8.9 EFFECT OF FEEDBACK ON THE AMPLIFIER POLES 836 8.9.1 STABILITY AND POLE LOCATION 837 8.9.2 POLES OF THE FEEDBACK AMPLIFIER 838 8.9.3 AMPLIFIER WITH SINGLE-POLE RESPONSE 838 8.9.4 AMPLIFIER WITH TWO-POLE RESPONSE 839 8.9.5 AMPLIFIERS WITH THREE OR MORE POLES 843 DETAILED TABLE OF CONTENTS XV 8.10 STABILITY STUDY USING BODE PLOTS 845 8.10.1 GAIN AND PHASE MARGINS 845 8.10.2 EFFECT OF PHASE MARGIN ON CLOSED-LOOP RESPONSE 846 8.10.3 AN ALTERNATIVE APPROACH FOR INVESTIGATING STABILITY 847 8.11 FREQUENCY COMPENSATION 849 8.11.1 THEORY 850 8.11.2 IMPLEMENTATION 851 8.11.3 MILLER COMPENSATION AND POLE SPLITTING 852 8.12 SPICE SIMULATION EXAMPLE 855 SUMMARY 859 PROBLEMS 860 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS 871 INTRODUCTION 871 9.1 THE TWO-STAGE CMOS OP AMP 872 9.1.1 THE CIRCUIT 872 9.1.2 INPUT COMMON-MODE RANGE AND OUTPUT SWING 873 9.1.3 VORTAGE GAIN 874 9.1.4 FREQUENCY RESPONSE 876 9.1.5 SLEWRATE 879 9.2 THE FOLDED-CASCODE CMOS OP AMP 883 9.2.1 THE CIRCUIT 883 9.2.2 INPUT COMMON-MODE RANGE AND THE OUTPUT VOLTAGE SWING 885 9.2.3 VOLTAGE GAIN 886 9.2.4 FREQUENCY RESPONSE 888 9.2.5 SLEWRATE 888 9.2.6 INCREASING THE INPUT COMMON-MODE RANGE: RAIL-TO-RAIL INPUT OPERATION 890 9.2.7 INCREASING THE OUTPUT VOLTAGE RANGE: THE WIDE-SWING CURRENT MIRROR 892 9.3 THE 741 OP-AMP CIRCUIT 893 9.3.1 BIAS CIRCUIT 893 9.3.2 SHORT-CIRCUIT PROTECTION CIRCUITRY 895 9.3.3 THE INPUT STAGE 895 9.3.4 THE SECOND STAGE 895 9.3.5 THE OUTPUT STAGE 896 9.3.6 DEVICE PARAMETERS 898 9.4 DC ANALYSISOFTHE741 899 9.4.1 REFERENCE BIAS CURRENT 899 9.4.2 INPUT-STAGE BIAS 899 9.4.3 INPUT BIAS AND OFFSET CURRENTS 902 9.4.4 INPUT OFFSET VOLTAGE 902 9.4.5 INPUT COMMON-MODE RANGE 902 9.4.6 SECOND-STAGE BIAS 902 9.4.7 OUTPUT-STAGE BIAS 903 9.4.8 SUMMARY 904 9.5 SMALL-SIGNAL ANALYSIS OF THE 741 905 9.5.1 THE INPUT STAGE 905 9.5.2 THE SECOND STAGE 910 9.5.3 THE OUTPUT STAGE 912 CONTENTS 9.6 GAIN, FREQUENCY RESPONSE, AND SLEW RATE OF THE 741 917 9.6.1 SMALL-SIGNAL GAIN 917 9.6.2 FREQUENCY RESPONSE 917 9.6.3 A SIMPLIFIED MODEL 918 9.6.4 SLEW RATE 919 9.6.5 RELATIONSHIP BETWEEN/, AND SR 920 9.7 DATA CONVERTERSAN INTRODUCTION 922 9.7.1 DIGITAL PROCESSING OF SIGNALS 922 9.7.2 SAMPLING OF ANALOG SIGNALS 922 9.7.3 SIGNAL QUANTIZATION 924 9.7 .4 THE A/D AND D/A CONVERTERS AS FUNCTIONAL BLOCKS 924 9.8 D/A CONVERTER CIRCUITS 925 9.8.1 BASIC CIRCUIT USING BINARY-WEIGHTED RESISTORS 925 9.8.2 #-2AE LADDERS 926 9.8.3 A PRACTICAL CIRCUIT IMPLEMENTATION 927 9.8.4 CURRENT SWITCHES 928 9.9 A/D CONVERTER CIRCUITS 929 9.9.1 THE FEEDBACK-TYPE CONVERTER 929 9.9.2 THE DUAL-SLOPE A/D CONVERTER 930 9.9.3 THE PARALLEL OR FLASH CONVERTER 932 9.9.4 THE CHARGE-REDISTRIBUTION CONVERTER 932 9.10 SPICE SIMULATION EXAMPLE 934 SUMMARY 940 PROBLEMS 941 DIGITAL CMOS LOGIC CIRCUITS 949 INTRODUCTION 949 10.1 DIGITAL CIRCUIT DESIGN: AN OVERVIEW 950 10.1.1 DIGITAL IC TECHNOLOGIES AND LOGIC-CIRCUIT FAMILIES 950 10.1.2 LOGIC-CIRCUIT CHARACTERIZATION 952 10.1.3 STYLES FOR DIGITAL SYSTEM DESIGN 954 10.1.4 DESIGN ABSTRACTION AND COMPUTER AIDS 955 10.2 DESIGN AND PERFORMANCE ANALYSIS OF THE CMOS INVERTER 955 10.2.1 CIRCUIT STRUCTURE 955 10.2.2 STATIC OPERATION 956 10.2.3 DYNAMIC OPERATION 958 10.2.4 DYNAMIC POWER DISSIPATION 961 10.3 CMOS LOGIC-GATE CIRCUITS 963 10.3.1 BASIC STRUCTURE 963 10.3.2 THE TWO-INPUT NOR GATE 966 10.3.3 THE TWO-INPUT NAND GATE 966 10.3.4 A COMPLEX GATE 967 10.3.5 OBTAINING THE PUN FROM THE PDN AND VICE VERSA 968 10.3.6 THE EXCLUSIVE-OR FUNCTION 969 10.3.7 SUMMARY OF THE SYNTHESIS METHOD 970 10.3.8 TRANSISTOR SIZING 970 10.3.9 EFFECTS OF FAN-IN AND FAN-OUT ON PROPAGATION DELAY 973 10.4 PSEUDO-NMOS LOGIC CIRCUITS 974 10.4.1 THE PSEUDO-NMOS INVERTER 974 10.4.2 STATIC CHARACTERISTICS 975 DETAILED TABLE OF CONTENTS 10.4.3 DERIVATION OF THE VTC 976 10.4.4 DYNAMIC OPERATION 979 10.4.5 DESIGN 979 10.4.6 GATE CIRCUITS 980 10.4.7 CONCLUDING REMARKS 980 PASS-TRANSISTOR LOGIC CIRCUITS 982 10.5.1 AN ESSENTIAL DESIGN REQUIREMENT 983 10.5.2 OPERATION WITH NMOS TRANSISTORS AS SWITCHES 984 10.5.3 THE USE OF CMOS TRANSMISSION GATES AS SWITCHES 988 10.5.4 PASS-TRANSISTOR LOGIC CIRCUIT EXAMPLES 990 10.5.5 A FINAL REMARK 991 DYNAMIC LOGIC CIRCUITS 991 10.6.1 BASIC PRINCIPLE 992 10.6.2 NONIDEAL EFFECTS 993 10.6.3 DOMINO CMOS LOGIC 996 10.6.4 CONCLUDING REMARKS 998 SPIEE SIMULATION EXAMPLE 998 SUMMARY 1002 PROBLEMS 1002 PART I SELECTED TOPICS 1010 11 MEMORY AND ADVANCED DIGITAL CIRCUITS 1013 INTRODUCTION 1013 11.1 LATCHES AND FLIP-FLOPS 1014 11.1.1 THELATCH 1014 11.1.2 THE SR FLIP-FLOP 1015 11.1.3 CMOS IMPLEMENTATION OF SR FLIP-FLOPS 1016 11. 1 .4 A SIMPLER CMOS IMPLEMENTATION OF THE CLOCKED SR FLIP- FLOP 1019 11.1.5 D FLIP-FLOP CIRCUITS 1019 11.2 MULTIVIBRATOR CIRCUITS 1021 11.2.1 A CMOS MONOSTABLE CIRCUIT 1022 11.2.2 AN ASTABLE CIRCUIT 1026 11.2.3 THE RING OSCILLATOR 1027 11.3 SEMICONDUCTOR MEMORIES: TYPES AND ARCHITECTURES 1028 11.3.1 MEMORY-CHIP ORGANIZATION 1028 11.3.2 MEMORY-CHIP TIMING 1030 11.4 RANDOM- ACCESS MEMORY (RAM) CELLS 1031 11.4.1 STATIC MEMORY CELL 1031 11.4.2 DYNAMIC MEMORY CELL 1036 1 1.5 SENSE AMPLIFIERS AND ADDRESS DECODERS 1038 11.5.1 THE SENSE AMPLIFIER 1038 11.5.2 THE ROW-ADDRESS DECODER 1043 11.5.3 THE COLUMN-ADDRESS DECODER 1045 11.6 READ-ONLY MEMORY (ROM) 1046 11.6.1 A MOS ROM 1047 11.6.2 MASK-PROGRAMMABLE ROMS 1049 11.6.3 PROGRAMMABLE ROMS (PROMS AND EPROMS) 1049 10.5 10.6 10.7 OF CONTENTS 11.7 EMITTER-COUPLED LOGIC (ECL) 1052 11.7.1 THE BASIC PRINCIPLE 1052 11.7.2 ECLFAMILIES 1053 11.7.3 THE BASIC GATE CIRCUIT 1053 11.7.4 VORTAGE TRANSFER CHARACTERISTICS 1057 11.7.5 FAN-OUT 1061 1 1.7.6 SPEED OF OPERATION AND SIGNAL TRANSMISSION 1062 11.7.7 POWER DISSIPATION 1063 11.7.8 THERMAL EFFECTS 1063 11.7.9 THE WIRED-OR CAPABILITY 1066 11.7.10 SOME FINAL REMARKS 1066 11.8 BICMOS DIGITAL CIRCUITS 1067 11.8.1 THE BICMOS INVERTER 1067 11.8.2 DYNAMIC OPERATION 1069 11.8.3 BICMOS LOGIC GATES 1070 11.9 SPICE SIMULATION EXAMPLE 1071 SUMMARY 1076 PROBLEMS 1077 FILTERS AND TUNED AMPLIFIERS 1083 INTRODUCTION 1083 12.1 FILTER TRANSMISSION, TYPES, AND SPECIFICATION 1084 12.1.1 FILTER TRANSMISSION 1084 12.1.2 FILTER TYPES 1085 12.1.3 FILTER SPECIFICATION 1085 12.2 THE FILTER TRANSFER FUNCTION 1088 12.3 BUTTERWORTH AND CHEBYSHEV FILTERS 1091 12.3.1 THE BUTTERWORTH FILTER 1091 12.3.2 THE CHEBYSHEV FILTER 1095 12.4 FIRST-ORDER AND SECOND-ORDER FILTER FUNCTIONS 1098 12.4.1 FIRST-ORDER FILTERS 1098 12.4.2 SECOND-ORDER FILTER FUNCTIONS 1101 12.5 THE SECOND-ORDER LCR RESONATOR 1106 12.5.1 THE RESONATOR NATURAL MODES 1106 12.5.2 REALIZATION OF TRANSMISSION ZEROS 1107 12.5.3 REALIZATION OF THE LOW-PASS FUNCTION 7705 12.5.4 REALIZATION OF THE HIGH-PASS FUNCTION 1108 12.5.5 REALIZATION OF THE BANDPASS FUNCTION 1108 1 2.5.6 REALIZATION OF THE NOTCH FUNCTIONS 1110 12.5.7 REALIZATION OF THE ALL-PASS FUNCTION 1111 12.6 SECOND-ORDER ACTIVE FILTERS BASED ON INDUCTOR REPLACEMENT 1112 12.6.1 THE ANTONIOU INDUCTANCE-SIMULATION CIRCUIT 1112 12.6.2 THE OPAMP-RC RESONATOR 1114 12.6.3 REALIZATION OF THE VARIOUS FILTER TYPES 1114 12.6.4 THE ALL-PASS CIRCUIT 1118 12.7 SECOND-ORDER ACTIVE FILTERS BASED ON THE TWO-INTEGRATOR-LOOP TOPOLOGY 1120 12.7.1 DERIVATION OF THE TWO-INTEGRATOR-LOOP BIQUAD 1120 12.7.2 CIRCUIT IMPLEMENTATION 1122 DETAILED TABLE OF CONTENTS * * XIX 12.7.3 AN ALTERNATIVE TWO-INTEGRATOR-LOOP BIQUAD CIRCUIT 1123 12JA FINAL REMARKS 1125 12.8 SINGLE-AMPLIFIER BIQUADRATIC ACTIVE FILTERS 1125 12.8.1 SYNTHESIS OF THE FEEDBACK LOOP 1126 12.8.2 INJECTING THE INPUT SIGNAL 1128 12.8.3 GENERATION OF EQUIVALENT FEEDBACK LOOPS 1130 12.9 SENSITIVITY 1133 12.10 SWITCHED-CAPACITOR FILTERS 1136 12.10.1 THE BASIC PRINCIPLE 1136 12.10.2 PRACTICAL CIRCUITS 1137 12.10.3 A FINAL REMARK 1141 12.11 TUNED AMPLIFIERS 1141 12.11.1 THE BASIC PRINCIPLE 1141 12.11.2 INDUCTOR LOSSES 1143 12.11.3 USE OF TRANSFORMERS 1144 12.11.4 AMPLIFIERS WITH MULTIPLE TUNED CIRCUITS 1145 12.11.5 THE CASCODE AND THE CC-CB CASCADE 1146 12.11.6 SYNCHRONOUS TUNING 1147 12.11.7 STAGGER-TUNING 1148 12.12 SPICE SIMULATION EXAMPLES 1152 SUMMARY 1158 PROBLEMS 1159 13 SIGNAL GENERATORS AND WAVEFORM-SHAPING CIRCUITS 1165 INTRODUCTION 1165 13.1 BASIC PRINCIPLES OF SINUSOIDAL OSCILLATORS 1166 13.1.1 THE OSCILLATOR FEEDBACK LOOP 1166 13.1.2 THE OSCILLATION CRITERION 1167 13.1.3 NONLINEAR AMPLITUDE CONTROL 1168 13.1.4 A POPULAER LIMITER CIRCUIT FOR AMPLITUDE CONTROL 1169 13.2 OP AMP-RC OSCILLATOR CIRCUITS 1171 13.2.1 THE WIEN-BRIDGE OSCILLATOR 1171 13.2.2 THE PHASE-SHIFT OSCILLATOR 1174 13.2.3 THE QUADRATURE OSCILLATOR 1176 13.2.4 THE ACTIVE-FILTER-TUNED OSCILLATOR 1177 13.2.5 A FINAL REMARK 7/79 13.3 LC AND CRYSTAL OSCILLATORS 1179 13.3.1 LC-TUNED OSCILLATORS 1179 13.3.2 CRYSTAL OSCILLATORS 1182 13.4 BISTABLE MULTIVIBRATORS 1185 13.4.1 THE FEEDBACK LOOP 1185 13.4.2 TRANSFER CHARACTERISTICS OF THE BISTABLE CIRCUIT 1186 13.4.3 TRIGGERING THE BISTABLE CIRCUIT 1187 13.4.4 THE BISTABLE CIRCUIT AS A MEMORY ELEMENT 1188 13.4.5 A BISTABLE CIRCUIT WITH NONINVERTING TRANSFER CHARACTERISTICS 1188 13.4.6 APPLICATION OF THE BISTABLE CIRCUIT AS A COMPARATOR 1189 13.4.7 MAKING THE OUTPUT LEVELS MORE PRECISE 1191 X X WM DETAILE D TABLE OF CONTENTS 13.5 GENERATION OF SQUARE AND TRIANGULAER WAVEFORMS USING ASTABLE MULTIVIBRATORS 1192 13.5.1 OPERATION OF THE ASTABLE MULTIVIBRATOR 1192 13.5.2 GENERATION OF TRIANGULAER WAVEFORMS 1194 13.6 GENERATION OF A STANDARDIZED PULSE*THE MONOSTABLE MULTIVIBRATOR 1196 13.7 INTEGRATED-CIRCUIT TIMERS 1198 13.7.1 THE 555 CIRCUIT 1198 13.7.2 IMPLEMENTING A MONOSTABLE MULTIVIBRATOR USING THE 555 IC 1199 13.7.3 AN ASTABLE MULTIVIBRATOR USING THE 555 IC 1201 13.8 NONLINEAR WAVEFORM-SHAPING CIRCUITS 1203 13.8.1 THE BREAKPOINT METHOD 1203 13.8.2 THE NONLINEAR-AMPLIFICATION METHOD 1205 13.9 PRECISION RECTIFIER CIRCUITS 1206 13.9.1 PRECISION HALF-WAVE RECTIFIER-THE SUPERDIODE 1207 13.9.2 AN ALTERNATIVE CIRCUIT 1208 13.9.3 AN APPLICATION: MEASURING AC VOLTAGES 1209 13.9.4 PRECISION FULL-WAVE RECTIFIER 1210 13.9.5 A PRECISION BRIDGE RECTIFIER FOR INSTRUMENTATION APPLICATIONS 1212 13.9.6 PRECISION PEAK RECTIFIERS 1213 13.9.7 A BUFFERED PRECISION PEAK DETECTOR 1213 13.9.8 A PRECISION CLAMPING CIRCUIT 1214 13.10 SPICE SIMULATION EXAMPLES 1214 SUMMARY 1219 PROBLEMS 1220 14 OUTPUT STAGES AND POWER AMPLIFIERS 1229 INTRODUCTION 1229 14.1 CLASSIFICATION OF OUTPUT STAGES 1230 14.2 CLASS A OUTPUT STAGE 1231 14.2.1 TRANSFER CHARACTERISTIC 1231 14.2.2 SIGNAL WAVEFORMS 1233 14.2.3 POWER DISSIPATION 1233 14.2.4 POWER-CONVERSION EFFICIENCY 1235 14.3 CLASS B OUTPUT STAGE 2235 14.3.1 CIRCUIT OPERATION 1236 14.3.2 TRANSFER CHARACTERISTIC 1236 14.3.3 POWER-CONVERSION EFFICIENCY 2236 14.3.4 POWER DISSIPATION 1238 14.3.5 REDUCING CROSSOVER DISTORTION 1240 14.3.6 SINGLE-SUPPLY OPERATION 1240 14.4 CLASS AB OUTPUT STAGE 724/ 14.4.1 CIRCUIT OPERATION 1242 14.4.2 OUTPUT RESISTANCE 1243 14.5 BIASING THE CLASS AB CIRCUIT 7244 14.5.1 BIASING USING DIODES 1244 14.5.2 BIASING USING THE V BE MULTIPLIER 1246 14.6 POWER BJTS 1249 14.6.1 JUNCTION TEMPERATURE 1249 14.6.2 THERMAL RESISTANCE 1249 DETAILED TABLE OF CONTENTS 14.6.3 POWER DISSIPATION VERSUS TEMPERATURE 1250 14.6.4 TRANSISTOR CASE AND HEAT SINK 1251 14.6.5 THE BJT SAFE OPERATING AREA 1254 14.6.6 PARAMETER VALUES OF POWER TRANSISTORS 1255 14.7 VARIATIONS ON THE CLASS AB CONFIGURATION 1256 14.7.1 USEOFLNPUT EMITTER FOLLOWERS 1256 14.7.2 USEOF COMPOUND DEVICES 1257 14.7.3 SHORT-CIRCUIT PROTECTION 1259 14.7 .4 THERMAL SHUTDOWN 1260 14.8 IC POWER AMPLIFIERS 1261 14.8.1 A FIXED-GAIN IC POWER AMPLIFIER 1261 14.8.2 POWER OPAMPS 1265 14.8.3 THE BRIDGE AMPLIFIER 1265 14.9 MOS POWER TRANSISTORS 1266 14.9.1 STRUCTUREOF THE POWER MOSFET 1266 14.9.2 CHARACTERISTICS OF POWER MOSFETS 1268 14.9.3 TEMPERATURE EFFECTS 1269 14.9.4 COMPARISON WITH BJTS 1269 14.9.5 A CLASS AB OUTPUT STAGE UTILIZING MOSFETS 1270 14.10 SPICE SIMULATION EXAMPLE 1271 SUMMARY 1276 PROBLEMS 1277 APPENDIXES A VLSI FABRICATION TECHNOLOGY A-1 B TWO-PORT NETWORK PARAMETERS B-1 C SOME USEFUL NETWORK THEOREMS C-1 D SINGLE-TIME-CONSTANT CIRCUITS D-1 E S-DOMAIN ANALYSIS: POLES, ZEROS, AND BODE PLOTS E-1 F BIBLIOGRAPHY F-1 G STANDARD RESISTANCE VALUES AND UNIT PREFIXES G-1 H ANSWERS TO SELECTED PROBLEMS H-1 INDEX IN-1
any_adam_object	1
author	Sedra, Adel S.
author_facet	Sedra, Adel S.
author_role	aut
author_sort	Sedra, Adel S.
author_variant	a s s as ass
building	Verbundindex
bvnumber	BV019357327
callnumber-first	T - Technology
callnumber-label	TK7867
callnumber-raw	TK7867
callnumber-search	TK7867
callnumber-sort	TK 47867
callnumber-subject	TK - Electrical and Nuclear Engineering
classification_rvk	ZN 4900
classification_tum	ELT 430f ELT 340f
ctrlnum	(OCoLC)53223719 (DE-599)BVBBV019357327
dewey-full	621.381
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.381
dewey-search	621.381
dewey-sort	3621.381
dewey-tens	620 - Engineering and allied operations
discipline	Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik
edition	5. ed.
format	Book
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genre	1\p (DE-588)4151278-9 Einführung gnd-content
genre_facet	Einführung
id	DE-604.BV019357327
illustrated	Illustrated
indexdate	2024-07-09T19:58:25Z
institution	BVB
isbn	0195142519
language	English
lccn	2003066178
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-012821179
oclc_num	53223719
open_access_boolean
owner	DE-573 DE-91 DE-BY-TUM DE-83
owner_facet	DE-573 DE-91 DE-BY-TUM DE-83
physical	Getr. Zählung Ill., graph. Darst. 1 CD-ROM (12 cm)
publishDate	2004
publishDateSearch	2004
publishDateSort	2004
publisher	Oxford Univ. Press
record_format	marc
series2	The Oxford series in electrical and computer engineering
spelling	Sedra, Adel S. Verfasser aut Microelectronic circuits Adel S. Sedra ; Kenneth C. Smith 5. ed. New York Oxford Univ. Press 2004 Getr. Zählung Ill., graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier The Oxford series in electrical and computer engineering Electronic circuits Integrated circuits Elektronische Schaltung (DE-588)4113419-9 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Mikroelektronik (DE-588)4039207-7 gnd rswk-swf 1\p (DE-588)4151278-9 Einführung gnd-content Mikroelektronik (DE-588)4039207-7 s Integrierte Schaltung (DE-588)4027242-4 s Elektronische Schaltung (DE-588)4113419-9 s 2\p DE-604 DE-604 Smith, Kenneth Carless Sonstige oth GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012821179&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk
spellingShingle	Sedra, Adel S. Microelectronic circuits Electronic circuits Integrated circuits Elektronische Schaltung (DE-588)4113419-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Mikroelektronik (DE-588)4039207-7 gnd
subject_GND	(DE-588)4113419-9 (DE-588)4027242-4 (DE-588)4039207-7 (DE-588)4151278-9
title	Microelectronic circuits
title_auth	Microelectronic circuits
title_exact_search	Microelectronic circuits
title_full	Microelectronic circuits Adel S. Sedra ; Kenneth C. Smith
title_fullStr	Microelectronic circuits Adel S. Sedra ; Kenneth C. Smith
title_full_unstemmed	Microelectronic circuits Adel S. Sedra ; Kenneth C. Smith
title_short	Microelectronic circuits
title_sort	microelectronic circuits
topic	Electronic circuits Integrated circuits Elektronische Schaltung (DE-588)4113419-9 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Mikroelektronik (DE-588)4039207-7 gnd
topic_facet	Electronic circuits Integrated circuits Elektronische Schaltung Integrierte Schaltung Mikroelektronik Einführung
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=012821179&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT sedraadels microelectroniccircuits AT smithkennethcarless microelectroniccircuits

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